-------------------------------------------------------------------------------
-- Title      : Testbench for design "TLMU"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : TLMU_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2010-11-08
-- Last update: 2010-11-08
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2010 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2010-11-08  1.0      tkrawuts	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity TLMU_tb is

end TLMU_tb;

-------------------------------------------------------------------------------

architecture fut of TLMU_tb is

  component TLMU
    generic (
      version_id : std_logic_vector;
      padCol     : positive;
      padRow     : positive);
    port (
      RESET_A    : in    std_logic;
      CLK40_A    : in    std_logic;
      SCSN_IN_A  : in    std_logic;
      SCSN_OUT_A : out   std_logic;
      T_A        : out   std_logic_vector (7 downto 0);
      SPA_A      : in    std_logic;
      SPB_A      : in    std_logic;
      SPC_A      : out   std_logic;
      SPD_A      : out   std_logic;
      EN_A       : in    std_logic;
      RESET_B    : in    std_logic;
      CLK40_B    : in    std_logic;
      SCSN_IN_B  : in    std_logic;
      SCSN_OUT_B : out   std_logic;
      T_B        : out   std_logic_vector (7 downto 0);
      SPA_B      : in    std_logic;
      SPB_B      : in    std_logic;
      SPC_B      : out   std_logic;
      SPD_B      : out   std_logic;
      EN_B       : in    std_logic;
      LED        : out   std_logic_vector (8 downto 1);
      SA         : in    std_logic_vector(padCol*padRow-1 downto 0);
      SB         : in    std_logic_vector(padCol*padRow-1 downto 0);
      T_Data     : inout std_logic;
      T_Clk      : out   std_logic);
  end component;

  constant p40  : time := 12500 ps;
  -- component generics
  constant version_id : std_logic_vector := x"00010001";
  constant padCol     : positive         := 8;
  constant padRow     : positive         := 36;

  -- component ports
  signal RESET_A    : std_logic;
  signal CLK40_A    : std_logic:='0';
  signal SCSN_IN_A  : std_logic;
  signal SCSN_OUT_A : std_logic;
  signal T_A        : std_logic_vector (7 downto 0);
  signal SPA_A      : std_logic;
  signal SPB_A      : std_logic;
  signal SPC_A      : std_logic;
  signal SPD_A      : std_logic;
  signal EN_A       : std_logic;
  signal RESET_B    : std_logic;
  signal CLK40_B    : std_logic;
  signal SCSN_IN_B  : std_logic;
  signal SCSN_OUT_B : std_logic;
  signal T_B        : std_logic_vector (7 downto 0);
  signal SPA_B      : std_logic;
  signal SPB_B      : std_logic;
  signal SPC_B      : std_logic;
  signal SPD_B      : std_logic;
  signal EN_B       : std_logic;
  signal LED        : std_logic_vector (8 downto 1);
  signal SA         : std_logic_vector(padCol*padRow-1 downto 0);
  signal SB         : std_logic_vector(padCol*padRow-1 downto 0);
  signal T_Data     : std_logic;
  signal T_Clk      : std_logic;

  -- clock

  signal triggerin  : std_logic_vector(575 downto 0);
begin  -- fut
  

  -- component instantiation
  DUT: TLMU
    generic map (
      version_id => version_id,
      padCol     => padCol,
      padRow     => padRow)
    port map (
      RESET_A    => RESET_A,
      CLK40_A    => CLK40_A,
      SCSN_IN_A  => SCSN_IN_A,
      SCSN_OUT_A => SCSN_OUT_A,
      T_A        => T_A,
      SPA_A      => SPA_A,
      SPB_A      => SPB_A,
      SPC_A      => SPC_A,
      SPD_A      => SPD_A,
      EN_A       => EN_A,
      RESET_B    => RESET_B,
      CLK40_B    => CLK40_B,
      SCSN_IN_B  => SCSN_IN_B,
      SCSN_OUT_B => SCSN_OUT_B,
      T_B        => T_B,
      SPA_B      => SPA_B,
      SPB_B      => SPB_B,
      SPC_B      => SPC_B,
      SPD_B      => SPD_B,
      EN_B       => EN_B,
      LED        => LED,
      SA         => SA,
      SB         => SB,
      T_Data     => T_Data,
      T_Clk      => T_Clk);

  -- clock generation

  CLK40_A <= not CLK40_A after p40;
  -- waveform generation
  WaveGen_Proc: process
  begin
    RESET_A   <= '1';
    SPA_A     <= '0';
    SPB_A     <= '0';
    EN_A      <= '1';
    RESET_B   <= '0';
    CLK40_B   <= '0';
    SCSN_IN_B <= '1';
    SPA_B     <= '0';
    SPB_B     <= '0';
    EN_B      <= '0';



    triggerin <= (575 downto 0 => '0');
--    SA        <= (others => '0');
--    SB        <= (others => '0');
    T_Data    <= '1';
    T_Clk     <= '1';
    wait for 2 us;
    RESET_A   <= '0';
    wait for 1 us;
    RESET_A   <= '1';
    wait for 1 us;
    RESET_A   <= '0';
    wait for 50 us;
--    SA        <= (others => '1');
    wait for 2*p40;
--    SA        <= (others => '0');    
    wait for 2*p40;
--    SA        <= (others => '1');

    wait for 2*p40;
    triggerin <= (575 downto 3 => '0') & '1' & (1 downto 0 => '0') ;
    wait for 2*p40;
    triggerin <= (575 downto 0 => '0');

    wait for 2*p40;
    triggerin <= (575 downto 0 => '1');
    wait for 2*p40;
    triggerin <= (575 downto 3 => '1') & '0' & (1 downto 0 => '1') ;

    wait for 2*p40;
    triggerin <= (575 downto 3 => '0') & '1' & (1 downto 0 => '0') ;
    wait for 2*p40;
    triggerin <= (575 downto 0 => '0');

    
    wait;

    -- insert signal assignments here
    
  
  end process WaveGen_Proc;

    SA <= not triggerin(287 downto 0);
  SB <= not triggerin(575 downto 288);

end fut;

-------------------------------------------------------------------------------

configuration TLMU_tb_fut_cfg of TLMU_tb is
  for fut
  end for;
end TLMU_tb_fut_cfg;

-------------------------------------------------------------------------------