-------------------------------------------------------------------------------
-- TLMU: top level Entity of TLMU FPGA
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

library UNISIM;
use UNISIM.vcomponents.all;


entity TLMU is

  generic (
    version_id : std_logic_vector := x"00010001";
    padCol     : positive         := 8;
    padRow     : positive         := 36);


  port (
    -- Signals from DCS-A 
    RESET_A    : in    std_logic;       -- activ low (G17, in DS: SPARE1-A)
    CLK40_A    : in    std_logic;       -- A20
    SCSN_IN_A  : in    std_logic;       -- C18
    SCSN_OUT_A : out   std_logic;       -- C17
    T_A        : out   std_logic_vector (7 downto 0);  --  
    SPA_A      : in    std_logic;       -- C15
    SPB_A      : in    std_logic;       -- F16
    SPC_A      : out   std_logic;       -- F20
    SPD_A      : out   std_logic;       -- G15
    EN_A       : in    std_logic;       -- C19
    -- Signals from DCS-B
    RESET_B    : in    std_logic;       -- activ low (AH17, in DS:SPARE1-B)
    CLK40_B    : in    std_logic;       -- AN14
    SCSN_IN_B  : in    std_logic;       -- AP14
    SCSN_OUT_B : out   std_logic;       -- AK17
    T_B        : out   std_logic_vector (7 downto 0);  -- 
    SPA_B      : in    std_logic;       -- AP24
    SPB_B      : in    std_logic;       -- AM23
    SPC_B      : out   std_logic;       -- AN23
    SPD_B      : out   std_logic;       -- AN22
    EN_B       : in    std_logic;       -- AJ15
    -- common I/O)
    LED        : out   std_logic_vector (8 downto 1);
    SA         : in    std_logic_vector(padCol*padRow-1 downto 0);
    SB         : in    std_logic_vector(padCol*padRow-1 downto 0);
    -- Temperature Sensor U2 (SHT11)
    T_Data     : inout std_logic;
    T_Clk      : out   std_logic
    );


end TLMU;

-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture behv of TLMU is
component TLMU_clk
  port (
    I_A      : in  std_logic;
    I_B      : in  std_logic;
    clocksel : in  std_logic;
    O40      : out std_logic;
    O160     : out std_logic;
    O120     : out std_logic;
    OCLKTA   : out std_logic);
end component;

--
component trigger_input_sort
  port (
    S_first_all_A_then_all_C : in  std_logic_vector(575 downto 0);
    S_SM_by_SM               : out std_logic_vector(575 downto 0));
end component;
--
component trigger_input_filter
  generic (
    use_sfr : boolean;
    use_asy : boolean;
    oreg    : boolean); 
  port (
    reset_n : in  std_logic;
    clk120  : in  std_logic;
    clk40   : in  std_logic;
    Sa      : in  std_logic_vector(575 downto 0);
    Ss      : out std_logic_vector(575 downto 0)); 
end component;

component or576
  port (
    i : in  std_logic_vector(575 downto 0);
    o : out std_logic);
end component;
-------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------

signal led_i   : std_logic_vector(7 downto 0);
signal reset_n : std_logic;

-- Signals to/from DCS Board A or B (AB_switch)


signal clocksel : std_logic;            -- 0 : clock from A, 1: clock from B


-- Clocks (TLMU_clk)
signal clk40   : std_logic;
signal clk160  : std_logic;
signal clk120  : std_logic;
signal clkta   : std_logic;
signal clkscsn : std_logic;

-- Filtered iin input_stage: Input SA,SB
signal Sin       : std_logic_vector(2*padCol*padRow-1 downto 0);
signal Sasync    : std_logic_vector(2*padCol*padRow-1 downto 0);
signal Ssynced40 : std_logic_vector(2*padCol*padRow-1 downto 0);

signal nSasync    : std_logic_vector(2*padCol*padRow-1 downto 0);
signal nSsynced40 : std_logic_vector(2*padCol*padRow-1 downto 0);



begin
-------------------------------------------------------------------------------
-- BEGIN ARCHITECTURE
-------------------------------------------------------------------------------
reset_n <= not RESET_A;
-------------------------------------------------------------------------------

TLMU_clk_1 : TLMU_clk
  port map (
    I_A      => CLK40_A,
    I_B      => CLK40_B,
    clocksel => '0',
    O40      => clk40,
    O160     => clk160,
    O120     => clk120,
    OCLKTA   => clkta);

clkscsn <= clk40;

Sin <= SB & SA;

trigger_input_sort_1 : trigger_input_sort
  port map (
    S_first_all_A_then_all_C => Sin,
    S_SM_by_SM               => Sasync);


trigger_input_filter_1 : trigger_input_filter
  generic map (
    use_sfr => false,
    use_asy => true,
    oreg    => true)
  port map (
    reset_n => reset_n,
    clk120  => clk120,
    clk40   => clk40,
    Sa      => Sasync,
    Ss      => Ssynced40);


or576_1 : or576
  port map (
    i => Sasync,
    o => T_A(0));

or576_2 : or576
  port map (
    i => Ssynced40,
    o => T_A(1));

nSsynced40 <= not Ssynced40;
nSasync <= not Sasync ;

or576_3: or576
  port map (
    i => nSasync ,
    o => T_A(2));

or576_4: or576
  port map (
    i => nSsynced40,
    o => T_A(3));

T_A(7 downto 4) <= "0000";

SCSN_OUT_A <= '0';
SPC_A      <= '0';
SPD_A      <= '0';
SCSN_OUT_B <= '0';
T_B        <= (others => '0');
SPC_B      <= '0';
SPD_B      <= '0';
LED        <= (others => '0');
T_Clk      <= '0';

end behv;