-------------------------------------------------------------------------------
-- AB switch select between signals from/to DCS-A and DCS-B
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity AB_switch is

  port (
    AB_OBI     : out std_logic_vector(31 downto 0);
    clocksel   : out std_logic;
    RESET_A    : in  std_logic;
    SCSN_IN_A  : in  std_logic;
    SCSN_OUT_A : out std_logic;
    T_A        : out std_logic_vector (7 downto 0);
    SPA_A      : in  std_logic;
    SPB_A      : in  std_logic;
    SPC_A      : out std_logic;
    SPD_A      : out std_logic;
    EN_A       : in  std_logic;
--
    RESET_B    : in  std_logic;
    SCSN_IN_B  : in  std_logic;
    SCSN_OUT_B : out std_logic;
    T_B        : out std_logic_vector (7 downto 0);
    SPA_B      : in  std_logic;
    SPB_B      : in  std_logic;
    SPC_B      : out std_logic;
    SPD_B      : out std_logic;
    EN_B       : in  std_logic;
--
    RESET      : out std_logic;
    SCSN_IN    : out std_logic;
    SCSN_OUT   : in  std_logic;
    T          : in  std_logic_vector (7 downto 0);
    SPA        : out std_logic;
    SPB        : out std_logic;
    SPC        : in  std_logic;
    SPD        : in  std_logic
    );

end AB_switch;

architecture behv of AB_switch is

  signal ENi : std_logic_vector(1 downto 0);
  signal sel : std_logic;
  
begin  -- behv

  ENi <= SPB_A & SPB_B ;
  AB_OBI <= (31 downto 6 => '0') & SPA_A & SPA_B & SPB_A & SPB_B & EN_B & EN_A;

  -- sel=0: Primary (A), sel=1: Backup(B)
  sel <= '1' when ENi = "01" else '0';
  clocksel <= sel;
  


  RESET   <= RESET_A   when sel = '0' else RESET_B;
  SCSN_IN <= SCSN_IN_A when sel = '0' else SCSN_IN_B;
  SPA     <= SPA_A     when sel = '0' else SPA_B;
  SPB     <= SPB_A     when sel = '0' else SPB_B;

  SCSN_OUT_A <= SCSN_OUT;
  SCSN_OUT_B <= SCSN_OUT;
  T_A        <= T;
  T_B        <= T;
  SPC_A      <= SPC;
  SPC_B      <= SPC;
  SPD_A      <= SPD;
  SPD_B      <= SPD;



end behv;