library ieee;
use ieee.std_logic_1164.all;

entity oddr2 is
port ( CE : in  std_logic;
       R  : in  std_logic;
       S  : in  std_logic; -- dummy
       C0 : in  std_logic; -- clock
       C1 : in  std_logic; -- not clock, dummy
       D0 : in  std_logic; -- d for rising edge
       D1 : in  std_logic; -- d for falling edge
       Q : out std_logic);
end oddr2;

architecture a of oddr2 is

COMPONENT DDR_OUT
  port(
       DR  : in    STD_ULOGIC;
       DF  : in    STD_ULOGIC;
       CLK : in    STD_ULOGIC;
       CLR : in    STD_ULOGIC;
       Q   : out   STD_ULOGIC);
END COMPONENT;

COMPONENT OUTBUF
  port(
       D   : in  STD_ULOGIC;
       PAD : out STD_ULOGIC);
END COMPONENT;

signal Q_i : std_logic;

begin

oddr: ddr_out
    port map(DR  => D0,
             DF  => D1,
             CLK => C0,
             CLR => '0',
             Q   => Q_i);

ob: outbuf port map(d => Q_i, pad => Q);

end;