library ieee;
use ieee.std_logic_1164.all;

entity OBUF is
port ( I : in  std_logic;
       O : out std_logic);
end OBUF;

architecture a of OBUF is

COMPONENT OUTBUF
    port(
            D   : in  STD_ULOGIC;
            PAD : out STD_ULOGIC);
END COMPONENT;

begin

ob: OUTBUF port map(D => I, PAD => O);

end;