library ieee;
use ieee.std_logic_1164.all;

entity iddr2 is
port ( CE : in  std_logic;
       R  : in  std_logic;
       S  : in  std_logic; -- dummy
       C0 : in  std_logic; -- clock
       C1 : in  std_logic; -- not clock, dummy
       D  : in  std_logic; -- d for rising edge
       Q0 : out std_logic;
       Q1 : out std_logic);
end iddr2;

architecture a of iddr2 is

COMPONENT DDR_REG
  port(
       D    : in    STD_ULOGIC;
       CLK  : in    STD_ULOGIC;
       CLR  : in    STD_ULOGIC;
       QR   : out   STD_ULOGIC;
       QF   : out   STD_ULOGIC);
END COMPONENT;

COMPONENT INBUF
    port(
         PAD : in  STD_ULOGIC;
         Y   : out STD_ULOGIC);
END COMPONENT;

signal D_i : std_logic;

begin

ib: inbuf port map(PAD => D, Y => D_i);

iddr: ddr_reg
      port map(D   => D_i,
               CLK => C0,
               CLR => '0',
               QR  => Q0,
               QF  => Q1);
end;