library ieee;
use ieee.std_logic_1164.all;

entity IBUFDS is
port ( I  : in  std_logic;
       IB : in  std_logic;
       O  : out std_logic);
end IBUFDS;

architecture a of IBUFDS is

COMPONENT INBUF_LVDS
    port(
      PADP   :  in    STD_ULOGIC;
      PADN   :  in    STD_ULOGIC;
      Y      :  out   STD_ULOGIC);
END COMPONENT;

begin

iib: INBUF_LVDS port map(PADP => I, PADN => IB, Y => O);

end;