library ieee;
use ieee.std_logic_1164.all;

entity IBUF is
port ( I : in  std_logic;
       O : out std_logic);
end IBUF;

architecture a of IBUF is

COMPONENT INBUF
    port(
            PAD : in  STD_ULOGIC;
            Y   : out STD_ULOGIC);
END COMPONENT;

begin

ib: inbuf port map(PAD => I, Y => O);

end;