`timescale 1 ns / 1 ns
`default_nettype none
module top(

    input  wire CLK40n,
    input  wire CLK40p,

    output wire CLK40q
);

wire clk40;

IBUFDS  lvds_in ( .I ( CLK40p ), .IB ( CLK40n ), .O ( clk40 ) );

//INBUF_LVDS  lvds_in ( .PADP ( CLK40p ), .PADN ( CLK40n ), .Y ( clk40 ) );

OBUF    se_out  ( .I ( clk40 ), .O ( CLK40q ));

//OUTBUF   se_out  ( .D ( clk40 ), .PAD ( CLK40q ));

endmodule