/*
top-level Verilog netlist for CB-B and PIMDDL designs

The CB-B is implemented on a Spartan 3E device, while the PIMDDL on an Actel ProAsic3E device

Don't forget, unlike VHDL, Verilog is case-sensitive!

$Id$:

*/

// read the defines, if SPARTAN defined, then compile only the CB-B part for Spartan
`include "./build/defines.v"

// only for simulation
`timescale 1 ns / 1 ns

// disable automatic wire generation when the declaration is missing
`default_nettype none

module top(

`ifndef SPARTAN
    input  wire RST_n,  // power up reset from the DS1818
    input  wire PUSHB,  // push button, active low
`endif
    // clock input from the DCS board
    input  wire CLK40n,
    input  wire CLK40p,

    // SCSN I/O to DCS board
    input  wire SCSNINn,
    input  wire SCSNINp,
    output wire SCSNOUTn,
    output wire SCSNOUTp,

    // SCSN I/O to TLMU
`ifndef SPARTAN
    input  wire IF17x_SCSN_IN_n,
    input  wire IF17x_SCSN_IN_p,
    output wire IF17x_SCSN_OUT_n,
    output wire IF17x_SCSN_OUT_p,
`else
    // SCSN I/O to TLMU
    input  wire IF17x_SCSN_IN,
    output wire IF17x_SCSN_OUT,
`endif

    // TTCrx
    input  wire L1ACCEPTn,
    input  wire L1ACCEPTp,
    input  wire B_Channel,

    // TTCex
    output wire A_ECL,
    output wire B_ECL,
    output wire BC_ECL,

    output wire CB_TOF,
`ifndef SPARTAN
    output wire L_OUTSP,      // spare to TLMU
`endif
    input  wire [1:0] IO_C,   // SOR/EOR signal from DCS board

    // PIM
    output wire [2:0] PIMLINK,

    // GTU
    input  wire BUSY,

    // Two RJ-45 connectors with LVDS signals
`ifndef SPARTAN
    input  wire [1:0] S1_IN_n,
    input  wire [1:0] S1_IN_p,

    input  wire [1:0] S2_IN_n,
    input  wire [1:0] S2_IN_p,

    output wire [1:0] S1_OUT_n,
    output wire [1:0] S1_OUT_p,

    output wire [1:0] S2_OUT_n,
    output wire [1:0] S2_OUT_p,

    // TLMU interface
    //
    output wire CLK40T_n, // clock to the TLMU
    output wire CLK40T_p,
`else
    input  wire [1:0] S1_IN,
    input  wire [1:0] S2_IN,
    output wire [1:0] S1_OUT,
    output wire [1:0] S2_OUT,

    // TLMU interface
    output wire CLK40T, // clock to the TLMU
`endif

    output wire RESET_TOFFPGA,
    output wire CNRRL, // enable for TLMU interface
                  // used for primary/backup switching
    // SCSN pass through to TLMU
    input  wire SCSNFEBINn,
    input  wire SCSNFEBINp,
    output wire SCSNFEBOUTn,
    output wire SCSNFEBOUTp,

    // TLMU trigger inputs
`ifndef SPARTAN
    input  wire [7:0] TLMU_n,
    input  wire [7:0] TLMU_p,
`else
    input  wire [7:0] TLMU,
`endif

`ifndef SPARTAN
    // flow control I/Os
    input  wire SPC_n,
    input  wire SPC_p,
    input  wire SPD_n,
    input  wire SPD_p,
    output wire SPA_n,
    output wire SPA_p,
    output wire SPB_n,
    output wire SPB_p,
`else
    input  wire SPC,
    input  wire SPD,
    output wire SPA,
    output wire SPB,
`endif

    // input from CB-A/C
    input  wire CB_A,
    input  wire CB_C,

`ifndef SPARTAN
    // serial 7-channel ADC ADC78H89 to monitor the supply voltages
    output wire ADC_CSn,
    output wire ADC_SCLK,
    input  wire ADC_SDI,
    output wire ADC_SDO,

    // Dallas 1-Wire Temperature Sensor DS18B20
    inout  wire TSENS,

    // S I U design
    //
    // on board LEDs
    output wire [1:4] LED_SIU,
    // I2C EEPROM 24LC02 with the SIU ID
    output wire SCL_ID,
    inout  wire SDA_ID,
    output wire WP_ID,

    // ADC to measure the power consumption of the SFP
    output wire SFPP_SCLK,
    output wire SFPP_SCSn,
    input  wire SFPP_SDO,

    // SFP static signals
    input  wire SFP_PRESENT,
    output wire SFP_TX_DIS,
    input  wire SFP_TX_FAULT,

    // I2C to read the optical power of the SFP module
    output wire SIU_SCL,
    inout  wire SIU_SDA,

    // TLK2501 static signals
    output wire SIU_ENABLE,
    output wire SIU_LCKREFN,
    output wire SIU_LOOPEN,
    output wire SIU_PRBSEN,
    input  wire SIU_RECV_LOS,

    // TLK2501 receiver port
    input  wire SIU_RXCLK,
    input  wire SIU_RXDV,
    input  wire SIU_RXER,
    input  wire [15:0] SIU_RXD,

    // TLK2501 sender port
    input  wire SIU_TXCLK,
    output wire [15:0] SIU_TXD,
    output wire SIU_TXEN,
    output wire SIU_TXER,
`endif
    // Front-Panel LEDs
    output wire [1:2] LED
);

parameter Ncnt = 26;


`ifndef SPARTAN
// 32 bit bus CBB <-> SIU
wire [31:0] fbDin;
wire [31:0] fbDout;
wire fbIEN;
wire fbOEN;
wire fbICTRL;
wire fbOCTRL;
wire fiBEN_N;
wire fiDIR;
wire fiLF_N;
wire foBSY_N;
wire foCLK;
`endif

// CBB design internal wires of the IOs
wire RST_n_i; // power up reset from the DS1818
wire reset_n; // internal reset signal
wire PUSHB_i; // push button
wire CLK40_i;
wire [1:0] IO_C_i;
wire CLK80out;
wire SCSNIN_i;
wire SCSNOUT_i;
wire CLK40out;
`ifndef SPARTAN
wire SCSNOUT2_i;
`endif
wire IF17x_SCSN_IN_i;
wire IF17x_SCSN_OUT_i;
wire L1ACCEPT_i;
wire B_Channel_i;
wire A_ECL_i;
wire B_ECL_i;
wire BC_ECL_i;
wire CB_TOF_i;
wire L_OUTSP_i; // spare to TLMU
wire [2:0] PIMLINK_i;
wire [1:0] BUSY_i;
wire [1:0] S1_IN_i;
wire [1:0] S1_OUT_i;
wire [1:0] S2_IN_i;
wire [1:0] S2_OUT_i;
wire CLK40T_i;
wire RST2FPGA_i;
wire CNRRL_i; // enable for TLMU interface
wire SCSNFEBIN_i;
wire SCSNFEBOUT_i;
wire [7:0] TLMU_i;
wire SPA_i;
wire SPB_i;
wire SPC_i;
wire SPD_i;
wire [1:0] CB_A_i;
wire [1:0] CB_C_i;
wire [1:2] LED_i;

// + second scsn slave

`ifndef SPARTAN
wire ADC_CSn_i;
wire ADC_SCLK_i;
wire ADC_SDI_i;
wire ADC_SDO_i;
wire TSENS_i;
wire TSENS_o;
wire TSENS_e;
wire SFP_PRESENT_i;

// S I U design internal wires of the IOs
wire [1:4] LED_SIU_i;
wire SCL_ID_i;
wire SDA_ID_i;
wire SDA_ID_o;
wire SDA_ID_e;
wire WP_ID_i;
wire SFPP_SCLK_i;
wire SFPP_SCSn_i;
wire SFPP_SDO_i;
wire SFP_TX_DIS_i;
wire SFP_TX_FAULT_i;
wire SIU_SCL_i;
wire SIU_SDA_i;
wire SIU_SDA_o;
wire SIU_SDA_e;
wire SIU_ENABLE_i;
wire SIU_LCKREFN_i;
wire SIU_LOOPEN_i;
wire SIU_PRBSEN_i;
wire SIU_RECV_LOS_i;
wire SIU_RXCLK_i;
wire SIU_RXDV_i;
wire SIU_RXER_i;
wire [15:0] SIU_RXD_i;
wire SIU_TXCLK_i;
wire [15:0] SIU_TXD_i;
wire SIU_TXEN_i;
wire SIU_TXER_i;
`endif

wire CLK80out_n;

wire Log1;
wire Log0;

reg [Ncnt-1 : 0] led_cnt;

genvar i;

cbb_top i_cbb(
    .RST_n               ( reset_n ),
    .CLK40in             ( CLK40_i ),
    .CLK40out            ( CLK40out ),
    .CLK80out            ( CLK80out ),

    // SCSN I/O to DCS board
    .SCSNIN              ( SCSNIN_i ),
    .SCSNOUT             ( SCSNOUT_i ),

    // SCSN I/O to TLMU
    .IF17x_SCSN_IN       ( IF17x_SCSN_IN_i ),
    .IF17x_SCSN_OUT      ( IF17x_SCSN_OUT_i ),

    // TTCrx
    .L1ACCEPT            ( L1ACCEPT_i ),
    .B_Channel           ( B_Channel_i ),
    .IO_C                ( IO_C_i ),

    // TTCex
    .A_ECL               ( A_ECL_i ),
    .B_ECL               ( B_ECL_i ),
    .BC_ECL              ( BC_ECL_i ),

    .CB_TOF              ( CB_TOF_i ),
    .L_OUTSP             ( L_OUTSP_i ),

    // PIM
    .PIMLINK             ( PIMLINK_i ),

    // GTU
    .BUSY                ( BUSY_i ),

    // Two RJ-45 connectors with LVDS signals
    .S1_IN               ( S1_IN_i ),
    .S1_OUT              ( S1_OUT_i ),
    .S2_IN               ( S2_IN_i ),
    .S2_OUT              ( S2_OUT_i ),

    // TLMU interface
    //
    .CLK40T              ( CLK40T_i ),
    .RESET_TOFFPGA       ( RST2FPGA_i ),
    .CNRRL               ( CNRRL_i ),
                                            // used for primary/backup switching
    // SCSN pass through to TLMU
    .SCSNFEBIN           ( SCSNFEBIN_i ),
    .SCSNFEBOUT          ( SCSNFEBOUT_i ),

    // TLMU trigger inputs
    .TLMU_trg            ( TLMU_i ),
    // flow control I/Os
    .SPC                 ( SPC_i ),
    .SPD                 ( SPD_i ),
    .SPA                 ( SPA_i ),
    .SPB                 ( SPB_i ),

    // input from CB-A/C
    .CB_A                ( CB_A_i ),
    .CB_C                ( CB_C_i ),

    // Front-Panel LEDs
    .LED                 ( LED_i));

`ifndef SPARTAN

adc2scsn i_adc(
    .RST_n               ( reset_n),
    .CLK40in             ( CLK40out ),

    // SCSN I/O to DCS board
    .SCSNIN              ( SCSNOUT_i ),
    .SCSNOUT             ( SCSNOUT2_i ),

    // serial 7-channel ADC ADC78H89 to monitor the supply voltages
    .ADC_CSn             ( ADC_CSn_i ),
    .ADC_SCLK            ( ADC_SCLK_i ),
    .ADC_SDI             ( ADC_SDI_i ),
    .ADC_SDO             ( ADC_SDO_i ),

    // 32 bit bus
    .fbDin               ( fbDin ),
    .fbDout              ( fbDout ),
    .fbIEN               ( fbIEN ),
    .fbOEN               ( fbOEN ),
    .fbICTRL             ( fbICTRL ),
    .fbOCTRL             ( fbOCTRL ),
    .fiBEN_N             ( fiBEN_N ),
    .fiDIR               ( fiDIR ),
    .fiLF_N              ( fiLF_N ),
    .foBSY_N             ( foBSY_N ),
    .foCLK               ( foCLK ),

    // SFP Module I2C and present
    .SFP_PRESENT         ( SFP_PRESENT_i ),
    .SFP_SCL             ( SIU_SCL_i ),
    .SFP_SDA_i           ( SIU_SDA_i ),
    .SFP_SDA_o           ( SIU_SDA_o ),
    .SFP_SDA_e           ( SIU_SDA_e ),

    // Dallas 1-Wire Temperature Sensor DS18B20
    .TSENS_i             ( TSENS_i ),
    .TSENS_o             ( TSENS_o ),
    .TSENS_e             ( TSENS_e) );


siu_top_core i_SIU(
    // to/from TLK2501
    .tx_clk   ( SIU_TXCLK_i ),
    .tx_en    ( SIU_TXEN_i ),
    .tx_er    ( SIU_TXER_i ),
    .txd      ( SIU_TXD_i ),

    .rx_clk   ( SIU_RXCLK_i ),
    .rx_dv    ( SIU_RXDV_i ),
    .rx_er    ( SIU_RXER_i ),
    .rxd      ( SIU_RXD_i ),
    // static signals
    .prbsen   ( SIU_PRBSEN_i ),
    .loopen   ( SIU_LOOPEN_i ),
    .enable   ( SIU_ENABLE_i ),
    .lckrefn  ( SIU_LCKREFN_i ),

    // 32 bit bus
    .fbDin    ( fbDin ),
    .fbDout   ( fbDout ),
    .fbIEN    ( fbIEN ),
    .fbOEN    ( fbOEN ),
    .fbICTRL  ( fbICTRL ),
    .fbOCTRL  ( fbOCTRL ),
    .fiBEN_N  ( fiBEN_N ),
    .fiDIR    ( fiDIR ),
    .fiLF_N   ( fiLF_N ),
    .foBSY_N  ( foBSY_N ),
    .foCLK    ( foCLK ),

    //
    .ot_los   ( SIU_RECV_LOS_i ),
    .ot_td    ( SFP_TX_DIS_i ),
    .ot_tf    ( SFP_TX_FAULT_i ),
    //
    .led1     ( LED_SIU_i[1] ),
    .led2     ( LED_SIU_i[2] ),
    .led3     ( LED_SIU_i[3] ),
    .led4     ( LED_SIU_i[4] ),

    .pm_dout  ( SFPP_SDO_i ),
    .pm_ncs   ( SFPP_SCSn_i ),
    .pm_clk   ( SFPP_SCLK_i ),
    .i2c_scl  ( SCL_ID_i ),
    .i2c_sda_i  ( SDA_ID_i ),
    .i2c_sda_o  ( SDA_ID_o ),
    .i2c_sda_e  ( SDA_ID_e ),
    .pwr_good ( reset_n) );

    assign WP_ID_i = 1;
`endif

  // I/O buffers

IBUFDS  lvds_clk40in       ( .I ( CLK40p ),  .IB ( CLK40n ),  .O ( CLK40_i ));
IBUFDS  lvds_scsn_in       ( .I ( SCSNINp ), .IB ( SCSNINn ), .O ( SCSNIN_i));

`ifndef SPARTAN
IBUFDS  lvds_IF17x_SCSN_IN ( .I ( IF17x_SCSN_IN_p ),  .IB ( IF17x_SCSN_IN_n ),  .O ( IF17x_SCSN_IN_i ));
OBUFDS  lvds_IF17x_SCSN_OUT( .I ( IF17x_SCSN_OUT_i ), .O  ( IF17x_SCSN_OUT_p ), .OB( IF17x_SCSN_OUT_n ));
`else
IBUF    lvds_IF17x_SCSN_IN ( .I ( IF17x_SCSN_IN ),   .O ( IF17x_SCSN_IN_i ));
OBUF    obuf_IF17x_SCSN_IN ( .I ( IF17x_SCSN_OUT_i ),.O ( IF17x_SCSN_OUT ));
`endif

IBUFDS  lvds_SCSNFEBIN     ( .I ( SCSNFEBINp ), .IB ( SCSNFEBINn ), .O ( SCSNFEBIN_i ));
IBUFDS  lvds_L1A           ( .I ( L1ACCEPTp ),  .IB ( L1ACCEPTn ),  .O ( L1ACCEPT_i ) );

`ifndef SPARTAN
IBUFDS  lvds_SPC ( .I ( SPC_p ), .IB ( SPC_n ), .O ( SPC_i ));
IBUFDS  lvds_SPD ( .I ( SPD_p ), .IB ( SPD_n ), .O ( SPD_i ));

OBUFDS  lvds_SPA ( .I ( SPA_i ), .O ( SPA_p ), .OB ( SPA_n ));
OBUFDS  lvds_SPB ( .I ( SPB_i ), .O ( SPB_p ), .OB ( SPB_n ));
`else
IBUF    ibuf_SPC ( .I ( SPC ),   .O ( SPC_i ));
IBUF    ibuf_SPD ( .I ( SPD ),   .O ( SPD_i ));

OBUF    obuf_SPA ( .I ( SPA_i ), .O ( SPA ));
OBUF    obuf_SPB ( .I ( SPB_i ), .O ( SPB ));
`endif

generate
 for (i=0; i<2; i=i+1)
  begin:adds1s2
   `ifndef SPARTAN

   IBUFDS  lvds_S1in  ( .I ( S1_IN_p[i] ),  .IB ( S1_IN_n[i] ),  .O ( S1_IN_i[i] ));
   IBUFDS  lvds_S2in  ( .I ( S2_IN_p[i] ),  .IB ( S2_IN_n[i] ),  .O ( S2_IN_i[i] ));

   OBUFDS  lvds_S1out ( .I ( S1_OUT_i[i] ), .O  ( S1_OUT_p[i] ), .OB( S1_OUT_n[i] ));
   OBUFDS  lvds_S2out ( .I ( S2_OUT_i[i] ), .O  ( S2_OUT_p[i] ), .OB( S2_OUT_n[i] ));

   `else

   IBUF    ibuf_S1in  ( .I ( S1_IN[i] ),    .O ( S1_IN_i[i] ));
   IBUF    ibuf_S2in  ( .I ( S2_IN[i] ),    .O ( S2_IN_i[i] ));

   OBUF    obuf_S1out ( .I ( S1_OUT_i[i] ), .O ( S1_OUT[i] ));
   OBUF    obuf_S2out ( .I ( S2_OUT_i[i] ), .O ( S2_OUT[i] ));

   `endif
  end
endgenerate


generate
 for (i=0; i<8;i=i+1)
 begin:tlmu_in
`ifndef SPARTAN
  IBUFDS  lvds_TLMU ( .I ( TLMU_p[i] ), .IB ( TLMU_n[i] ), .O ( TLMU_i[i] ) );
`else
  IBUF    ibuf_TLMU ( .I ( TLMU[i] ),                      .O ( TLMU_i[i] ));
`endif
end
endgenerate

`ifndef SPARTAN
OBUFDS  lvds_clk40out ( .I ( CLK40T_i ), .O ( CLK40T_p ), .OB( CLK40T_n ));
`else
OBUF    obuf_clk40out ( .I ( CLK40T_i ), .O ( CLK40T ));
`endif

OBUFDS  lvds_SCSNFEBOUT ( .I ( SCSNFEBOUT_i ), .O  ( SCSNFEBOUTp ), .OB( SCSNFEBOUTn ));

`ifndef SPARTAN
OBUFDS  lvds_SCSNOUT    ( .I ( SCSNOUT2_i ),   .O  ( SCSNOUTp ),    .OB( SCSNOUTn ));
`else
OBUFDS  lvds_SCSNOUT    ( .I ( SCSNOUT_i  ),   .O  ( SCSNOUTp ),    .OB( SCSNOUTn ));
`endif

`ifndef SPARTAN
  IBUF    ibuf_RST_n      ( .I ( RST_n ),        .O ( RST_n_i ));
  IBUF    ibuf_PUSHB      ( .I ( PUSHB ),        .O ( PUSHB_i ));
  assign reset_n = RST_n_i & PUSHB_i;
`else
  assign reset_n = 1'b1;
`endif
IBUF    ibuf_b_channel  ( .I ( B_Channel ),    .O ( B_Channel_i ));

IBUF    ibuf_IO_C0      ( .I ( IO_C[0] ),      .O ( IO_C_i[0] ));
IBUF    ibuf_IO_C1      ( .I ( IO_C[1] ),      .O ( IO_C_i[1] ));

assign CLK80out_n = ~ CLK80out;
assign Log1 = 1'b1;
assign Log0 = 1'b0;

IDDR2   iddr_busy   (.CE ( Log1 ), .R ( Log0 ), .S ( Log0 ), .C0 ( CLK80out ), .C1 ( CLK80out_n ), .D ( BUSY ), .Q0 ( BUSY_i[0] ), .Q1 ( BUSY_i[1] ));
IDDR2   iddr_CB_A   (.CE ( Log1 ), .R ( Log0 ), .S ( Log0 ), .C0 ( CLK80out ), .C1 ( CLK80out_n ), .D ( CB_A ), .Q0 ( CB_A_i[0] ), .Q1 ( CB_A_i[1] ));
IDDR2   iddr_CB_C   (.CE ( Log1 ), .R ( Log0 ), .S ( Log0 ), .C0 ( CLK80out ), .C1 ( CLK80out_n ), .D ( CB_C ), .Q0 ( CB_C_i[0] ), .Q1 ( CB_C_i[1] ));

OBUF  obuf_A_ECL    ( .I ( A_ECL_i ),  .O ( A_ECL ));
OBUF  obuf_B_ECL    ( .I ( B_ECL_i ),  .O ( B_ECL ));
OBUF  obuf_BC_ECL   ( .I ( BC_ECL_i ), .O ( BC_ECL ));
OBUF  obuf_CB_TOF   ( .I ( CB_TOF_i ), .O ( CB_TOF ));

`ifndef SPARTAN
OBUF  obuf_L_OUTSP  ( .I ( L_OUTSP_i ),  .O ( L_OUTSP ));
`endif

OBUF  obuf_RST2FPGA ( .I ( RST2FPGA_i ), .O ( RESET_TOFFPGA ));
OBUF  obuf_CNRRL    ( .I ( CNRRL_i ),    .O ( CNRRL ));

generate
 for (i=0; i<3; i=i+1)
  begin:pim_out
   OBUF  oddr_PIMLINK ( .I ( PIMLINK_i[i] ), .O ( PIMLINK[i] ));
  end
endgenerate

// front panel LEDs
OBUF  obuf_led_fp1 ( .I ( LED_i[1] ), .O ( LED[1] ));
OBUF  obuf_led_fp2 ( .I ( LED_i[2] ), .O ( LED[2] ));

`ifndef SPARTAN
// ADC diagnostic module

OBUF  obuf_ADC_CSn     ( .I ( ADC_CSn_i ),   .O ( ADC_CSn ));
OBUF  obuf_ADC_SCLK    ( .I ( ADC_SCLK_i ),  .O ( ADC_SCLK ));
OBUF  obuf_ADC_SDO     ( .I ( ADC_SDO_i ),   .O ( ADC_SDO ));
IBUF  ibuf_ADC_SDI     ( .I ( ADC_SDI ),     .O ( ADC_SDI_i ));
IBUF  ibuf_SFP_PRESENT ( .I ( SFP_PRESENT ), .O ( SFP_PRESENT_i ));
OBUF  obuf_SIU_SCL     ( .I ( SIU_SCL_i ),   .O ( SIU_SCL ));
BIBUF bbuf_SIU_SDA     ( .D ( SIU_SDA_o ), .E ( SIU_SDA_e ), .Y ( SIU_SDA_i ), .PAD ( SIU_SDA));
BIBUF bbuf_TSENS       ( .D ( TSENS_o ),   .E ( TSENS_e ),   .Y ( TSENS_i ),   .PAD ( TSENS));


//obuf_tlmu_clk40  : ODDR2 port map ( CE ( '1' ), R ( '0' ), S ( '0' ), C0 ( clk40 ), C1 ( not clk40 ), D0 ( '0' ), D1 ( '1' ),  Q ( CLK40T );
//ttcex_clk_buf : ODDR2 port map ( CE ( '1' ), R ( '0' ), S ( '0' ), C0 ( clk40_ps ), C1 ( clk40int ), D0 ( '1' ), D1 ( '0' ),  Q ( BC_ECL );
//ddr_pim_0 : ODDR2 port map ( CE ( '1' ), R ( '0' ), S ( '0' ), C0 ( clk40 ),    C1 ( not clk40 ),    D0 ( '0' ),         D1 ( '1' ),     Q ( PIMLINK(0) );
//ddr_pim_1 : ODDR2 port map ( CE ( '1' ), R ( '0' ), S ( '0' ), C0 ( clk40_90 ), C1 ( not clk40_90 ), D0 ( not tin1_out ), D1 ( tin1_out ), Q ( PIMLINK(1) );
//ddr_pim_2 : ODDR2 port map ( CE ( '1' ), R ( '0' ), S ( '0' ), C0 ( clk40_90 ), C1 ( not clk40_90 ), D0 ( not tin2_out ), D1 ( tin2_out ), Q ( PIMLINK(2) );


// S I U


OBUF  obuf_SFPP_SCLK    ( .I ( SFPP_SCLK_i ), .O ( SFPP_SCLK ));
OBUF  obuf_SFPP_SCSn    ( .I ( SFPP_SCSn_i ), .O ( SFPP_SCSn ));
IBUF  ibuf_SFPP_SDO     ( .I ( SFPP_SDO ),    .O ( SFPP_SDO_i ));

OBUF  obuf_WP_ID        ( .I ( WP_ID_i ),  .O ( WP_ID ));
OBUF  obuf_SCL_ID       ( .I ( SCL_ID_i ), .O ( SCL_ID ));
BIBUF bbuf_SDA_ID       ( .D ( SDA_ID_o ), .E ( SDA_ID_e ), .Y ( SDA_ID_i ), .PAD ( SDA_ID));

IBUF  ibuf_SFP_TX_FAULT ( .I ( SFP_TX_FAULT ), .O ( SFP_TX_FAULT_i ));
OBUF  obuf_SFP_TX_DIS   ( .I ( SFP_TX_DIS_i ), .O ( SFP_TX_DIS ));

OBUF  obuf_SIU_ENABLE   ( .I ( SIU_ENABLE_i ),  .O ( SIU_ENABLE ));
OBUF  obuf_SIU_LOOPEN   ( .I ( SIU_LOOPEN_i ),  .O ( SIU_LOOPEN ));
OBUF  obuf_SIU_PRBSEN   ( .I ( SIU_PRBSEN_i ),  .O ( SIU_PRBSEN ));
OBUF  obuf_SIU_LCKREFN  ( .I ( SIU_LCKREFN_i ), .O ( SIU_LCKREFN ));
IBUF  ibuf_SIU_RECV_LOS ( .I ( SIU_RECV_LOS ),  .O ( SIU_RECV_LOS_i ));

IBUF  ibuf_SIU_RXCLK    ( .I ( SIU_RXCLK ), .O ( SIU_RXCLK_i )); // ? clock buf
IBUF  ibuf_SIU_TXCLK    ( .I ( SIU_TXCLK ), .O ( SIU_TXCLK_i )); // ? clock buf

IBUF  ibuf_SIU_RXDV     ( .I ( SIU_RXDV ),  .O ( SIU_RXDV_i ));
IBUF  ibuf_SIU_RXER     ( .I ( SIU_RXER ),  .O ( SIU_RXER_i ));

generate
 for (i=0; i<16; i=i+1)
  begin:addds
   IBUF  ibuf_SIU_RXD ( .I ( SIU_RXD[i] ),   .O ( SIU_RXD_i[i] ));
   OBUF  obuf_SIU_TXD ( .I ( SIU_TXD_i[i] ), .O ( SIU_TXD[i] ));
  end
endgenerate

OBUF  obuf_SIU_TXEN ( .I ( SIU_TXEN_i ), .O ( SIU_TXEN ));
OBUF  obuf_SIU_TXER ( .I ( SIU_TXER_i ), .O ( SIU_TXER ));

// SIU LEDs

always @(posedge SIU_TXCLK_i)
begin
    led_cnt <= led_cnt + 1;
end



generate
 for (i=1; i<5; i=i+1)
//  OBUF leds_siu ( .I ( LED_SIU_i[i] ), .O ( LED_SIU[i] ) );
  OBUF leds_siu ( .I ( led_cnt[Ncnt-i] ), .O ( LED_SIU[i] ) );
endgenerate
`endif

endmodule