library ieee; use ieee.std_logic_1164.all; entity top is port ( RST_n : in std_logic; -- power up reset from the DS1818 -- clock input from the DCS board CLK40n : in std_logic; CLK40p : in std_logic; -- SCSN I/O to DCS board SCSNINn : in std_logic; SCSNINp : in std_logic; SCSNOUTn : out std_logic; SCSNOUTp : out std_logic; -- SCSN I/O to TLMU IF17x_SCSN_IN_n : in std_logic; IF17x_SCSN_IN_p : in std_logic; IF17x_SCSN_OUT_n : out std_logic; IF17x_SCSN_OUT_p : out std_logic; -- TTCrx L1ACCEPTn : in std_logic; L1ACCEPTp : in std_logic; B_Channel : in std_logic; -- TTCex A_ECL : out std_logic; B_ECL : out std_logic; BC_ECL : out std_logic; CB_TOF : out std_logic; L_OUTSP : out std_logic; -- spare to TLMU IO_C0 : in std_logic; -- SOR/EOR signal from DCS board -- PIM PIMLINK : out std_logic_vector(2 downto 0); -- GTU BUSY : in std_logic; -- Two RJ-45 connectors with LVDS signals S1_IN_n : in std_logic_vector(1 downto 0); S1_IN_p : in std_logic_vector(1 downto 0); S1_OUT_n : out std_logic_vector(1 downto 0); S1_OUT_p : out std_logic_vector(1 downto 0); S2_IN_n : in std_logic_vector(1 downto 0); S2_IN_p : in std_logic_vector(1 downto 0); S2_OUT_n : out std_logic_vector(1 downto 0); S2_OUT_p : out std_logic_vector(1 downto 0); -- TLMU interface -- CLK40T_n : out std_logic; -- clock to the TLMU CLK40T_p : out std_logic; RST2FPGA : out std_logic; CNRRL : out std_logic; -- enable for TLMU interface -- used for primary/backup switching -- SCSN pass through to TLMU SCSNFEBINn : in std_logic; SCSNFEBINp : in std_logic; SCSNFEBOUTn : out std_logic; SCSNFEBOUTp : out std_logic; -- TLMU trigger inputs TLMU_n : in std_logic_vector(7 downto 0); TLMU_p : in std_logic_vector(7 downto 0); -- flow control I/Os SP_IN_n : in std_logic_vector(1 downto 0); SP_IN_p : in std_logic_vector(1 downto 0); SP_OUT_n : out std_logic_vector(1 downto 0); SP_OUT_p : out std_logic_vector(1 downto 0); -- input from CB-A/C CB_A : in std_logic; CB_C : in std_logic; -- Front-Panel LEDs LED : out std_logic_vector(1 to 2) ); -- serial 7-channel ADC ADC78H89 to monitor the supply voltages -- ADC_CSn : out std_logic; -- ADC_SCLK : out std_logic; -- ADC_SDI : in std_logic; -- ADC_SDO : out std_logic; -- -- -- Dallas 1-Wire Temperature Sensor DS18B20 -- TSENS : inout std_logic; -- -- -- S I U design -- -- -- -- on board LEDs -- LED_SIU : out std_logic_vector(1 to 4); -- -- I2C EEPROM 24LC02 with the SIU ID -- SCL_ID : out std_logic; -- SDA_ID : inout std_logic; -- WP_ID : out std_logic; -- -- -- ADC to measure the power consumption of the SFP -- SFPP_SCLK : out std_logic; -- SFPP_SCSn : out std_logic; -- SFPP_SDO : in std_logic; -- -- -- SFP static signals -- SFP_PRESENT : in std_logic; -- SFP_TX_DIS : out std_logic; -- SFP_TX_FAULT : in std_logic; -- -- -- I2C to read the optical power of the SFP module -- SIU_SCL : out std_logic; -- SIU_SDA : inout std_logic; -- -- -- TLK2501 static signals -- SIU_ENABLE : out std_logic; -- SIU_LCKREFN : out std_logic; -- SIU_LOOPEN : out std_logic; -- SIU_PRBSEN : out std_logic; -- SIU_RECV_LOS : in std_logic; -- -- -- TLK2501 receiver port -- SIU_RXCLK : in std_logic; -- SIU_RXDV : in std_logic; -- SIU_RXER : in std_logic; -- SIU_RXD : in std_logic_vector(15 downto 0); -- -- -- TLK2501 sender port -- SIU_TXCLK : in std_logic; -- SIU_TXD : out std_logic_vector(15 downto 0); -- SIU_TXEN : out std_logic; -- SIU_TXER : out std_logic -- ); end top; architecture struct of top is component cbb_top is port ( RST_n : in std_logic; -- power up reset from the DS1818 -- clock input from the DCS board CLK40in : in std_logic; CLK40out : out std_logic; CLK80out : out std_logic; -- SCSN I/O to DCS board SCSNIN : in std_logic; SCSNOUT : out std_logic; -- SCSN I/O to TLMU IF17x_SCSN_IN : in std_logic; IF17x_SCSN_OUT : out std_logic; -- TTCrx L1ACCEPT : in std_logic; B_Channel : in std_logic; IO_C0 : in std_logic; -- SOR/EOR signal from DCS board -- TTCex A_ECL : out std_logic; B_ECL : out std_logic; BC_ECL : out std_logic; CB_TOF : out std_logic; L_OUTSP : out std_logic; -- spare to TLMU -- PIM PIMLINK : out std_logic_vector(2 downto 0); -- GTU BUSY : in std_logic_vector(1 downto 0); -- 0 is rising edge, 1 falling -- Two RJ-45 connectors with LVDS signals S1_IN : in std_logic_vector(1 to 2); S1_OUT : out std_logic_vector(1 to 2); S2_IN : in std_logic_vector(1 to 2); S2_OUT : out std_logic_vector(1 to 2); -- TLMU interface -- CLK40T : out std_logic; -- clock to the TLMU RESET_TOFFPGA : out std_logic; CNRRL : out std_logic; -- enable for TLMU interface -- used for primary/backup switching -- SCSN pass through to TLMU SCSNFEBIN : in std_logic; SCSNFEBOUT : out std_logic; -- TLMU trigger inputs TLMU_trg : in std_logic_vector(7 downto 0); -- flow control I/Os SPA : out std_logic; SPB : out std_logic; -- input from CB-A/C CB_A : in std_logic_vector(1 downto 0); CB_C : in std_logic_vector(1 downto 0); -- 0 is rising edge, 1 falling -- -- bidir bus to the SIU -- fbDin : out std_logic_vector (31 downto 0); -- fbDout : in std_logic_vector (31 downto 0); -- fbIEN : out std_logic; -- fbOEN : in std_logic; -- fbICTRL : out std_logic; -- fbOCTRL : in std_logic; -- fiBEN_N : in std_logic; -- fiDIR : in std_logic; -- fiLF_N : in std_logic; -- foBSY_N : out std_logic; -- foCLK : out std_logic; -- Front-Panel LEDs LED : out std_logic_vector(1 to 2); SPC : in std_logic; SPD : in std_logic); --component -- serial 7-channel ADC ADC78H89 to monitor the supply voltages -- ADC_CSN : out std_logic; -- ADC_SCLK : out std_logic; -- ADC_SDI : in std_logic; -- ADC_SDO : out std_logic; -- -- -- Dallas 1-Wire Temperature Sensor DS18B20, bidirectional cell -- TSENS_o : out std_logic; -- output -- TSENS_e : out std_logic; -- output enable -- TSENS_i : in std_logic; -- input -- -- -- SFP Module I2C and present -- SFP_PRESENT : in std_logic; -- SFP_SCL : out std_logic; -- SFP_SDA_i : in std_logic; -- SFP_SDA_o : out std_logic; -- SFP_SDA_e : out std_logic; -- end component; component siu_top_core is port ( -- to/from TLK2501 tx_clk : in std_logic; tx_en : out std_logic; tx_er : out std_logic; txd : out std_logic_vector (15 downto 0); rx_clk : in std_logic; rx_dv : in std_logic; rx_er : in std_logic; rxd : in std_logic_vector (15 downto 0); -- static signals prbsen : out std_logic; loopen : out std_logic; enable : out std_logic; lckrefn : out std_logic; -- 32 bit bus fbDin : in std_logic_vector (31 downto 0); fbDout : out std_logic_vector (31 downto 0); fbIEN : in std_logic; fbOEN : out std_logic; fbICTRL : in std_logic; fbOCTRL : out std_logic; fiBEN_N : out std_logic; fiDIR : out std_logic; fiLF_N : out std_logic; foBSY_N : in std_logic; foCLK : in std_logic; -- ot_los : in std_logic; ot_td : out std_logic; ot_tf : in std_logic; -- led1 : out std_logic; led2 : out std_logic; led3 : out std_logic; -- GREENLED led4 : out std_logic; -- REDLED pm_dout : in std_logic; pm_ncs : out std_logic; pm_clk : out std_logic; i2c_scl : out std_logic; i2c_sda_i : in std_logic; i2c_sda_o : out std_logic; i2c_sda_e : out std_logic; pwr_good : in std_logic ); end component; --component pll40_160 is -- port(POWERDOWN : in std_logic; -- active high -- CLKA : in std_logic; -- input clock 40 MHz -- LOCK : out std_logic; -- locked -- GLA : out std_logic; -- 40 MHz -- GLB : out std_logic) ; -- 160 MHz --end component; -- component BIBUF -- direct for ACTEL! port( D : in STD_ULOGIC; E : in STD_ULOGIC; PAD : inout STD_ULOGIC; Y : out STD_ULOGIC); end component; component ibuf is port ( I : in std_logic; O : out std_logic); end component; component iddr2 is port ( CE : in std_logic; R : in std_logic; S : in std_logic; -- dummy C0 : in std_logic; -- clock C1 : in std_logic; -- not clock, dummy D : in std_logic; -- d for rising edge Q0 : out std_logic; Q1 : out std_logic); end component; component obuf is port ( I : in std_logic; O : out std_logic); end component; component oddr2 is port ( CE : in std_logic; R : in std_logic; S : in std_logic; -- dummy C0 : in std_logic; -- clock C1 : in std_logic; -- not clock, dummy D0 : in std_logic; -- d for rising edge D1 : in std_logic; -- d for falling edge Q : out std_logic); end component; component ibufds is port ( I : in std_logic; IB : in std_logic; O : out std_logic); end component; component obufds is port ( I : in std_logic; O : out std_logic; OB : out std_logic); end component; COMPONENT CLKBUF_LVDS port( PADP : in STD_ULOGIC; PADN : in STD_ULOGIC; Y : out STD_ULOGIC); END COMPONENT; -- 32 bit bus CBB <-> SIU signal fbDin : std_logic_vector(31 downto 0); signal fbDout : std_logic_vector(31 downto 0); signal fbIEN : std_logic; signal fbOEN : std_logic; signal fbICTRL : std_logic; signal fbOCTRL : std_logic; signal fiBEN_N : std_logic; signal fiDIR : std_logic; signal fiLF_N : std_logic; signal foBSY_N : std_logic; signal foCLK : std_logic; -- CBB design internal signals of the IOs signal RST_n_i : std_logic; -- power up reset from the DS1818 signal CLK40_i : std_logic; signal IO_C0_i : std_logic; signal CLK40out : std_logic; signal CLK80out : std_logic; signal SCSNIN_i : std_logic; signal SCSNOUT_i : std_logic; signal IF17x_SCSN_IN_i : std_logic; signal IF17x_SCSN_OUT_i : std_logic; signal L1ACCEPT_i : std_logic; signal B_Channel_i : std_logic; signal A_ECL_i : std_logic; signal B_ECL_i : std_logic; signal BC_ECL_i : std_logic; signal CB_TOF_i : std_logic; signal L_OUTSP_i : std_logic; -- spare to TLMU signal PIMLINK_i : std_logic_vector(2 downto 0); signal BUSY_i : std_logic_vector(1 downto 0); signal S1_IN_i : std_logic_vector(1 downto 0); signal S1_OUT_i : std_logic_vector(1 downto 0); signal S2_IN_i : std_logic_vector(1 downto 0); signal S2_OUT_i : std_logic_vector(1 downto 0); signal CLK40T_i : std_logic; -- clock to the TLMU signal RST2FPGA_i : std_logic; signal CNRRL_i : std_logic; -- enable for TLMU interface signal SCSNFEBIN_i : std_logic; signal SCSNFEBOUT_i : std_logic; signal TLMU_i : std_logic_vector(7 downto 0); signal SP_IN_i : std_logic_vector(1 downto 0); signal SP_OUT_i : std_logic_vector(1 downto 0); signal CB_A_i : std_logic_vector(1 downto 0); signal CB_C_i : std_logic_vector(1 downto 0); signal LED_i : std_logic_vector(1 to 2); -- + second scsn slave --signal ADC_CSN_i : std_logic; --signal ADC_SCLK_i : std_logic; --signal ADC_SDI_i : std_logic; --signal ADC_SDO_i : std_logic; --signal TSENS_i : std_logic; --signal TSENS_o : std_logic; --signal TSENS_e : std_logic; --signal SFP_PRESENT_i : std_logic; -- S I U design internal signals of the IOs --signal LED_SIU_i : std_logic_vector(1 to 4); --signal SCL_ID_i : std_logic; --signal SDA_ID_i : std_logic; --signal SDA_ID_o : std_logic; --signal SDA_ID_e : std_logic; --signal WP_ID_i : std_logic; --signal SFPP_SCLK_i : std_logic; --signal SFPP_SCSn_i : std_logic; --signal SFPP_SDO_i : std_logic; --signal SFP_TX_DIS_i : std_logic; --signal SFP_TX_FAULT_i : std_logic; --signal SIU_SCL_i : std_logic; --signal SIU_SDA_i : std_logic; --signal SIU_SDA_o : std_logic; --signal SIU_SDA_e : std_logic; --signal SIU_ENABLE_i : std_logic; --signal SIU_LCKREFN_i : std_logic; --signal SIU_LOOPEN_i : std_logic; --signal SIU_PRBSEN_i : std_logic; --signal SIU_RECV_LOS_i : std_logic; --signal SIU_RXCLK_i : std_logic; --signal SIU_RXDV_i : std_logic; --signal SIU_RXER_i : std_logic; --signal SIU_RXD_i : std_logic_vector(15 downto 0); --signal SIU_TXCLK_i : std_logic; --signal SIU_TXD_i : std_logic_vector(15 downto 0); --signal SIU_TXEN_i : std_logic; --signal SIU_TXER_i : std_logic; begin i_cbb: cbb_top port map( RST_n => RST_n_i, -- clock input from the DCS board CLK40in => CLK40_i, CLK40out => CLK40out, CLK80out => CLK80out, -- SCSN I/O to DCS board SCSNIN => SCSNIN_i, SCSNOUT => SCSNOUT_i, -- SCSN I/O to TLMU IF17x_SCSN_IN => IF17x_SCSN_IN_i, IF17x_SCSN_OUT => IF17x_SCSN_OUT_i, -- TTCrx L1ACCEPT => L1ACCEPT_i, B_Channel => B_Channel_i, IO_C0 => IO_C0_i, -- TTCex A_ECL => A_ECL_i, B_ECL => B_ECL_i, BC_ECL => BC_ECL_i, CB_TOF => CB_TOF_i, L_OUTSP => L_OUTSP_i, -- PIM PIMLINK => PIMLINK_i, -- GTU BUSY => BUSY_i, -- Two RJ-45 connectors with LVDS signals S1_IN => S1_IN_i, S1_OUT => S1_OUT_i, S2_IN => S2_IN_i, S2_OUT => S2_OUT_i, -- TLMU interface -- CLK40T => CLK40T_i, RESET_TOFFPGA => RST2FPGA_i, CNRRL => CNRRL_i, -- used for primary/backup switching -- SCSN pass through to TLMU SCSNFEBIN => SCSNFEBIN_i, SCSNFEBOUT => SCSNFEBOUT_i, -- TLMU trigger inputs TLMU_trg => TLMU_i, -- flow control I/Os SPC => SP_IN_i(0), SPD => SP_IN_i(1), SPA => SP_OUT_i(0), SPB => SP_OUT_i(1), -- input from CB-A/C CB_A => CB_A_i, CB_C => CB_C_i, -- Front-Panel LEDs LED => LED_i); -- serial 7-channel ADC ADC78H89 to monitor the supply voltages -- ADC_CSN => ADC_CSN_i, -- ADC_SCLK => ADC_SCLK_i, -- ADC_SDI => ADC_SDI_i, -- ADC_SDO => ADC_SDO_i, -- -- -- 32 bit bus -- fbDin => fbDin, -- fbDout => fbDout, -- fbIEN => fbIEN, -- fbOEN => fbOEN, -- fbICTRL => fbICTRL, -- fbOCTRL => fbOCTRL, -- fiBEN_N => fiBEN_N, -- fiDIR => fiDIR, -- fiLF_N => fiLF_N, -- foBSY_N => foBSY_N, -- foCLK => foCLK, -- -- -- SFP Module I2C and present -- SFP_PRESENT => SFP_PRESENT_i, -- SFP_SCL => SIU_SCL_i, -- SFP_SDA_i => SIU_SDA_i, -- SFP_SDA_o => SIU_SDA_o, -- SFP_SDA_e => SIU_SDA_e, -- -- -- Dallas 1-Wire Temperature Sensor DS18B20 -- TSENS_i => TSENS_i, -- TSENS_o => TSENS_o, -- TSENS_e => TSENS_e); --i_SIU: siu_top_core -- port map( -- -- to/from TLK2501 -- tx_clk => SIU_TXCLK_i, -- tx_en => SIU_TXEN_i, -- tx_er => SIU_TXER_i, -- txd => SIU_TXD_i, -- -- rx_clk => SIU_RXCLK_i, -- rx_dv => SIU_RXDV_i, -- rx_er => SIU_RXER_i, -- rxd => SIU_RXD_i, -- -- static signals -- prbsen => SIU_PRBSEN_i, -- loopen => SIU_LOOPEN_i, -- enable => SIU_ENABLE_i, -- lckrefn => SIU_LCKREFN_i, -- -- -- 32 bit bus -- fbDin => fbDin, -- fbDout => fbDout, -- fbIEN => fbIEN, -- fbOEN => fbOEN, -- fbICTRL => fbICTRL, -- fbOCTRL => fbOCTRL, -- fiBEN_N => fiBEN_N, -- fiDIR => fiDIR, -- fiLF_N => fiLF_N, -- foBSY_N => foBSY_N, -- foCLK => foCLK, -- -- -- -- ot_los => SIU_RECV_LOS_i, -- ot_td => SFP_TX_DIS_i, -- ot_tf => SFP_TX_FAULT_i, -- -- -- led1 => LED_SIU_i(1), -- led2 => LED_SIU_i(2), -- led3 => LED_SIU_i(3), -- led4 => LED_SIU_i(4), -- -- pm_dout => SFPP_SDO_i, -- pm_ncs => SFPP_SCSn_i, -- pm_clk => SFPP_SCLK_i, -- i2c_scl => SCL_ID_i, -- i2c_sda_i => SDA_ID_i, -- i2c_sda_o => SDA_ID_o, -- i2c_sda_e => SDA_ID_e, -- pwr_good => RST_n_i); -- -- WP_ID_i <= '1'; --ipll: pll40_160 -- port map( -- POWERDOWN => '0', -- CLKA => CLK40i, -- LOCK => open, -- GLA => clk40int, -- GLB => clk160); -- I/O buffers lvds_clk40in : IBUFDS port map ( I => CLK40p, IB => CLK40n, O => CLK40_i ); lvds_scsn_in : IBUFDS port map ( I => SCSNINp, IB => SCSNINn, O => SCSNIN_i); lvds_IF17x_SCSN_IN : IBUFDS port map ( I => IF17x_SCSN_IN_p, IB => IF17x_SCSN_IN_n, O => IF17x_SCSN_IN_i); lvds_SCSNFEBIN : IBUFDS port map ( I => SCSNFEBINp, IB => SCSNFEBINn, O => SCSNFEBIN_i ); lvds_L1A : IBUFDS port map ( I => L1ACCEPTp, IB => L1ACCEPTn, O => L1ACCEPT_i ); s1s2sp: for i in 0 to 1 generate lvds_S1in : IBUFDS port map ( I => S1_IN_p(i), IB => S1_IN_n(i), O => S1_IN_i(i) ); lvds_S2in : IBUFDS port map ( I => S2_IN_p(i), IB => S2_IN_n(i), O => S2_IN_i(i) ); lvds_SPin : IBUFDS port map ( I => SP_IN_p(i), IB => SP_IN_n(i), O => SP_IN_i(i) ); lvds_S1out : OBUFDS port map ( I => S1_OUT_i(i), O => S1_OUT_p(i), OB=> S1_OUT_n(i) ); lvds_S2out : OBUFDS port map ( I => S2_OUT_i(i), O => S2_OUT_p(i), OB=> S2_OUT_n(i) ); lvds_SPout : OBUFDS port map ( I => SP_OUT_i(i), O => SP_OUT_p(i), OB=> SP_OUT_n(i) ); end generate; i_tlmu: for i in TLMU_i'range generate lvds_TLMU : IBUFDS port map ( I => TLMU_p(i), IB => TLMU_n(i), O => TLMU_i(i) ); end generate; lvds_clk40out : OBUFDS port map ( I => CLK40T_i, O => CLK40T_p, OB=> CLK40T_n ); lvds_SCSNFEBOUT : OBUFDS port map ( I => SCSNFEBOUT_i, O => SCSNFEBOUTp, OB=> SCSNFEBOUTn ); lvds_SCSNOUT : OBUFDS port map ( I => SCSNOUT_i, O => SCSNOUTp, OB=> SCSNOUTn ); lvds_IF17x_SCSN_OUT : OBUFDS port map ( I => IF17x_SCSN_OUT_i, O => IF17x_SCSN_OUT_p, OB=> IF17x_SCSN_OUT_n ); ibuf_RST_n : IBUF port map ( I => RST_n, O => RST_n_i ); ibuf_b_channel : IBUF port map ( I => B_Channel, O => B_Channel_i ); ibuf_IO_C0 : IBUF port map ( I => IO_C0, O => IO_C0_i ); iddr_busy : IDDR2 port map (CE => '1', R => '0', S => '0', C0 => clk80out, C1 => not clk80out, D => BUSY, Q0 => busy_i(0), Q1 => busy_i(1) ); -- ddr_gtu_busy : IDDR2 port map ( CE => '1', R => '0', S => '0', C0 => clk40_90, C1 => not clk40_90, D => BUSY, Q0 => gtu_busy_ddr(0), Q1 => gtu_busy_ddr(1) ); --ibuf_CB_A : IBUF port map ( I => CB_A, O => CB_A_i ); iddr_CB_A : IDDR2 port map (CE => '1', R => '0', S => '0', C0 => clk80out, C1 => not clk80out, D => CB_A, Q0 => CB_A_i(0), Q1 => CB_A_i(1) ); iddr_CB_C : IDDR2 port map (CE => '1', R => '0', S => '0', C0 => clk80out, C1 => not clk80out, D => CB_C, Q0 => CB_C_i(0), Q1 => CB_C_i(1) ); --ibuf_CB_C : IBUF port map ( I => CB_C, O => CB_C_i ); obuf_A_ECL : OBUF port map ( I => A_ECL_i, O => A_ECL ); obuf_B_ECL : OBUF port map ( I => B_ECL_i, O => B_ECL ); obuf_BC_ECL : OBUF port map ( I => BC_ECL_i, O => BC_ECL ); obuf_CB_TOF : OBUF port map ( I => CB_TOF_i, O => CB_TOF ); obuf_L_OUTSP : OBUF port map ( I => L_OUTSP_i, O => L_OUTSP ); obuf_RST2FPGA : OBUF port map ( I => RST2FPGA_i, O => RST2FPGA ); obuf_CNRRL : OBUF port map ( I => CNRRL_i, O => CNRRL ); obuf_PL: for i in PIMLINK'range generate oddr_PIMLINK : OBUF port map ( I => PIMLINK_i(i), O => PIMLINK(i) ); end generate; -- front panel LEDs obuf_led_fp1 : OBUF port map ( I => LED_i(1), O => LED(1) ); obuf_led_fp2 : OBUF port map ( I => LED_i(2), O => LED(2) ); --obuf_ADC_CSn : OBUF port map ( I => ADC_CSn_i, O => ADC_CSn ); --obuf_ADC_SCLK : OBUF port map ( I => ADC_SCLK_i, O => ADC_SCLK ); --obuf_ADC_SDO : OBUF port map ( I => ADC_SDO_i, O => ADC_SDO ); --ibuf_ADC_SDI : IBUF port map ( I => ADC_SDI, O => ADC_SDI_i ); --bbuf_TSENS : BIBUF port map ( D => TSENS_o, E => TSENS_e, Y => TSENS_i, PAD => TSENS); -- obuf_tlmu_clk40 : ODDR2 port map ( CE => '1', R => '0', S => '0', C0 => clk40, C1 => not clk40, D0 => '0', D1 => '1', Q => CLK40T ); -- ttcex_clk_buf : ODDR2 port map ( CE => '1', R => '0', S => '0', C0 => clk40_ps, C1 => clk40int, D0 => '1', D1 => '0', Q => BC_ECL ); -- ddr_pim_0 : ODDR2 port map ( CE => '1', R => '0', S => '0', C0 => clk40, C1 => not clk40, D0 => '0', D1 => '1', Q => PIMLINK(0) ); -- ddr_pim_1 : ODDR2 port map ( CE => '1', R => '0', S => '0', C0 => clk40_90, C1 => not clk40_90, D0 => not tin1_out, D1 => tin1_out, Q => PIMLINK(1) ); -- ddr_pim_2 : ODDR2 port map ( CE => '1', R => '0', S => '0', C0 => clk40_90, C1 => not clk40_90, D0 => not tin2_out, D1 => tin2_out, Q => PIMLINK(2) ); -- S I U --bbuf_SIU_SDA : BIBUF port map ( D => SIU_SDA_o, E => SIU_SDA_e, Y => SIU_SDA_i, PAD => SIU_SDA); --obuf_SIU_SCL : OBUF port map ( I => SIU_SCL_i, O => SIU_SCL ); -- --obuf_SFPP_SCLK : OBUF port map ( I => SFPP_SCLK_i, O => SFPP_SCLK ); --obuf_SFPP_SCSn : OBUF port map ( I => SFPP_SCSn_i, O => SFPP_SCSn ); --ibuf_SFPP_SDO : IBUF port map ( I => SFPP_SDO, O => SFPP_SDO_i ); -- -- --obuf_WP_ID : OBUF port map ( I => WP_ID_i, O => WP_ID ); --obuf_SCL_ID : OBUF port map ( I => SCL_ID_i, O => SCL_ID ); --bbuf_SDA_ID : BIBUF port map ( D => SDA_ID_o, E => SDA_ID_e, Y => SDA_ID_i, PAD => SDA_ID); -- --ibuf_SFP_PRESENT : IBUF port map ( I => SFP_PRESENT, O => SFP_PRESENT_i ); --ibuf_SFP_TX_FAULT : IBUF port map ( I => SFP_TX_FAULT, O => SFP_TX_FAULT_i ); --obuf_SFP_TX_DIS : OBUF port map ( I => SFP_TX_DIS_i, O => SFP_TX_DIS ); -- --obuf_SIU_ENABLE : OBUF port map ( I => SIU_ENABLE_i, O => SIU_ENABLE ); --obuf_SIU_LOOPEN : OBUF port map ( I => SIU_LOOPEN_i, O => SIU_LOOPEN ); --obuf_SIU_PRBSEN : OBUF port map ( I => SIU_PRBSEN_i, O => SIU_PRBSEN ); --obuf_SIU_LCKREFN : OBUF port map ( I => SIU_LCKREFN_i, O => SIU_LCKREFN ); --ibuf_SIU_RECV_LOS : IBUF port map ( I => SIU_RECV_LOS, O => SIU_RECV_LOS_i ); -- --ibuf_SIU_RXCLK : IBUF port map ( I => SIU_RXCLK, O => SIU_RXCLK_i ); -- ! clock buf --ibuf_SIU_TXCLK : IBUF port map ( I => SIU_TXCLK, O => SIU_TXCLK_i ); -- ! clock buf -- --ibuf_SIU_RXDV : IBUF port map ( I => SIU_RXDV, O => SIU_RXDV_i ); --ibuf_SIU_RXER : IBUF port map ( I => SIU_RXER, O => SIU_RXER_i ); -- --rxd: for i in SIU_RXD'range generate --ibuf_SIU_RXD : IBUF port map ( I => SIU_RXD(i), O => SIU_RXD_i(i) ); --obuf_SIU_TXD : OBUF port map ( I => SIU_TXD_i(i), O => SIU_TXD(i) ); --end generate; -- --obuf_SIU_TXEN : OBUF port map ( I => SIU_TXEN_i, O => SIU_TXEN ); --obuf_SIU_TXER : OBUF port map ( I => SIU_TXER_i, O => SIU_TXER ); -- ---- SIU LEDs --i_led_siu: for i in LED_SIU'range generate --leds_siu : OBUF port map ( I => LED_SIU_i(i), O => LED_SIU(i) ); --end generate; end;