library ieee; use ieee.std_logic_1164.all; entity siu_top_core is port ( -- to/from TLK2501 tx_clk : in std_logic; tx_en : out std_logic; tx_er : out std_logic; txd : out std_logic_vector (15 downto 0); rx_clk : in std_logic; rx_dv : in std_logic; rx_er : in std_logic; rxd : in std_logic_vector (15 downto 0); -- static signals prbsen : out std_logic; loopen : out std_logic; enable : out std_logic; lckrefn : out std_logic; -- 32 bit bus fbDin : in std_logic_vector (31 downto 0); fbDout : out std_logic_vector (31 downto 0); fbIEN : in std_logic; fbOEN : out std_logic; fbICTRL : in std_logic; fbOCTRL : out std_logic; fiBEN_N : out std_logic; fiDIR : out std_logic; fiLF_N : out std_logic; foBSY_N : in std_logic; foCLK : in std_logic; -- ot_los : in std_logic; ot_td : out std_logic; ot_tf : in std_logic; -- led1 : out std_logic; led2 : out std_logic; led3 : out std_logic; -- GREENLED led4 : out std_logic; -- REDLED pm_dout : in std_logic; pm_ncs : out std_logic; pm_clk : out std_logic; i2c_scl : out std_logic; i2c_sda_i : in std_logic; i2c_sda_o : out std_logic; i2c_sda_e : out std_logic; pwr_good : in std_logic ); end siu_top_core; architecture test of siu_top_core is signal leds : std_logic_vector(1 to 4); begin TX_ER <= '0'; LCKREFN <= '1'; ENABLE <= '1'; LOOPEN <= '0'; prbsen <= '1'; -- check pseudorandom led1 <= leds(1); process(tx_clk) begin if rising_edge(tx_clk) then end process; end;