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--******************************************************************************
--*
--* Module          : TXD_FIFO
--* File            : txd_fifo.vhd
--* Library         : ieee, lpm
--* Description     : It is a FIFO, which stores the data and status, which are
--*                   coming from the FEE.
--* Simulator       : Modelsim
--* Synthesizer     : Lenoardo Spectrum + Quartus II
--* Author/Designer : C. SOOS ( Csaba.Soos@cern.ch)
--*
--* Revision history:
--*   21-Oct-2002 CS  Original coding
--*   13-Nov-2002 CS  depth is reduced to 256 words
--*   24-Jun-2004 CS  Legacy synchronous mode
--*   17-Oct-2005 CS  FIFO width has been changed to 36 bits (+2 parity bits)
--*
--******************************************************************************

library ieee;
use ieee.std_logic_1164.all;

entity txd_fifo is

  port (
    wrclock     : in  std_logic;
    rdclock     : in  std_logic;
--    txdf_wrclr  : in  std_logic;
    txdf_rdclr  : in  std_logic;
    txdf_d      : in  std_logic_vector (35 downto 0);
    txdf_wrreq  : in  std_logic;
    txdf_rdreq  : in  std_logic;
    txdf_q      : out std_logic_vector (35 downto 0);
    txdf_empty  : out std_logic;
    txdf_full   : out std_logic;
    txdf_afull  : out std_logic;
    txdf_aempty : out std_logic);

end txd_fifo;

library ieee;
use ieee.std_logic_1164.all;

architecture SYN of txd_fifo is

  type read_state is (
    RD_EMPTY,
    RD_FETCH,
    RD_NEMPTY);

  component txdf_core
    port (
      DATA   : in  std_logic_vector (35 downto 0);
      Q      : out std_logic_vector (35 downto 0);
      RCLOCK : in  std_logic;
      WCLOCK : in  std_logic;
      WE     : in  std_logic;
      RE     : in  std_logic;
      RESET  : in  std_logic;
      FULL   : out std_logic;
      EMPTY  : out std_logic;
      AFULL  : out std_logic;
      AEMPTY : out std_logic);
  end component;

  signal txdf_r_i : std_logic;
  signal txdf_e_i : std_logic;
  signal read_ena : std_logic;
  signal fetch    : std_logic;

begin  -- SYN

  txdf_r_i <= fetch or (txdf_rdreq and read_ena);
  TXDF_CORE_INST : txdf_core
    port map (
      DATA   => txdf_d,
      Q      => txdf_q,
      RCLOCK => rdclock,
      WCLOCK => wrclock,
      WE     => txdf_wrreq,
      RE     => txdf_r_i,
      RESET  => txdf_rdclr,
      FULL   => txdf_full,
      EMPTY  => txdf_e_i,
      AFULL  => txdf_afull,
      AEMPTY => txdf_aempty
    );

  proc_read: process (rdclock, txdf_rdclr)
    variable read_present : read_state;
    variable read_next    : read_state;
  begin  -- process proc_read
    if txdf_rdclr = '0' then                  -- asynchronous reset (active low)
      read_ena   <= '0';
      fetch      <= '0';
      txdf_empty <= '1';
      read_present := RD_EMPTY;
      read_next    := RD_EMPTY;
    elsif rdclock'event and rdclock = '1' then  -- rising clock edge
      fetch <= '0';
      case read_present is
        when RD_EMPTY =>
          read_ena <= '0';
          if txdf_e_i = '0' then
            fetch <= '1';
            read_next := RD_FETCH;
          else
            read_next := RD_EMPTY;
          end if;
        when RD_FETCH =>
          txdf_empty <= '0';
          read_ena <= '1';
          read_next := RD_NEMPTY;
        when RD_NEMPTY =>
          if txdf_e_i = '1' and txdf_rdreq = '1' then
            txdf_empty <= '1';
            read_ena <= '0';
            read_next := RD_EMPTY;
          else
            read_ena <= '1';
            read_next := RD_NEMPTY;
          end if;
      end case;
      read_present := read_next;
    end if;
  end process proc_read;
end SYN;