LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

-- $Id$:

-- MSB first

entity sm_adc78h89 is
generic (
         iCLK : Boolean  :=  false;
         iCNV : Boolean  :=  false;
         iDIN : Boolean  :=  false;
         iDOU : Boolean  :=  false;
         Nstep: Integer  :=   1;  -- shift step/tc
         Nacc : Integer  :=  18;  -- acc width
         Ndiv : Positive := 100); -- divide the clock to get the spi clock
port (
    clk     : in  std_logic;
    rst_n   : in  std_logic;

    -- read port to the uC bus
    disu    : in  std_logic;
    we      : in  std_logic;
    din     : in  std_logic_vector(31 downto 0);
    addr    : in  std_logic_vector(1 downto 0);
    data    : out std_logic_vector(31 downto 0);

    -- signals to the ADC78H89
    spi_sdi : in  std_logic;
    spi_sdo : out std_logic;
    spi_clk : out std_logic;
    spi_csn : out std_logic);
end sm_adc78h89;

architecture a of sm_adc78h89 is

component adc78h89 is
generic (
         iCLK : Boolean  :=  false;
         iCNV : Boolean  :=  false;
         iDIN : Boolean  :=  false;
         iDOU : Boolean  :=  false;
         Nbit : Positive := 16;
         Ndiv : Positive := 100); -- divide the clock to get the spi clock
port (
    clk     : in  std_logic;
    srst    : in  std_logic;

    start   : in  std_logic;
    nextch  : in  std_logic_vector( 2 downto 0);

    rdy     : out std_logic;
    busy    : out std_logic;
    dout    : out std_logic_vector(11 downto 0);


    spi_sdi : in  std_logic;
    spi_sdo : out std_logic;
    spi_clk : out std_logic;
    spi_csn : out std_logic);
end component;

component relax is
generic(Nd : Positive:= 8;  -- data width
        Nf : Natural := 8;  -- data bits after the dec point at the output
        Ns : Positive:= 2;  -- shift step/tc
        Na : Positive:=18); -- acc width
port (                      -- note: Nd+3*Ns<Na!
    clk : in  std_logic;
    clr : in  std_logic;
    ena : in  std_logic;
    x   : in  std_logic_vector(Nd-1 downto 0);   -- input data
    tc  : in  std_logic_vector(   1 downto 0);   -- time constant
    y   : out std_logic_vector(Nd+Nf-1 downto 0));  -- output
end component;

type sm_type is (idle, start_s, wait_s);

-- For Precision!
-- The FSM_STATE attribute has 6 possible values:
-- auto, binary, onehot, twohot, random, and gray

attribute FSM_STATE : string;
attribute FSM_STATE of sm_type : type is "gray";

attribute SAFE_FSM : boolean;
attribute SAFE_FSM of sm_type : type is true;

constant Nf : Natural := 0;

signal sm : sm_type;


subtype adc_data  is std_logic_vector(11    downto 0);
subtype adc_dataf is std_logic_vector(11+Nf downto 0);
type adc_reg is array(0 to 6) of adc_dataf;

signal adc  : adc_reg;
signal adcr : adc_reg;

signal acq_channel : std_logic_vector(2 downto 0);

ATTRIBUTE disable_fsm : BOOLEAN;
ATTRIBUTE disable_fsm OF acq_channel : SIGNAL IS true;

signal start : std_logic;
signal rdy   : std_logic;
signal busy  : std_logic;
signal dout  : adc_data;
signal srst  : std_logic;
signal tc    : std_logic_vector(1 downto 0);
signal acc_clr : std_logic;
signal adc_ena : std_logic_vector(6 downto 0);

begin

    process(clk)
    begin
        if rising_edge(clk) then
            acc_clr <= '0';
            if we = '1' then
                if addr = "11" then
                    tc <= din(tc'range);
                    acc_clr <= din(tc'length);
                else
                    acc_clr <= '1';
                end if;
            end if;
        end if;
    end process;

    process(clk)
    begin
        if rising_edge(clk) then
            srst <= not rst_n;
            start <= '0';
            adc_ena <= (others => '0');
            if srst = '1' then
                sm <= idle;
                acq_channel <= "110";
            else
                case sm is
                when idle => sm <= start_s;
                when start_s => if busy = '0' then start <= '1'; sm <= wait_s; end if;
                when wait_s  => if rdy = '1' then
                    case acq_channel is
                    when "001"  => acq_channel <= "010"; adc_ena(0) <= '1';
                    when "010"  => acq_channel <= "011"; adc_ena(1) <= '1';
                    when "011"  => acq_channel <= "100"; adc_ena(2) <= '1';
                    when "100"  => acq_channel <= "101"; adc_ena(3) <= '1';
                    when "101"  => acq_channel <= "110"; adc_ena(4) <= '1';
                    when "110"  => acq_channel <= "000"; adc_ena(5) <= '1';
                    when "000"  => acq_channel <= "001"; adc_ena(6) <= '1';
                    when others => acq_channel <= "000";
                    end case;
                    sm <= start_s;
                    end if;
                end case;
            end if;
        end if;
    end process;

rfilt: for i in 0 to 6 generate

rfi: relax
generic map(Nd => 12,    -- data width
            Nf => Nf,
            Ns => Nstep, -- shift step/tc
            Na => Nacc)  -- acc width
port map(                -- note: Nd+3*Nstep<Nacc!
    clk => clk,
    clr => acc_clr,
    ena => adc_ena(i),
    x   => dout,
    tc  => tc,
    y   => adc(i));

end generate;

adci: adc78h89
generic map(
         iCLK => iCLK,
         iCNV => iCNV,
         iDIN => iDIN,
         iDOU => iDOU,
         Nbit => 16,
         Ndiv => Ndiv)
port map(
    clk     => clk,
    srst    => srst,

    start   => start,
    nextch  => acq_channel,

    rdy     => rdy,
    busy    => busy,
    dout    => dout,

    spi_sdi => spi_sdi,
    spi_sdo => spi_sdo,
    spi_clk => spi_clk,
    spi_csn => spi_csn);

    process(clk)
    begin
        if rising_edge(clk) then
            if disu = '0' then
                adcr <= adc;
            end if;
        end if;
    end process;

    process(addr, adcr, tc)
    begin
        data <= (others => '0');
        case addr is
        when "00"   => data <= "0000" & adcr(1) & "0000" & adcr(0);
        when "01"   => data <= "0000" & adcr(3) & "0000" & adcr(2);
        when "10"   => data <= "0000" & adcr(5) & "0000" & adcr(4);
        when "11"   => data <= tc & "00" & adcr(1) & "0000" & adcr(6);
        when others => data <= (others => '-');
        end case;
    end process;

end;