library ieee;
use ieee.std_logic_1164.all;

-- $Id$:

-- This is only a temporary design to have all signals connected!


entity siu_io is
port (
    RST_n               : in  std_logic; -- power up reset from the DS1818
    -- clock input from the DCS board
    CLK                 : in  std_logic;

    we                  : in  std_logic;
    addr                : in  std_logic_vector( 3 downto 0);
    din                 : in  std_logic_vector(31 downto 0);
    dout                : out std_logic_vector(31 downto 0);

    -- bidir bus to the SIU
    fbDin               : out std_logic_vector (31 downto 0);
    fbDout              : in  std_logic_vector (31 downto 0);
    fbIEN               : out std_logic;
    fbOEN               : in  std_logic;
    fbICTRL             : out std_logic;
    fbOCTRL             : in  std_logic;
    fiBEN_N             : in  std_logic;
    fiDIR               : in  std_logic;
    fiLF_N              : in  std_logic;
    foBSY_N             : out std_logic;
    foCLK               : out std_logic);
end siu_io;

architecture a of siu_io is
signal    fbICTRL_i           : std_logic;
signal    fbIEN_i             : std_logic;
signal    foBSY_N_i           : std_logic;
signal    fbDin_i             : std_logic_vector (31 downto 0);

begin
    process(clk, rst_n)
    begin
        if rst_n = '0' then
            fbDin_i <= (others => '0');
            fbIEN_i   <= '0';
            fbICTRL_i <= '0';
            foBSY_N_i <= '0';
            dout <= (others => '0');
        elsif rising_edge(clk) then
            -- write
            if we = '1' then
                case addr is
                    when "0000" => fbDin_i   <= din;
                    when "0001" => fbIEN_i   <= din(0);
                                   fbICTRL_i <= din(1);
                                   foBSY_N_i <= din(2);
                    when others => NULL;
                end case;
            end if;
            -- read
            dout <= (others => '0');
            case addr is
                when "0000" => dout <= fbDin_i;
                when "0001" => dout(2 downto 0) <= foBSY_N_i & fbICTRL_i & fbIEN_i;
                when "0010" => dout <= fbDout;
                when "0011" => dout(4 downto 0) <= fiLF_N & fiDIR & fiBEN_N & fbOCTRL & fbOEN;
                when others => dout <= (others => '-');
            end case;
        end if;
    end process;

    foCLK <= clk;
    fbDin <= fbDin_i;
    fbIEN    <= fbIEN_i;
    fbICTRL  <= fbICTRL_i;
    foBSY_N  <= foBSY_N_i;

end;