library IEEE;
USE IEEE.STD_LOGIC_1164.all;

-- $Id$:

entity mux41nbit is
generic(Nbit : Integer := 4);
    port(A0       : in  std_logic_vector(Nbit-1 downto 0);
         A1       : in  std_logic_vector(Nbit-1 downto 0);
         A2       : in  std_logic_vector(Nbit-1 downto 0);
         A3       : in  std_logic_vector(Nbit-1 downto 0);
         SEL      : in  std_logic_vector(     1 downto 0);
         Y        : out std_logic_vector(Nbit-1 downto 0));
end entity;

architecture a of mux41nbit is

begin
    with SEL select
    Y <= A0 when "00",
         A1 when "01",
         A2 when "10",
         A3 when "11",
         (others => 'X') when others;
end;