library ieee;
use ieee.std_logic_1164.all;

-- $Id$:

entity adc2scsn is

port (
    RST_n               : in  std_logic; -- power up reset from the DS1818
    -- clock input from the DCS board
    CLK40in             : in  std_logic;
    -- SCSN I/O to DCS board
    SCSNIN              : in  std_logic;
    SCSNOUT             : out std_logic;

    -- bidir bus to the SIU
    fbDin               : out std_logic_vector (31 downto 0);
    fbDout              : in  std_logic_vector (31 downto 0);
    fbIEN               : out std_logic;
    fbOEN               : in  std_logic;
    fbICTRL             : out std_logic;
    fbOCTRL             : in  std_logic;
    fiBEN_N             : in  std_logic;
    fiDIR               : in  std_logic;
    fiLF_N              : in  std_logic;
    foBSY_N             : out std_logic;
    foCLK               : out std_logic;

    -- serial 7-channel ADC ADC78H89 to monitor the supply voltages
    ADC_CSN             : out std_logic;
    ADC_SCLK            : out std_logic;
    ADC_SDO             : in  std_logic;
    ADC_SDI             : out std_logic;

    -- Dallas 1-Wire Temperature Sensor DS18B20, bidirectional cell
    TSENS_o             : out std_logic; -- output
    TSENS_e             : out std_logic; -- output enable
    TSENS_i             : in  std_logic; -- input

    -- SFP Module I2C and present
    SFP_PRESENT         : in  std_logic;
    SFP_SCL             : out std_logic;
    SFP_SDA_i           : in  std_logic;
    SFP_SDA_o           : out std_logic;
    SFP_SDA_e           : out std_logic);
end adc2scsn;

architecture a of adc2scsn is

component mcm_network_interface is
 port(
        -- external Network Interface
        ser0_din  : in  std_logic ; --ring 0 data in
        ser0_dout : out std_logic ; --ring 0 data out
        ser1_din  : in  std_logic ; --ring 1 data in
        ser1_dout : out std_logic ; --ring 1 data out

        -- Bus interface
        bus_addr  : out std_logic_vector(15 downto 0); -- address to read/write
        bus_dout  : out std_logic_vector(31 downto 0); -- data out
        bus_din   : in  std_logic_vector(31 downto 0); -- data in
        bus_req   : out std_logic; -- bus request SCSN wants to do something
        bus_we    : out std_logic; -- write enable '1' indicates write cycle
                                            --              '0' indicates read cycle

        bus_ack   : in std_logic; -- allow SCSN to do something

        chipRST_n : out std_logic; -- a reset can be sent via SCSN

        --- clock and reset Signals
        reset_n   : in  std_logic; -- reset the scsn logic from outside
        clk_buf_disable : out std_logic;
        clk_buf   : in  std_logic;
        clk       : in  std_logic -- clk120
     );
end component;

component sm_adc78h89 is
generic (
         iCLK : Boolean  :=  false;
         iCNV : Boolean  :=  false;
         iDIN : Boolean  :=  false;
         iDOU : Boolean  :=  false;
         Nstep: Integer  :=   1;  -- shift step/tc
         Nacc : Integer  :=  18;  -- acc width
         Ndiv : Positive := 100); -- divide the clock to get the spi clock
port (
    clk     : in  std_logic;
    rst_n   : in  std_logic;

    -- read port to the uC bus
    disu    : in  std_logic;
    we      : in  std_logic;
    din     : in  std_logic_vector(31 downto 0);
    addr    : in  std_logic_vector(1 downto 0);
    data    : out std_logic_vector(31 downto 0);

    -- signals to the ADC78H89
    spi_sdi : in  std_logic;
    spi_sdo : out std_logic;
    spi_clk : out std_logic;
    spi_csn : out std_logic);
end component;

component ds_top is
generic (
    Nrst0   : Integer range 0 to 1023 := 512;  -- us, pull down time
    Nrsts   : Integer range 0 to  255 := 100;  -- us, sample time
    Nrst1   : Integer range 0 to 1023 := 512;  -- us, high Z time
    Nwr0    : Integer range 0 to  127 :=  80;  -- us, pull down time
    Nwr1    : Integer range 0 to   15 :=   8;  -- us, pull down time
    Nrd     : Integer range 0 to    3 :=   2;  -- us, pull down time
    Ntts    : Integer range 0 to  127 :=  90;  -- us, total time for a time slot read/write
    Nrds    : Integer range 0 to   15 :=   8); -- us, sample time for read
port (
    clk     : in    std_logic;  -- 1MHz
    rst_n   : in    std_logic;
    -- to the I/O cell
    oe      : out   std_logic;
    dout    : out   std_logic;
    din     : in    std_logic;
    -- from the configuration or just constants
    tres    : in    std_logic_vector(1 downto 0); -- resolution
    tL      : in    std_logic_vector(7 downto 0); -- T low
    tH      : in    std_logic_vector(7 downto 0); -- T high
    -- read port for the read bytes, 0..8
    presence: out   std_logic;
    rTsensL : out   std_logic_vector(7 downto 0); -- read Tsensor
    rTsensH : out   std_logic_vector(7 downto 0); --/
    rtL     : out   std_logic_vector(7 downto 0); -- read thresholds
    rtH     : out   std_logic_vector(7 downto 0)  --/
    );
end component;

component sfp_read is
port (
    RST_n               : in  std_logic; -- power up reset from the DS1818
    -- clock input from the DCS board
    CLK                 : in  std_logic; -- 40 MHz
    we                  : in  std_logic;
    addr                : in  std_logic_vector( 3 downto 0);
    din                 : in  std_logic_vector(31 downto 0);
    dout                : out std_logic_vector(31 downto 0);
    -- SFP Module I2C and present
    SFP_PRESENT         : in  std_logic;
    SFP_SCL             : out std_logic;
    SFP_SDA_i           : in  std_logic;
    SFP_SDA_o           : out std_logic;
    SFP_SDA_e           : out std_logic);
end component;

component clk_div is
GENERIC (Nd : Integer := 50);
PORT(
        clk, en : IN  STD_LOGIC;
        div     : OUT STD_LOGIC);
end component;

component mux41nbit is
generic(Nbit : Integer := 4);
    port(A0       : in  std_logic_vector(Nbit-1 downto 0);
         A1       : in  std_logic_vector(Nbit-1 downto 0);
         A2       : in  std_logic_vector(Nbit-1 downto 0);
         A3       : in  std_logic_vector(Nbit-1 downto 0);
         SEL      : in  std_logic_vector(     1 downto 0);
         Y        : out std_logic_vector(Nbit-1 downto 0));
end component;

component siu_io is
port (
    RST_n               : in  std_logic; -- power up reset from the DS1818
    -- clock input from the DCS board
    CLK                 : in  std_logic;

    we                  : in  std_logic;
    addr                : in  std_logic_vector( 3 downto 0);
    din                 : in  std_logic_vector(31 downto 0);
    dout                : out std_logic_vector(31 downto 0);

    -- bidir bus to the SIU
    fbDin               : out std_logic_vector (31 downto 0);
    fbDout              : in  std_logic_vector (31 downto 0);
    fbIEN               : out std_logic;
    fbOEN               : in  std_logic;
    fbICTRL             : out std_logic;
    fbOCTRL             : in  std_logic;
    fiBEN_N             : in  std_logic;
    fiDIR               : in  std_logic;
    fiLF_N              : in  std_logic;
    foBSY_N             : out std_logic;
    foCLK               : out std_logic);
end component;

COMPONENT CLKINT
  port(
       A         : in  STD_ULOGIC;
       Y         : out STD_ULOGIC);
END COMPONENT;

signal  Log0        : std_logic;
signal  clk         : std_logic;
signal  clk1MHz     : std_logic;
signal  clk1MHz_b   : std_logic;

signal  we_adc      : std_logic;
signal  we_sfp      : std_logic;
signal  we_siu      : std_logic;

signal  data_adc    : std_logic_vector(31 downto 0);
signal  data_ts     : std_logic_vector(31 downto 0);
signal  data_siu    : std_logic_vector(31 downto 0);
signal  data_sfp    : std_logic_vector(31 downto 0);

signal  bus_dout    : std_logic_vector(31 downto 0);
signal  bus_din     : std_logic_vector(31 downto 0);
signal  bus_req     : std_logic;
signal  bus_we      : std_logic;
signal  bus_addr    : std_logic_vector(15 downto 0);

signal  bus_saddr   : std_logic_vector( 3 downto 0);

signal  bus_ack     : std_logic;

signal  threshL     : std_logic_vector( 7 downto 0);
signal  threshH     : std_logic_vector( 7 downto 0);
signal  tres        : std_logic_vector( 1 downto 0);

begin
    Log0  <= '0';
    clk   <= clk40in;
    bus_saddr <= bus_addr(15 downto 12);

    we_sfp <= bus_we when bus_saddr = "0000" else '0';
    we_adc <= bus_we when bus_saddr = "0001" else '0';

    we_siu <= bus_we when bus_saddr = "0010" else '0';

scsn_slv: mcm_network_interface
 port map(
        -- external Network Interface
        ser0_din  => SCSNIN,
        ser0_dout => SCSNOUT,
        ser1_din  => Log0,
        ser1_dout => open,

        -- Bus interface
        bus_addr  => bus_addr,
        bus_dout  => bus_dout,
        bus_din   => bus_din,
        bus_req   => bus_req,
        bus_we    => bus_we,
                                            --              '0' indicates read cycle
        bus_ack   => bus_ack,
        chipRST_n => open,

        --- clock and reset Signals
        reset_n   => rst_n,
        clk_buf_disable => open,
        clk_buf   => clk,
        clk       => clk
     );

    process(clk)
    begin
        if rising_edge(clk) then
            bus_ack <= bus_req;
        end if;
    end process;

adc: sm_adc78h89
generic map(
--         iCLK => iCLK,
--         iCNV => iCNV,
--         iDIN => iDIN,
--         iDOU => iDOU,
         Nstep=>  1,
         Nacc => 19,
         Ndiv => 40)
port map(
    clk     => clk,
    rst_n   => rst_n,

    -- read port to the uC bus
    disu    => bus_req,
    we      => we_adc,
    din     => bus_dout,
    addr    => bus_addr(1 downto 0),
    data    => data_adc,

    -- signals to the ADC78H89
    spi_sdi => ADC_SDO,
    spi_sdo => ADC_SDI,
    spi_clk => ADC_SCLK,
    spi_csn => ADC_CSN);


    -- Temperature Sensor DS1820
    threshL <= X"00";
    threshH <= X"00";
    tres <= "11";

cdiv: clk_div
GENERIC map(Nd => 40)
PORT map(
        clk     => clk,
        en      => '1',
        div     => clk1MHz);

cbuf_1MHz: CLKINT
  port map(
       A         => clk1MHz,
       Y         => clk1MHz_b);

ds_tsens: ds_top
port map(
    clk     => clk1MHz_b,
    rst_n   => rst_n,
    -- to the I/O cell
    oe      => TSENS_e,
    dout    => TSENS_o,
    din     => TSENS_i,
    -- from the configuration or just constants
    tres    => tres,
    tL      => threshL,
    tH      => threshH,
    -- read port for the read bytes, 0..8
    presence=> open,
    rTsensL => data_ts( 7 downto  0),
    rTsensH => data_ts(15 downto  8),
    rtL     => data_ts(23 downto 16),
    rtH     => data_ts(31 downto 24));

sfp_rd: sfp_read
port map(
    RST_n               => RST_n,
    -- clock input from the DCS board
    CLK                 => CLK,
    we                  => we_sfp,
    addr                => bus_addr(3 downto 0),
    din                 => bus_dout,
    dout                => data_sfp,
    -- SFP Module I2C and present
    SFP_PRESENT         => SFP_PRESENT,
    SFP_SCL             => SFP_SCL,
    SFP_SDA_i           => SFP_SDA_i,
    SFP_SDA_o           => SFP_SDA_o,
    SFP_SDA_e           => SFP_SDA_e);

siu_i: siu_io
port map(
    RST_n               => RST_n,
    -- clock input from the DCS board
    CLK                 => CLK,

    we                  => we_siu,
    addr                => bus_addr(3 downto 0),
    din                 => bus_dout,
    dout                => data_siu,

    -- bidir bus to the SIU
    fbDin               => fbDin,
    fbDout              => fbDout,
    fbIEN               => fbIEN,
    fbOEN               => fbOEN,
    fbICTRL             => fbICTRL,
    fbOCTRL             => fbOCTRL,
    fiBEN_N             => fiBEN_N,
    fiDIR               => fiDIR,
    fiLF_N              => fiLF_N,
    foBSY_N             => foBSY_N,
    foCLK               => foCLK);

mx: mux41nbit
generic map(Nbit => 32)
    port map(
         A0       => data_sfp,
         A1       => data_adc,
         A2       => data_siu,
         A3       => data_ts,
         SEL      => bus_addr(13 downto 12),
         Y        => bus_din);
end;