-- $Id$:

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

LIBRARY fpga;
use std.textio.all;
use IEEE.std_logic_textio.all;

ENTITY ram_cnt_tb IS
generic
       (Tperiod     : time      := 25.0 ns;
        width_addr  : integer   := 7;
        width_ram   : integer   := 54; -- 3*18
        width_fast  : integer   := 8
   );
END ram_cnt_tb;

ARCHITECTURE sim OF ram_cnt_tb IS

        -- Component Declaration for the Unit Under Test (UUT)
component ram_cnt is
   generic (
     width_addr  : integer := 7;
     width_ram   : integer := 54; -- 3*18
     width_fast  : integer := 8
   );
   port (
    clk         : in  std_logic;
    rst         : in  std_logic;

    capture     : in  std_logic;
    clear       : in  std_logic;

    inputs      : in  std_logic_vector(2**width_addr-1 downto 0);
    input_mask  : in  std_logic_vector(2**width_addr-1 downto 0);

    scsn_addr   : in  std_logic_vector(15 downto 0);
    scsn_dout   : out std_logic_vector(31 downto 0);
    scsn_req    : in  std_logic;
    scsn_ack    : out std_logic
   );
 end component;

component gen_inps IS
generic(N : Positive := 7);
port(
    clk     : in    std_logic;
    rst     : in    std_logic;
    inputs  : out   std_logic_vector(2**N - 1 downto 0));
END component;

component ram_cnt_checker IS
generic(Na : Positive := 7;
        logfile : string := "./DATA/compare.log");
port(
    clk     : in    std_logic;
    rst     : in    std_logic;

    inputs  : in    std_logic_vector(2**Na-1 downto 0);
    inp_msk : in    std_logic_vector(2**Na-1 downto 0);
    track   : in    std_logic;
    clear   : in    std_logic;

    ack     : in    std_logic;
    raddr   : in    std_logic_vector(15 downto 0);
    rdata_s : in    std_logic_vector(31 downto 0));
END component;

signal clk          : std_logic;
signal rst          : std_logic;

signal capture      : std_logic;
signal clear        : std_logic;

signal inputs       : std_logic_vector(2**width_addr-1 downto 0);
signal input_mask   : std_logic_vector(inputs'range);

-- scsn interface
signal scsn_addr    : std_logic_vector(15 downto 0);
signal scsn_dout    : std_logic_vector(31 downto 0);
signal scsn_req     : std_logic;
signal scsn_ack     : std_logic;

constant scsn_addr_ea : std_logic_vector(width_addr-1 downto 0) := (others => '1');

signal read_loop_ready : Boolean;

begin
    -- clock & reset generation
    process
    begin
        clk <= '0';
        wait for Tperiod/2;
        clk <= '1';
        wait for (Tperiod - Tperiod/2);
    end process;

    rst <= '1' after 0 ns,
           '0' after 7*Tperiod;


inp_stimuli: gen_inps
generic map(N => 2**width_addr)
port map(
    clk     => clk,
    rst     => rst,
    inputs  => inputs);

    process
    begin
    -- input mask - all inputs enabled
        --input_mask <= (2|3 => '1', others => '0');
        input_mask <= (others => '1');
        clear <= '0';
        capture <= '1';
        wait until falling_edge(clk);
        wait for 100*Tperiod;
        wait for Tperiod;
        clear <= '0';
        wait for 500*Tperiod;
        capture <= '0';
        wait until falling_edge(clk);
        wait until read_loop_ready;
        wait until falling_edge(clk);
        wait for 10*Tperiod;
        capture <= '1';
        wait for 200*Tperiod; -- > 128
        capture <= '0';
        wait until falling_edge(clk);
        wait until read_loop_ready;
        wait until falling_edge(clk);
        wait for 10*Tperiod;
        capture <= '1';
        clear <= '1';
        wait for Tperiod;
        clear <= '0';
        wait for 200*Tperiod; -- > 128
        capture <= '0';
        wait until falling_edge(clk);
        wait until read_loop_ready;
        wait until falling_edge(clk);
        wait for 10*Tperiod;
        capture <= '1';
        wait for 2000*Tperiod; -- > 128
        capture <= '0';
        wait until falling_edge(clk);
        wait until read_loop_ready;
        wait until falling_edge(clk);
        wait for 10*Tperiod;
        capture <= '1';
        wait for 20000*Tperiod; -- > 128
        capture <= '0';
        wait until falling_edge(clk);
        wait until read_loop_ready;
        wait until falling_edge(clk);
        wait for 10*Tperiod;
        capture <= '1';
        wait;
    end process;

rc_check: ram_cnt_checker
generic map(Na => width_addr,
        logfile => "./DATA/compare.log")
port map(
    clk     => clk,
    rst     => rst,

    track   => capture,
    inputs  => inputs,
    inp_msk => input_mask,
    clear   => clear,

    ack     => scsn_ack,
    raddr   => scsn_addr,
    rdata_s => scsn_dout);

    process
    begin
        scsn_req <= '0';
        scsn_addr <= (others => '0');
        read_loop_ready <= true;
        wait until falling_edge(capture);
        read_loop_ready <= false;
        wait for (inputs'length+2)*Tperiod;
        -- start checking
        for i in 0 to inputs'high loop
            for j in 0 to 1 loop

                if    j=0 then scsn_addr(11) <= '0'; -- running
                elsif j=1 then scsn_addr(11) <= '1'; -- captured
                end if;

                scsn_addr(width_addr-1 downto 0) <= conv_std_logic_vector(i, width_addr);
                wait until falling_edge(clk);
                scsn_req <= '1';
                wait until scsn_ack = '1';
                wait until falling_edge(clk);
                scsn_req <= '0';
                wait until falling_edge(clk);
                wait until falling_edge(clk);
            end loop;
        end loop;
    end process;


uut: ram_cnt
   generic map(
     width_addr  => width_addr,
     width_ram   => width_ram,
     width_fast  => width_fast)
   port map(
     clk => clk,
     rst => rst,

     capture => capture,
     clear => clear,

    inputs      => inputs,
    input_mask  => input_mask,

    scsn_addr   => scsn_addr,
    scsn_dout   => scsn_dout,
    scsn_req    => scsn_req,
    scsn_ack    => scsn_ack);

end;