-- $Id$:

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY gen_inps IS
generic(N : Positive := 128);
port(
    clk     : in    std_logic;
    rst     : in    std_logic;
    inputs  : out   std_logic_vector(N-1 downto 0));
END gen_inps;

ARCHITECTURE sim OF gen_inps IS

function psrg_fun(sr : std_logic_vector) return std_logic is
variable bit0 : std_logic;
begin
 case sr'length is
  when 32 => bit0 := sr(31) xor sr(21) xor sr( 1) xor sr( 0);
  when 31 => bit0 := sr(30) xor sr(27);
  when 30 => bit0 := sr(29) xor sr( 5) xor sr( 3) xor sr( 0);
  when 29 => bit0 := sr(28) xor sr(26);
  when 28 => bit0 := sr(27) xor sr(24);
  when 27 => bit0 := sr(26) xor sr( 4) xor sr( 1) xor sr( 0);
  when 26 => bit0 := sr(25) xor sr( 5) xor sr( 1) xor sr( 0);
  when 25 => bit0 := sr(24) xor sr(21);
  when 24 => bit0 := sr(23) xor sr(22) xor sr(21) xor sr(16);
  when 23 => bit0 := sr(22) xor sr(17);
  when 22 => bit0 := sr(21) xor sr(20);
  when 21 => bit0 := sr(20) xor sr(18);
  when 20 => bit0 := sr(19) xor sr(16);
  when 19 => bit0 := sr(18) xor sr( 5) xor sr( 1) xor sr( 0);
  when 18 => bit0 := sr(17) xor sr(10);
  when 17 => bit0 := sr(16) xor sr(13);
  when 16 => bit0 := sr(15) xor sr(14) xor sr(12) xor sr( 3);
  when 14 => bit0 := sr(13) xor sr( 4) xor sr( 2) xor sr( 0);
  when 13 => bit0 := sr(12) xor sr( 3) xor sr( 2) xor sr( 0);
  when 12 => bit0 := sr(11) xor sr( 5) xor sr( 3) xor sr( 0);
  when 11 => bit0 := sr(10) xor sr( 8);
  when 10 => bit0 := sr( 9) xor sr( 6);
  when  9 => bit0 := sr( 8) xor sr( 4);
  when  8 => bit0 := sr( 7) xor sr( 5) xor sr( 4) xor sr( 3);
  when  5 => bit0 := sr( 4) xor sr( 2);
  when 15 | 7 | 6 | 4 | 3 =>
             bit0 := sr(sr'length-1) xor sr(sr'length-2);
  when others => bit0 := '-';
 end case;
 return bit0;
end;

-- pseudorandom generator of the inputs
constant Npsrg : Integer := 11;
type psrg_thresh_arr is array(0 to inputs'high) of Integer;
constant psrg_thresh : psrg_thresh_arr := (2 => 10, 3 => 30, others => Npsrg/2-1);
constant Npsrg_rd : Integer := 1; -- 1 uses the threshold, >1 copies slices from the psrg register

subtype psrg_reg_type is std_logic_vector(Npsrg-1 downto 0);
type psrg_arr_type is array(0 to inputs'high) of psrg_reg_type;

begin
    -- generate some pseudorandom inputs
    process(rst, clk)
    variable inps : std_logic_vector(inputs'range);
    variable psrg_regs : psrg_arr_type;
    begin
        if rst = '1' then
            for i in psrg_arr_type'range loop
                psrg_regs(i) := conv_std_logic_vector(i+1+129*i, psrg_regs(i)'length);
            end loop;
        elsif falling_edge(clk) then
            for i in psrg_arr_type'range loop
                psrg_regs(i) := psrg_regs(i)(psrg_regs(i)'high-1 downto 0) & psrg_fun(psrg_regs(i));
            end loop;
        end if;
        for i in psrg_arr_type'range loop
            if Npsrg_rd = 1 then -- control the rate by the threshold, only if 1 psrg_reg / 1 input
                if psrg_regs(i) > psrg_thresh(i) then
                    inputs(i) <= '1';
                else
                    inputs(i) <= '0';
                end if;
            else -- take directly slices of psrg_regs
                inputs((i+1)*Npsrg_rd-1 downto i*Npsrg_rd) <= psrg_regs(i)(Npsrg_rd-1 downto 0);
            end if;
        end loop;
    end process;
end;