-- $Id$:

LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY fpga;
use std.textio.all;

ENTITY cbb_top_tb IS
generic (Tperiod : time := 25.0 ns);
END cbb_top_tb;

ARCHITECTURE behavior OF cbb_top_tb IS

        -- Component Declaration for the Unit Under Test (UUT)
component cbb_top is

  generic (
    trg_cnt_width : integer := 12
  );

  port (
    RST_n       : in  std_logic; -- power up reset from the DS1818
    -- clock inputs
    CLK40in     : in  std_logic;
    CLK40out    : out std_logic;
    CLK40out_90 : out std_logic;
    CLK40out_180: out std_logic;
    CLK40out_270: out std_logic;
    CLK80out    : out std_logic;

    -- SCSN I/O to DCS board
    SCSNIN      : in  std_logic;
    SCSNOUT     : out std_logic;
    SCSNFEBIN   : in  std_logic;
    SCSNFEBOUT  : out std_logic;

    -- SCSN I/O to TLMU
    IF17x_SCSN_IN  : in  std_logic;
    IF17x_SCSN_OUT : out std_logic;

    -- TTCrx
    L1ACCEPT  : in std_logic;
    B_Channel : in std_logic;
    IO_C      : in std_logic_vector(1 downto 0);  -- SOR/EOR signal from DCS board

    -- TTCex
    A_ECL  : out std_logic;
    B_ECL  : out std_logic;
    BC_ECL : out std_logic;

    -- PIM
    PIMLINK  : out std_logic_vector(2 downto 0);

    -- GTU
    GTU_BUSY : in  std_logic_vector(1 downto 0);

    -- TLMU interface
    CLK40T        : out std_logic;
    RESET_TOFFPGA : out std_logic;
    CNRRL         : out std_logic;      -- enable for TLMU interface
                                        -- used for primary/backup switching
    SPA           : out std_logic;      -- spare: used for SOR/EOR signalling

    -- TLMU trigger inputs
    TLMU_trg      : in  std_logic_vector(7 downto 0);

    -- input from CB-A/C
    CB_A : in  std_logic_vector(1 downto 0);
    CB_C : in  std_logic_vector(1 downto 0);

    -- Front-Panel LEDs
    LED : out std_logic_vector(1 to 2);

    -- unused
    SPC    : in  std_logic;
    SPD    : in  std_logic;
    CB_TOF : out std_logic;             -- ???
    L_OUTSP : out std_logic;      -- spare to TLMU
    SPB    : out std_logic;             -- spare to TLMU
    S1_IN  : in  std_logic_vector(1 to 2);
    S1_OUT : out std_logic_vector(1 to 2);
    S2_IN  : in  std_logic_vector(1 to 2);
    S2_OUT : out std_logic_vector(1 to 2)
  );
end component;

COMPONENT ser_int
  generic (
    wait_delay :     integer := 100;
    init_delay :     integer := 4095;
    file_in    :     string  := "./DATA/sc_send.dat";
    file_out   :     string  := "./DATA/sc_recv.dat" );
 PORT(
         reset_n  : IN  std_logic;
         clk      : IN  std_logic;
         ready    : IN  std_logic;
         ser0din  : IN  std_logic;
         ser0dout : OUT std_logic;
         pre      : OUT std_logic );
 END COMPONENT;

--Inputs
SIGNAL reset_n  :  std_logic;
SIGNAL clk      :  std_logic := '1';
SIGNAL ready    :  std_logic := '0';
SIGNAL ser_dout :  std_logic_vector(0 to 1);

signal Log0     : std_logic;

signal CLK40out     :  std_logic;
signal CLK40out_90  :  std_logic;
signal CLK40out_180 :  std_logic;
signal CLK40out_270 :  std_logic;
signal CLK80out     :  std_logic;

    -- TTCrx
signal L1ACCEPT : std_logic := '0';
signal B_Channel: std_logic := '0';
signal IO_C     : std_logic_vector(1 downto 0) := "00";  -- SOR/EOR signal from DCS board

    -- TTCex
signal A_ECL    :  std_logic;
signal B_ECL    :  std_logic;
signal BC_ECL   :  std_logic;

    -- PIM
signal PIMLINK  : std_logic_vector(2 downto 0);

    -- GTU
signal GTU_BUSY : std_logic_vector(1 downto 0) := "00";

    -- TLMU interface
signal CLK40T   :  std_logic;
signal RESET_TOFFPGA :  std_logic;
signal CNRRL    :  std_logic;      -- enable for TLMU interface
                                     -- used for primary/backup switching
signal SPA      :  std_logic;      -- spare: used for SOR/EOR signalling

    -- TLMU trigger inputs
signal TLMU_trg : std_logic_vector(7 downto 0) := (others => '0');

    -- input from CB-A/C
signal CB_A     : std_logic_vector(1 downto 0) := "00";
signal CB_C     : std_logic_vector(1 downto 0) := "00";

    -- Front-Panel LEDs
signal LED      :  std_logic_vector(1 to 2);

    -- unused
signal SPC      : std_logic := '0';
signal SPD      : std_logic := '0';
signal CB_TOF   : std_logic;      -- ???
signal L_OUTSP  : std_logic;      -- spare to TLMU
signal SPB      : std_logic;      -- spare to TLMU
signal S1_IN    : std_logic_vector(1 to 2) := "00";
signal S1_OUT   : std_logic_vector(1 to 2);
signal S2_IN    : std_logic_vector(1 to 2) := "00";
signal S2_OUT   : std_logic_vector(1 to 2);

BEGIN

        Log0 <= '0';

scsnmast: ser_int
        PORT MAP(
        reset_n  => reset_n,
        clk      => clk,
        ready    => ready,
        ser0din  => ser_dout(1),
        ser0dout => ser_dout(0)
);

uut: cbb_top

--  generic map(
--    trg_cnt_width : integer := 12
--  );

  port map(
    RST_n       => reset_n,
    -- clock inputs
    CLK40in     => clk,
    CLK40out    => CLK40out,
    CLK40out_90 => CLK40out_90,
    CLK40out_180=> CLK40out_180,
    CLK40out_270=> CLK40out_270,
    CLK80out    => CLK80out,

    -- SCSN I/O to DCS board
    SCSNIN      => ser_dout(0),
    SCSNOUT     => ser_dout(1),
    SCSNFEBIN   => Log0,
    SCSNFEBOUT  => open,

    -- SCSN I/O to TLMU
    IF17x_SCSN_IN  => Log0,
    IF17x_SCSN_OUT => open,

    -- TTCrx
    L1ACCEPT  => L1ACCEPT,
    B_Channel => B_Channel,
    IO_C      => IO_C,

    -- TTCex
    A_ECL  => A_ECL,
    B_ECL  => B_ECL,
    BC_ECL => BC_ECL,

    -- PIM
    PIMLINK  => PIMLINK,

    -- GTU
    GTU_BUSY => GTU_BUSY,

    -- TLMU interface
    CLK40T        => CLK40T,
    RESET_TOFFPGA => RESET_TOFFPGA,
    CNRRL         => CNRRL,
                                        -- used for primary/backup switching
    SPA           => SPA,

    -- TLMU trigger inputs
    TLMU_trg      => TLMU_trg,

    -- input from CB-A/C
    CB_A => CB_A,
    CB_C => CB_C,

    -- Front-Panel LEDs
    LED => LED,

    -- unused
    SPC    => SPC,
    SPD    => SPD,
    CB_TOF => CB_TOF,
    L_OUTSP => L_OUTSP,
    SPB    => SPB,
    S1_IN  => S1_IN,
    S1_OUT => S1_OUT,
    S2_IN  => S2_IN,
    S2_OUT => S2_OUT
  );

        clk <= NOT clk after Tperiod/2;
        reset_n <= '0' after 0 us,
                   '1' after 2 us,
                   '0' after 3 us,
                   '1' after 4 us;

END;