# $Id$:

# specifiy the technology, xilinx or actel
# This works for ram_cnt simulation only! For cbb the choice xlinx-actel is not ready!
technology=actel
#technology=xilinx

# for Xilinx compile once unisim
# for Actel compile once proasic3e

# for ram_cnt only start fram_cnt (functional simulation)
# for cbb start fcbb

cbb_dir=../../../CB-B/trunk

scsn_sources=\
$(cbb_dir)/src/mcm/hamm34enc67.vhd           \
$(cbb_dir)/src/mcm/hamm67dec34.vhd           \
$(cbb_dir)/src/mcm/hamm_reg.vhd              \
$(cbb_dir)/src/mcm/mcm_nw_apl.vhd            \
$(cbb_dir)/src/mcm/mcm_nw_timer.vhd          \
$(cbb_dir)/src/mcm/mcm_nw_destuffing.vhd     \
$(cbb_dir)/src/mcm/mcm_nw_stuffing.vhd       \
$(cbb_dir)/src/mcm/mcm_nw_outbuf.vhd         \
$(cbb_dir)/src/mcm/mcm_nw_inbuf.vhd          \
$(cbb_dir)/src/mcm/mcm_nw_bittiming.vhd      \
$(cbb_dir)/src/mcm/mcm_nw_sendtiming.vhd     \
$(cbb_dir)/src/mcm/mcm_nw_dll.vhd            \
$(cbb_dir)/src/mcm/mcm_nw_nwsl.vhd           \
$(cbb_dir)/src/mcm/mcm_nw_nwl.vhd            \
$(cbb_dir)/src/mcm/mcm_nw_pl.vhd             \
$(cbb_dir)/src/mcm/mcm_network_interface.vhd

siu_sources=\
../src/SIU/my_utilities.vhd   \
../src/SIU/my_conversions.vhd \
../src/SIU/cm_siu.vhd         \
../src/SIU/crc16.vhd          \
../src/SIU/fee_if.vhd         \
../src/SIU/framing.vhd        \
../src/SIU/i2c_if.vhd         \
../src/SIU/lm_siu.vhd         \
../src/SIU/rx_in.vhd          \
../src/SIU/parity_chk.vhd     \
../src/SIU/parity_gen.vhd     \
../src/SIU/pm_if.vhd          \
../src/SIU/rx_cmd.vhd         \
../src/SIU/rx_crc.vhd         \
../src/SIU/rx_data.vhd        \
../src/SIU/rxd_fifo.vhd       \
../src/SIU/rxdf_core.vhd      \
../src/SIU/txd_fifo.vhd       \
../src/SIU/txdf_core.vhd      \
../src/SIU/siu_top_core.vhd

# for cbb the choice xlinx-actel is not ready!
cbb_sources=\
$(cbb_dir)/arch/$(technology)/cores/pll40_40d_80.vhd    \
$(cbb_dir)/arch/$(technology)/cores/dp_sram_actel.vhd   \
$(cbb_dir)/arch/$(technology)/cores/ram4k9_actel.vhd    \
$(cbb_dir)/arch/$(technology)/cores/lut_8k_2.vhd        \
$(cbb_dir)/arch/$(technology)/cores/dp_sram_128x54.vhd  \
$(cbb_dir)/arch/$(technology)/cores/dp_sram_512x32.vhd  \
$(cbb_dir)/arch/$(technology)/cores/ram4k_w8_r1.vhd     \
$(cbb_dir)/src/misc/bc_cnt.vhd                  \
$(cbb_dir)/src/misc/pt_align.vhd                \
$(cbb_dir)/src/misc/ttcex_out.vhd               \
$(cbb_dir)/src/misc/cb_ac_sample.vhd            \
$(cbb_dir)/src/cores/psrg.vhd                   \
$(cbb_dir)/src/misc/del_coinc_cnt_en.vhd        \
$(cbb_dir)/src/misc/ram_cnt_ref.vhd             \
$(cbb_dir)/src/misc/ram_cnt_log.vhd             \
$(cbb_dir)/src/misc/ram_cnt_checker.vhd         \
$(cbb_dir)/src/misc/ram_cnt_cnt.vhd             \
$(cbb_dir)/src/misc/ram_cnt.vhd                 \
$(cbb_dir)/src/misc/random_pulser.vhd           \
$(cbb_dir)/src/misc/shiftreg_piso.vhd           \
$(cbb_dir)/src/misc/sys_config.vhd              \
$(cbb_dir)/src/misc/trg_lut.vhd                 \
$(cbb_dir)/src/misc/busy.vhd                    \
$(cbb_dir)/src/tlmureceiver/ucrc_par.vhd        \
$(cbb_dir)/src/tlmureceiver/cbbr_iserdes.vhd    \
$(cbb_dir)/src/tlmureceiver/cbbr_top.vhd        \
$(cbb_dir)/src/ttcreceiver/channelB_reg.vhd     \
$(cbb_dir)/src/ttcreceiver/serialb_com.vhd      \
$(cbb_dir)/src/ttcreceiver/ttc_receiver_top.vhd \
$(cbb_dir)/src/clock_gen.vhd                    \
$(cbb_dir)/src/bc_trigger.vhd                   \
$(cbb_dir)/src/timing_analyzer.vhd              \
$(cbb_dir)/src/ctp_tin.vhd                      \
$(cbb_dir)/src/trg_emulator.vhd                 \
$(cbb_dir)/src/trg_generator.vhd                \
$(cbb_dir)/src/cbb_top.vhd

ifeq ($(technology),actel)
ram_cnt_src=\
$(cbb_dir)/arch/$(technology)/cores/dp_sram_actel.vhd   \
$(cbb_dir)/arch/$(technology)/cores/dp_sram_128x54.vhd  \
$(cbb_dir)/src/misc/ram_cnt_ref.vhd             \
$(cbb_dir)/src/misc/ram_cnt_log.vhd             \
$(cbb_dir)/src/misc/ram_cnt_checker.vhd         \
$(cbb_dir)/src/misc/ram_cnt_cnt.vhd             \
$(cbb_dir)/src/misc/ram_cnt.vhd
endif

ifeq ($(technology),xilinx)
ram_cnt_src=\
$(cbb_dir)/arch/$(technology)/cores/dp_sram_128x54.vhd  \
$(cbb_dir)/src/misc/ram_cnt_ref.vhd             \
$(cbb_dir)/src/misc/ram_cnt_log.vhd             \
$(cbb_dir)/src/misc/ram_cnt_checker.vhd         \
$(cbb_dir)/src/misc/ram_cnt_cnt.vhd             \
$(cbb_dir)/src/misc/ram_cnt.vhd
endif

ram_cnt_tb_src=\
./SRC/gen_inps.vhd \
./SRC/ram_cnt_tb.vhd

adc_sources=\
../src/ADC/adc78h89.vhd    \
../src/ADC/relax.vhd       \
../src/ADC/sm_adc78h89.vhd \
../src/ADC/ds_pack.vhd     \
../src/ADC/program.vhd     \
../src/ADC/timeslots.vhd   \
../src/ADC/byteslots.vhd   \
../src/ADC/ds_top.vhd      \
../src/ADC/sfp_read.vhd    \
../src/ADC/siu_io.vhd      \
../src/ADC/clk_div.vhd     \
../src/ADC/mux41nbit.vhd   \
../src/ADC/adc2scsn.vhd

ioc_sources_vhd=\
../src/cores/oddr2.vhd  \
../src/cores/ibuf.vhd   \
../src/cores/obufds.vhd \
../src/cores/iddr2.vhd

ioc_sources_v=\
../src/cores/ibufds.v   \
../src/cores/obuf.v

cbb_tb_sources=  \
./SRC/pre_enc_sim.vhd  \
./SRC/ser_int_mast.vhd \
./SRC/ser_int.vhd      \
./SRC/cbb_top_tb.vhd

scsn_tcs_files=./CNF/test.tcs

# source for place & route simulation
source_par=../NETLIST/top_ba.vhd
source_sdf=../NETLIST/top_ba.sdf

# directory with the Actel software

# Windows
#actel_dir=c:\Programme\Actel\Libero_v9.1\Designer
# subdirectory with the simulation models
#actel_models=$(actel_dir)\lib\vtl\95

# Linux
actel_dir=/usr/local/actel/Libero_v9.1/Libero
# subdirectory with the simulation models
actel_models=$(actel_dir)/lib/vtl/95


# The location of the Xilinx simulation models
xilinx_models=c:\Xilinx\13.1\ISE_DS\ISE\vhdl\src

# The Xilinx unisim library
unisim:
	@vlib $@
	@echo "Compiling the Xilinx Simulation Library $@..."
	vcom -quiet -93 -work $@ "$(xilinx_models)\unisims\unisim_VPKG.vhd"
	vcom -quiet -93 -work $@ "$(xilinx_models)\unisims\unisim_VCOMP.vhd"
	vcom -quiet -93 -work $@ "$(xilinx_models)\unisims\primitive\*.vhd"
#	vcom -quiet -93 -work $@ "$(xilinx_models)\unisims\primitive\RAMB16_S18_S18.vhd"
#	vcom -quiet -93 -work $@ "$(xilinx_models)\unisims\unisim_VITAL.vhd"

# The Xilinx simprim library
simprim:
	@vlib $@
	@echo "Compiling the Xilinx Simulation Library $@..."
	vcom -quiet -93 -work $@ "$(xilinx_models)\simprims\simprim_Vpackage_mti.vhd"
	vcom -quiet -93 -work $@ "$(xilinx_models)\simprims\simprim_Vcomponents_mti.vhd"
#	vcom -quiet -93 -work $@ "$(xilinx_models)\simprims\simprim_SMODEL_mti.vhd"
#	vcom -quiet -93 -work $@ "$(xilinx_models)\simprims\simprim_VITAL_mti.vhd"

proasic3 proasic3e:
	@vlib $@
	@echo "Compiling the Actel Simulation Models for $@ Family..."
	vcom -quiet -work $@ -explicit "$(actel_models)/$@.vhd"

# compile for functional simulation
ccbb: functional ../build/buildstamp.vhd $(scsn_sources) $(cbb_sources) Makefile
	vmap fpga functional
	vcom -quiet -work functional -93 -explicit ../build/buildstamp.vhd
	@echo "-------------------------"
	@echo " *** SCSN compile..."
	vcom -quiet -work functional -93 -explicit $(scsn_sources)
	@echo "-------------------------"
	@echo " *** CB-B compile..."
	vcom -quiet -work functional -2008 -explicit $(cbb_sources)
	@echo "-------------------------"

# compile ram_cnt for functional simulation
cram_cnt: functional work $(ram_cnt_src) $(ram_cnt_tb_src) Makefile
	vmap fpga functional
	@echo " *** ram_cnt compile..."
	vcom -quiet -work functional -2008 -novopt -explicit $(ram_cnt_src)
	@echo "-------------------------"
	@echo " *** ram_cnt_tb compile..."
	vcom -quiet -work work -novopt -2008 -explicit $(ram_cnt_tb_src)
	@echo "-------------------------"

# start functional simulation of CB-B
fram_cnt: cram_cnt
	vsim -quiet -t 1ps -novopt 'work.ram_cnt_tb' -do wave_ram_cnt_$(technology).do

# compile for functional simulation
ctop: ccbb $(siu_sources) $(adc_sources) $(ioc_sources_vhd) $(ioc_sources_v) ../src/TOP_PAD/top.v Makefile
	@echo " *** SIU compile..."
	vcom -quiet -work functional -2008 -explicit $(siu_sources)
	@echo "-------------------------"
	@echo " *** ADCs compile..."
	vcom -quiet -work functional -2008 -explicit $(adc_sources)
	@echo "-------------------------"
	@echo " *** IO cell wrapper compile..."
	vcom -quiet -work functional -2008 -explicit $(ioc_sources_vhd)
	vlog  $(ioc_sources_v)
	@echo "-------------------------"
	@echo " *** compile the top level of the design..."
	vlog  -work functional +define+ACTEL ../src/TOP_PAD/top.v
	@echo "-------------------------"
	@echo " *** compile the test-bench files..."

# compile the place & route netlist
ctop_par: $(source_par)
	if [ -d par ]; then rm -rf par
	vlib par
	vmap fpga par
	vcom -quiet -work par -2008 -explicit $(source_par)

ccbbtb: work $(cbb_tb_sources) $(scsn_sources)
	@echo " *** SCSN compile..."
	vcom -quiet -work work -93 -explicit $(scsn_sources)
	@echo "-------------------------"
	@echo " *** compile cbb-top testbench..."
	vcom -quiet -work work -novopt -2008 -explicit $(cbb_tb_sources)
	@echo "-------------------------"

# start functional simulation of CB-B
fcbb: ccbb ccbbtb
	vsim -quiet -t 1ps 'work.cbb_top_tb' -do wave_cbb.do

# create work library
functional work:
	if [ ! -d $@ ]; then vlib $@; fi

./DATA/sc_send.dat: $(scsn_tcs_files)
	trapcc $(scsn_tcs_files) >$@

# clean up
clean:
	rm -rf work par functional

clean_all: clean
	rm -rf proasic3 proasic3e unisim simprim

.PHONY : ccbb ctop ctop_par ccbbtb fcbb clean