-- POST-SYNTHESIS TIMING REPORTS ARE ESTIMATES AND SHOULD NOT BE RELIED ON TO MAKE QoR DECISIONS. For accurate timing information, please run place-and-route (P&R) and review P&R generated timing reports. -- Device: Actel - ProASIC3E : A3PE1500 : -2 -- CTE report timing.. CTE Path Report Critical path #1, (path slack = 2.293): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_s_arstn/CLK DFN1C1 0.000 up i_SIU/reg_s_arstn/Q DFN1C1 0.299 0.299 dn i_SIU/s_arstn (net) 2.146 1227 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst/RESET FIFO4K18 2.445 dn i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst/EMPTY FIFO4K18 1.439 3.884 up i_SIU/TXDF_INST_TXDF_CORE_INST_EMPTY_0 (net) 0.326 2 i_SIU/TXDF_INST_txdf_e_i/B NAND2B 4.210 up i_SIU/TXDF_INST_txdf_e_i/Y NAND2B 0.298 4.508 up i_SIU/TXDF_INST_txdf_e_i (net) 0.326 2 i_SIU/ix14207z40557/B AO1B 4.834 up i_SIU/ix14207z40557/Y AO1B 0.273 5.107 up i_SIU/nx14207z2 (net) 0.326 2 i_SIU/NOT_TXDF_INST_ix44315z40560/C AO1E 5.433 up i_SIU/NOT_TXDF_INST_ix44315z40560/Y AO1E 0.298 5.731 dn i_SIU/nx44315z2 (net) 0.191 1 i_SIU/ix44315z14896/S MX2 5.922 dn i_SIU/ix44315z14896/Y MX2 0.184 6.106 dn i_SIU/nx44315z1 (net) 0.191 1 i_SIU/TXDF_INST_reg_txdf_empty/D DFN1P0 6.297 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 6.297 ( 44.32% cell delay, 55.68% net delay ) ----------- Slack: 2.293 Critical path #2, (path slack = 2.396): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(14)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(14)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(14) (net) 0.817 6 i_SIU/FRAMING_INST/ix50624z49935/B NAND2B 1.116 dn i_SIU/FRAMING_INST/ix50624z49935/Y NAND2B 0.298 1.414 dn i_SIU/FRAMING_INST/nx50624z2 (net) 1.286 11 i_SIU/FRAMING_INST/NOT_ix49627z50935/C NAND3C 2.700 dn i_SIU/FRAMING_INST/NOT_ix49627z50935/Y NAND3C 0.342 3.042 dn i_SIU/FRAMING_INST/nx49627z4 (net) 0.714 5 i_SIU/FRAMING_INST/ix45639z24339/A NAND3 3.756 dn i_SIU/FRAMING_INST/ix45639z24339/Y NAND3 0.244 4.000 up i_SIU/FRAMING_INST/nx45639z3 (net) 1.225 10 i_SIU/FRAMING_INST/ix45639z40563/C AO1D 5.225 up i_SIU/FRAMING_INST/ix45639z40563/Y AO1D 0.298 5.523 up i_SIU/FRAMING_INST/nx45639z6 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/B NAND2 5.714 up i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/Y NAND2 0.289 6.003 dn i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts2(10)/D DFN1C0 6.194 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 6.194 ( 28.58% cell delay, 71.42% net delay ) ----------- Slack: 2.396 Critical path #3, (path slack = 2.821): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(13)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(13)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(13) (net) 0.454 3 i_SIU/FRAMING_INST/ix50624z49935/A NAND2B 0.753 dn i_SIU/FRAMING_INST/ix50624z49935/Y NAND2B 0.236 0.989 dn i_SIU/FRAMING_INST/nx50624z2 (net) 1.286 11 i_SIU/FRAMING_INST/NOT_ix49627z50935/C NAND3C 2.275 dn i_SIU/FRAMING_INST/NOT_ix49627z50935/Y NAND3C 0.342 2.617 dn i_SIU/FRAMING_INST/nx49627z4 (net) 0.714 5 i_SIU/FRAMING_INST/ix45639z24339/A NAND3 3.331 dn i_SIU/FRAMING_INST/ix45639z24339/Y NAND3 0.244 3.575 up i_SIU/FRAMING_INST/nx45639z3 (net) 1.225 10 i_SIU/FRAMING_INST/ix45639z40563/C AO1D 4.800 up i_SIU/FRAMING_INST/ix45639z40563/Y AO1D 0.298 5.098 up i_SIU/FRAMING_INST/nx45639z6 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/B NAND2 5.289 up i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/Y NAND2 0.289 5.578 dn i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts2(10)/D DFN1C0 5.769 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 5.769 ( 29.61% cell delay, 70.39% net delay ) ----------- Slack: 2.821 Critical path #4, (path slack = 2.838): SOURCE CLOCK: name: i_cbb/clock_generation_ipll_Core/GLC period: 12.500000 Times are relative to the 1st rising edge DEST CLOCK: name: i_cbb/clock_generation_ipll_Core/GLA period: 25.000000 Times are relative to the 1st rising edge NAME GATE DELAY ARRIVAL DIR FANOUT iddr_CB_A_iddr/CLK DDR_REG 0.000 up iddr_CB_A_iddr/QR DDR_REG 0.082 0.082 up CB_A_i(0) (net) 1.286 11 i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/ix19627z50933/C NAND3A 1.368 up i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/ix19627z50933/Y NAND3A 0.294 1.662 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/nx19627z4 (net) 0.191 1 i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/ix19627z40558/C AO1D 1.853 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/ix19627z40558/Y AO1D 0.298 2.151 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/nx19627z1 (net) 0.191 1 i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/q_next_2n1ss1(4)/A AX1 2.342 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/q_next_2n1ss1(4)/Y AX1 0.455 2.797 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/q_next_2n1ss1(4) (net) 0.191 1 i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/ix64606z2957/C AND3B 2.988 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/ix64606z2957/Y AND3B 0.303 3.291 dn i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/q_next(4) (net) 0.326 2 i_cbb/ram_cnt_inst/gen_cnt_fast_14_cnt_i/reg_q_hold(4)/D DFN1E1 3.617 dn Initial edge separation: 6.250 Source clock delay: - 1.995 Dest clock delay: + 2.610 ----------- Edge separation: 6.865 Setup constraint: - 0.410 ----------- Data required time: 6.455 Data arrival time: - 3.617 ( 39.59% cell delay, 60.41% net delay ) ----------- Slack: 2.838 Critical path #5, (path slack = 2.911): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(16)/CLK DFN1C0 0.000 up i_SIU/reg_q(16)/Q DFN1C0 0.299 0.299 dn i_SIU/RXIN_INST_v_por_timer(16) (net) 1.123 9 i_SIU/NOT_ix32078z50931/A NAND3A 1.422 dn i_SIU/NOT_ix32078z50931/Y NAND3A 0.343 1.765 dn i_SIU/nx32078z2 (net) 0.454 3 i_SIU/NOT_ix32078z50930/A NAND3A 2.219 dn i_SIU/NOT_ix32078z50930/Y NAND3A 0.343 2.562 dn i_SIU/nx32078z1 (net) 0.714 5 i_SIU/NOT_a(0)/A NAND3C 3.276 dn i_SIU/NOT_a(0)/Y NAND3C 0.227 3.503 dn i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 4.626 dn i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 4.969 dn i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 5.160 dn i_SIU/ix17096z21032/Y XA1A 0.428 5.588 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 5.779 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 5.779 ( 34.31% cell delay, 65.69% net delay ) ----------- Slack: 2.911 Critical path #6, (path slack = 3.240): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(11)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(11)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(11) (net) 0.454 3 i_SIU/FRAMING_INST/ix50624z49937/B NAND2B 0.753 dn i_SIU/FRAMING_INST/ix50624z49937/Y NAND2B 0.298 1.051 dn i_SIU/FRAMING_INST/nx50624z4 (net) 0.817 6 i_SIU/FRAMING_INST/NOT_ix49627z50935/B NAND3C 1.868 dn i_SIU/FRAMING_INST/NOT_ix49627z50935/Y NAND3C 0.330 2.198 dn i_SIU/FRAMING_INST/nx49627z4 (net) 0.714 5 i_SIU/FRAMING_INST/ix45639z24339/A NAND3 2.912 dn i_SIU/FRAMING_INST/ix45639z24339/Y NAND3 0.244 3.156 up i_SIU/FRAMING_INST/nx45639z3 (net) 1.225 10 i_SIU/FRAMING_INST/ix45639z40563/C AO1D 4.381 up i_SIU/FRAMING_INST/ix45639z40563/Y AO1D 0.298 4.679 up i_SIU/FRAMING_INST/nx45639z6 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/B NAND2 4.870 up i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/Y NAND2 0.289 5.159 dn i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts2(10)/D DFN1C0 5.350 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 5.350 ( 32.86% cell delay, 67.14% net delay ) ----------- Slack: 3.240 Critical path #7, (path slack = 3.259): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXDATA_INST/reg_b_rx_data/CLK DFN1C0 0.000 up i_SIU/RXDATA_INST/reg_b_rx_data/Q DFN1C0 0.240 0.240 up i_SIU/RXDATA_INST/p_b_rx_data (net) 1.756 26 i_SIU/RXDATA_INST/b_ivsof_2n21s1/A NAND2B 1.996 up i_SIU/RXDATA_INST/b_ivsof_2n21s1/Y NAND2B 0.236 2.232 up i_SIU/RXDATA_INST/p_b_ivsof_2n21s1 (net) 0.585 4 i_SIU/RXDATA_INST/ix63900z48516/A AND3 2.817 up i_SIU/RXDATA_INST/ix63900z48516/Y AND3 0.244 3.061 up i_SIU/RXDATA_INST/nx63900z2 (net) 0.919 7 i_SIU/RXCMD_INST/ix62670z40560/A AO1C 3.980 up i_SIU/RXCMD_INST/ix62670z40560/Y AO1C 0.182 4.162 dn i_SIU/RXCMD_INST/nx62670z4 (net) 0.191 1 i_SIU/RXCMD_INST/ix62670z40556/C AO1A 4.353 dn i_SIU/RXCMD_INST/ix62670z40556/Y AO1A 0.298 4.651 dn i_SIU/RXCMD_INST/nx62670z2 (net) 0.191 1 i_SIU/RXCMD_INST/ix62670z5366/C AO1 4.842 dn i_SIU/RXCMD_INST/ix62670z5366/Y AO1 0.298 5.140 dn i_SIU/RXCMD_INST/nx62670z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_rxc_present(7)/D DFN1C0 5.331 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 5.331 ( 28.10% cell delay, 71.90% net delay ) ----------- Slack: 3.259 Critical path #8, (path slack = 3.302): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(12)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(12)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(12) (net) 0.454 3 i_SIU/FRAMING_INST/ix50624z49937/A NAND2B 0.753 dn i_SIU/FRAMING_INST/ix50624z49937/Y NAND2B 0.236 0.989 dn i_SIU/FRAMING_INST/nx50624z4 (net) 0.817 6 i_SIU/FRAMING_INST/NOT_ix49627z50935/B NAND3C 1.806 dn i_SIU/FRAMING_INST/NOT_ix49627z50935/Y NAND3C 0.330 2.136 dn i_SIU/FRAMING_INST/nx49627z4 (net) 0.714 5 i_SIU/FRAMING_INST/ix45639z24339/A NAND3 2.850 dn i_SIU/FRAMING_INST/ix45639z24339/Y NAND3 0.244 3.094 up i_SIU/FRAMING_INST/nx45639z3 (net) 1.225 10 i_SIU/FRAMING_INST/ix45639z40563/C AO1D 4.319 up i_SIU/FRAMING_INST/ix45639z40563/Y AO1D 0.298 4.617 up i_SIU/FRAMING_INST/nx45639z6 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/B NAND2 4.808 up i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/Y NAND2 0.289 5.097 dn i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts2(10)/D DFN1C0 5.288 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 5.288 ( 32.07% cell delay, 67.93% net delay ) ----------- Slack: 3.302 Critical path #9, (path slack = 3.426): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(0)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(0)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx52268z2 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_ix22081z24342/B NAND2 0.884 dn i_SIU/CMSIU_INST/NOT_ix22081z24342/Y NAND2 0.289 1.173 up i_SIU/CMSIU_INST/nx22081z5 (net) 0.326 2 i_SIU/CMSIU_INST/NOT_ix22081z50933/A NAND3A 1.499 up i_SIU/CMSIU_INST/NOT_ix22081z50933/Y NAND3A 0.343 1.842 up i_SIU/CMSIU_INST/nx22081z4 (net) 1.123 9 i_SIU/CMSIU_INST/NOT_ix22081z50934/A NAND3C 2.965 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.227 3.192 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 4.111 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 4.454 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 4.645 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 5.073 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 5.264 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 5.264 ( 36.65% cell delay, 63.35% net delay ) ----------- Slack: 3.426 Critical path #10, (path slack = 3.441): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(0)_dup_380/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(0)_dup_380/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx33974z2 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_ix32078z24339/B NAND2 0.884 dn i_SIU/LMSIU_INST/NOT_ix32078z24339/Y NAND2 0.289 1.173 up i_SIU/LMSIU_INST/nx32078z2 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix32078z50930/A NAND3A 1.499 up i_SIU/LMSIU_INST/NOT_ix32078z50930/Y NAND3A 0.343 1.842 up i_SIU/LMSIU_INST/nx32078z1 (net) 0.714 5 i_SIU/LMSIU_INST/NOT_a(0)/A NAND3C 2.556 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.227 2.783 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 4.008 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 4.463 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 4.654 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 4.958 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 5.149 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 5.149 ( 37.23% cell delay, 62.77% net delay ) ----------- Slack: 3.441 Critical path #11, (path slack = 3.605): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(1)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(1)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z6 (net) 0.454 3 i_SIU/CMSIU_INST/NOT_ix22081z24342/A NAND2 0.753 dn i_SIU/CMSIU_INST/NOT_ix22081z24342/Y NAND2 0.241 0.994 up i_SIU/CMSIU_INST/nx22081z5 (net) 0.326 2 i_SIU/CMSIU_INST/NOT_ix22081z50933/A NAND3A 1.320 up i_SIU/CMSIU_INST/NOT_ix22081z50933/Y NAND3A 0.343 1.663 up i_SIU/CMSIU_INST/nx22081z4 (net) 1.123 9 i_SIU/CMSIU_INST/NOT_ix22081z50934/A NAND3C 2.786 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.227 3.013 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.932 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 4.275 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 4.466 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.894 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 5.085 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 5.085 ( 36.99% cell delay, 63.01% net delay ) ----------- Slack: 3.605 Critical path #12, (path slack = 3.620): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(1)_dup_379/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(1)_dup_379/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx32078z3 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix32078z24339/A NAND2 0.753 dn i_SIU/LMSIU_INST/NOT_ix32078z24339/Y NAND2 0.241 0.994 up i_SIU/LMSIU_INST/nx32078z2 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix32078z50930/A NAND3A 1.320 up i_SIU/LMSIU_INST/NOT_ix32078z50930/Y NAND3A 0.343 1.663 up i_SIU/LMSIU_INST/nx32078z1 (net) 0.714 5 i_SIU/LMSIU_INST/NOT_a(0)/A NAND3C 2.377 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.227 2.604 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 3.829 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 4.284 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 4.475 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 4.779 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 4.970 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.970 ( 37.61% cell delay, 62.39% net delay ) ----------- Slack: 3.620 Critical path #13, (path slack = 3.654): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(7)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(7)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(7) (net) 0.326 2 i_SIU/FRAMING_INST/ix28945z49935/B NAND2B 0.625 dn i_SIU/FRAMING_INST/ix28945z49935/Y NAND2B 0.298 0.923 dn i_SIU/FRAMING_INST/nx28945z2 (net) 1.286 11 i_SIU/FRAMING_INST/ix29942z40558/B AO1D 2.209 dn i_SIU/FRAMING_INST/ix29942z40558/Y AO1D 0.308 2.517 up i_SIU/FRAMING_INST/nx29942z1 (net) 1.470 14 i_SIU/FRAMING_INST/ix29942z40557/B AO1A 3.987 up i_SIU/FRAMING_INST/ix29942z40557/Y AO1A 0.269 4.256 up i_SIU/FRAMING_INST/nx29942z3 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/C AO1C 4.447 up i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/Y AO1C 0.298 4.745 dn i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts1(14)/D DFN1C0 4.936 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.936 ( 29.82% cell delay, 70.18% net delay ) ----------- Slack: 3.654 Critical path #14, (path slack = 3.679): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(0)/CLK DFN1C0 0.000 up i_SIU/reg_q(0)/Q DFN1C0 0.299 0.299 dn i_SIU/nx32078z3 (net) 0.454 3 i_SIU/NOT_ix32078z50931/B NAND3A 0.753 dn i_SIU/NOT_ix32078z50931/Y NAND3A 0.244 0.997 up i_SIU/nx32078z2 (net) 0.454 3 i_SIU/NOT_ix32078z50930/A NAND3A 1.451 up i_SIU/NOT_ix32078z50930/Y NAND3A 0.343 1.794 up i_SIU/nx32078z1 (net) 0.714 5 i_SIU/NOT_a(0)/A NAND3C 2.508 up i_SIU/NOT_a(0)/Y NAND3C 0.227 2.735 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 3.858 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 4.201 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 4.392 up i_SIU/ix17096z21032/Y XA1A 0.428 4.820 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 5.011 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 5.011 ( 37.60% cell delay, 62.40% net delay ) ----------- Slack: 3.679 Critical path #15, (path slack = 3.716): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(8)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(8)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(8) (net) 0.326 2 i_SIU/FRAMING_INST/ix28945z49935/A NAND2B 0.625 dn i_SIU/FRAMING_INST/ix28945z49935/Y NAND2B 0.236 0.861 dn i_SIU/FRAMING_INST/nx28945z2 (net) 1.286 11 i_SIU/FRAMING_INST/ix29942z40558/B AO1D 2.147 dn i_SIU/FRAMING_INST/ix29942z40558/Y AO1D 0.308 2.455 up i_SIU/FRAMING_INST/nx29942z1 (net) 1.470 14 i_SIU/FRAMING_INST/ix29942z40557/B AO1A 3.925 up i_SIU/FRAMING_INST/ix29942z40557/Y AO1A 0.269 4.194 up i_SIU/FRAMING_INST/nx29942z3 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/C AO1C 4.385 up i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/Y AO1C 0.298 4.683 dn i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts1(14)/D DFN1C0 4.874 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.874 ( 28.93% cell delay, 71.07% net delay ) ----------- Slack: 3.716 Critical path #16, (path slack = 3.732): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_stswflag/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_stswflag/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/stswflag (net) 1.572 17 i_SIU/FRAMING_INST/ix45639z40562/C AO1D 1.871 dn i_SIU/FRAMING_INST/ix45639z40562/Y AO1D 0.298 2.169 dn i_SIU/FRAMING_INST/nx45639z5 (net) 0.191 1 i_SIU/FRAMING_INST/ix45639z24339/C NAND3 2.360 dn i_SIU/FRAMING_INST/ix45639z24339/Y NAND3 0.304 2.664 up i_SIU/FRAMING_INST/nx45639z3 (net) 1.225 10 i_SIU/FRAMING_INST/ix45639z40563/C AO1D 3.889 up i_SIU/FRAMING_INST/ix45639z40563/Y AO1D 0.298 4.187 up i_SIU/FRAMING_INST/nx45639z6 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/B NAND2 4.378 up i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/Y NAND2 0.289 4.667 dn i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts2(10)/D DFN1C0 4.858 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.858 ( 30.63% cell delay, 69.37% net delay ) ----------- Slack: 3.732 Critical path #17, (path slack = 3.733): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(4)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(4)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx56256z3 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_ix22081z24344/B NAND2 0.884 dn i_SIU/CMSIU_INST/NOT_ix22081z24344/Y NAND2 0.289 1.173 up i_SIU/CMSIU_INST/nx22081z9 (net) 0.454 3 i_SIU/CMSIU_INST/ix22081z50935/A NAND3A 1.627 up i_SIU/CMSIU_INST/ix22081z50935/Y NAND3A 0.343 1.970 up i_SIU/CMSIU_INST/nx22081z8 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_ix22081z50934/B NAND3C 2.555 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.330 2.885 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.804 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 4.147 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 4.338 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.766 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.957 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.957 ( 40.99% cell delay, 59.01% net delay ) ----------- Slack: 3.733 Critical path #18, (path slack = 3.757): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(1)/CLK DFN1C0 0.000 up i_SIU/reg_q(1)/Q DFN1C0 0.299 0.299 dn i_SIU/nx32078z4 (net) 0.326 2 i_SIU/NOT_ix32078z50931/C NAND3A 0.625 dn i_SIU/NOT_ix32078z50931/Y NAND3A 0.294 0.919 up i_SIU/nx32078z2 (net) 0.454 3 i_SIU/NOT_ix32078z50930/A NAND3A 1.373 up i_SIU/NOT_ix32078z50930/Y NAND3A 0.343 1.716 up i_SIU/nx32078z1 (net) 0.714 5 i_SIU/NOT_a(0)/A NAND3C 2.430 up i_SIU/NOT_a(0)/Y NAND3C 0.227 2.657 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 3.780 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 4.123 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 4.314 up i_SIU/ix17096z21032/Y XA1A 0.428 4.742 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 4.933 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.933 ( 39.21% cell delay, 60.79% net delay ) ----------- Slack: 3.757 Critical path #19, (path slack = 3.897): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(1)/CLK DFN1E1 0.000 up reg_q(1)/Q DFN1E1 0.299 0.299 dn nx53265z3 (net) 0.454 3 ix58250z24342/B NAND2 0.753 dn ix58250z24342/Y NAND2 0.289 1.042 up nx58250z5 (net) 0.326 2 NOT_ix58250z50933/A NAND3A 1.368 up NOT_ix58250z50933/Y NAND3A 0.343 1.711 up nx58250z4 (net) 0.919 7 NOT_ix24075z50934/C NAND3C 2.630 up NOT_ix24075z50934/Y NAND3C 0.342 2.972 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 4.258 up ix23078z24338/Y NAND3 0.304 4.562 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.753 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.753 ( 33.18% cell delay, 66.82% net delay ) ----------- Slack: 3.897 Critical path #20, (path slack = 3.912): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(5)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(5)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z10 (net) 0.454 3 i_SIU/CMSIU_INST/NOT_ix22081z24344/A NAND2 0.753 dn i_SIU/CMSIU_INST/NOT_ix22081z24344/Y NAND2 0.241 0.994 up i_SIU/CMSIU_INST/nx22081z9 (net) 0.454 3 i_SIU/CMSIU_INST/ix22081z50935/A NAND3A 1.448 up i_SIU/CMSIU_INST/ix22081z50935/Y NAND3A 0.343 1.791 up i_SIU/CMSIU_INST/nx22081z8 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_ix22081z50934/B NAND3C 2.376 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.330 2.706 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.625 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.968 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 4.159 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.587 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.778 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.778 ( 41.52% cell delay, 58.48% net delay ) ----------- Slack: 3.912 Critical path #21, (path slack = 3.993): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(6)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(6)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(6) (net) 0.919 7 i_SIU/FRAMING_INST/NOT_ix49627z50935/A NAND3C 1.218 dn i_SIU/FRAMING_INST/NOT_ix49627z50935/Y NAND3C 0.227 1.445 dn i_SIU/FRAMING_INST/nx49627z4 (net) 0.714 5 i_SIU/FRAMING_INST/ix45639z24339/A NAND3 2.159 dn i_SIU/FRAMING_INST/ix45639z24339/Y NAND3 0.244 2.403 up i_SIU/FRAMING_INST/nx45639z3 (net) 1.225 10 i_SIU/FRAMING_INST/ix45639z40563/C AO1D 3.628 up i_SIU/FRAMING_INST/ix45639z40563/Y AO1D 0.298 3.926 up i_SIU/FRAMING_INST/nx45639z6 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/B NAND2 4.117 up i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10)/Y NAND2 0.289 4.406 dn i_SIU/FRAMING_INST/txd_sts2_2n22ss1(10) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts2(10)/D DFN1C0 4.597 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.597 ( 29.52% cell delay, 70.48% net delay ) ----------- Slack: 3.993 Critical path #22, (path slack = 4.010): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(2)/CLK DFN1C0 0.000 up i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(2)/Q DFN1C0 0.299 0.299 dn i_SIU/INST_PMIF/bit_cnt(2) (net) 1.470 14 i_SIU/INST_PMIF/ix51283z49934/B NAND2B 1.769 dn i_SIU/INST_PMIF/ix51283z49934/Y NAND2B 0.298 2.067 dn i_SIU/INST_PMIF/nx51283z1 (net) 0.326 2 i_SIU/INST_PMIF/ix9569z2958/C AND3C 2.393 dn i_SIU/INST_PMIF/ix9569z2958/Y AND3C 0.342 2.735 up i_SIU/INST_PMIF/nx9569z1 (net) 1.470 14 i_SIU/INST_PMIF/ix47302z14896/S MX2 4.205 up i_SIU/INST_PMIF/ix47302z14896/Y MX2 0.184 4.389 dn i_SIU/INST_PMIF/nx47302z1 (net) 0.191 1 i_SIU/INST_PMIF/reg_pm_value(12)/D DFN1C0 4.580 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.580 ( 24.52% cell delay, 75.48% net delay ) ----------- Slack: 4.010 Critical path #23, (path slack = 4.073): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(2)/CLK DFN1E1 0.000 up reg_q(2)/Q DFN1E1 0.299 0.299 dn nx58250z6 (net) 0.326 2 ix58250z24342/A NAND2 0.625 dn ix58250z24342/Y NAND2 0.241 0.866 up nx58250z5 (net) 0.326 2 NOT_ix58250z50933/A NAND3A 1.192 up NOT_ix58250z50933/Y NAND3A 0.343 1.535 up nx58250z4 (net) 0.919 7 NOT_ix24075z50934/C NAND3C 2.454 up NOT_ix24075z50934/Y NAND3C 0.342 2.796 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 4.082 up ix23078z24338/Y NAND3 0.304 4.386 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.577 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.577 ( 33.41% cell delay, 66.59% net delay ) ----------- Slack: 4.073 Critical path #24, (path slack = 4.082): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(16)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(16)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(16) (net) 1.797 28 i_SIU/FRAMING_INST/ix50636z50933/B NAND3C 2.096 dn i_SIU/FRAMING_INST/ix50636z50933/Y NAND3C 0.330 2.426 dn i_SIU/FRAMING_INST/nx50636z2 (net) 1.695 23 i_SIU/FRAMING_INST/txd_dat_2n22ss1(14)/C AOI1D 4.121 dn i_SIU/FRAMING_INST/txd_dat_2n22ss1(14)/Y AOI1D 0.196 4.317 dn i_SIU/FRAMING_INST/txd_dat_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_dat(14)/D DFN1C0 4.508 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.508 ( 18.30% cell delay, 81.70% net delay ) ----------- Slack: 4.082 Critical path #25, (path slack = 4.090): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_sts_present(7)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_sts_present(7)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/sts_present(7) (net) 0.919 7 i_SIU/CMSIU_INST/ix14645z49940/A NAND2B 1.218 dn i_SIU/CMSIU_INST/ix14645z49940/Y NAND2B 0.236 1.454 dn i_SIU/CMSIU_INST/nx14645z7 (net) 1.633 20 i_SIU/CMSIU_INST/ix14645z50935/B NAND3A 3.087 dn i_SIU/CMSIU_INST/ix14645z50935/Y NAND3A 0.244 3.331 up i_SIU/CMSIU_INST/nx14645z6 (net) 0.191 1 i_SIU/CMSIU_INST/ix14645z40561/C AO1C 3.522 up i_SIU/CMSIU_INST/ix14645z40561/Y AO1C 0.298 3.820 dn i_SIU/CMSIU_INST/nx14645z5 (net) 0.191 1 i_SIU/CMSIU_INST/ix14645z40558/C AO1D 4.011 dn i_SIU/CMSIU_INST/ix14645z40558/Y AO1D 0.298 4.309 dn i_SIU/CMSIU_INST/nx14645z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_sts_present(12)/D DFN1C0 4.500 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.500 ( 30.56% cell delay, 69.44% net delay ) ----------- Slack: 4.090 Critical path #26, (path slack = 4.113): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_q(0)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_q(0)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/nx52268z2 (net) 0.585 4 i_SIU/FRAMING_INST/NOT_ix58250z24342/B NAND2 0.884 dn i_SIU/FRAMING_INST/NOT_ix58250z24342/Y NAND2 0.289 1.173 up i_SIU/FRAMING_INST/nx58250z5 (net) 0.326 2 i_SIU/FRAMING_INST/NOT_ix58250z50933/A NAND3A 1.499 up i_SIU/FRAMING_INST/NOT_ix58250z50933/Y NAND3A 0.343 1.842 up i_SIU/FRAMING_INST/nx58250z4 (net) 0.454 3 i_SIU/FRAMING_INST/NOT_ix58250z50932/A NAND3A 2.296 up i_SIU/FRAMING_INST/NOT_ix58250z50932/Y NAND3A 0.343 2.639 up i_SIU/FRAMING_INST/nx58250z3 (net) 0.817 6 i_SIU/FRAMING_INST/NOT_ix59247z50931/A NAND3A 3.456 up i_SIU/FRAMING_INST/NOT_ix59247z50931/Y NAND3A 0.343 3.799 up i_SIU/FRAMING_INST/nx59247z2 (net) 0.191 1 i_SIU/FRAMING_INST/ix59247z21034/B XA1C 3.990 up i_SIU/FRAMING_INST/ix59247z21034/Y XA1C 0.296 4.286 dn i_SIU/FRAMING_INST/nx59247z1 (net) 0.191 1 i_SIU/FRAMING_INST/reg_q(8)/D DFN1C0 4.477 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.477 ( 42.73% cell delay, 57.27% net delay ) ----------- Slack: 4.113 Critical path #27, (path slack = 4.130): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(0)_dup_342/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(0)_dup_342/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx30975z2 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_ix17096z24343/B NAND2 0.884 dn i_SIU/LMSIU_INST/NOT_ix17096z24343/Y NAND2 0.289 1.173 up i_SIU/LMSIU_INST/nx17096z6 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix17096z50934/A NAND3A 1.499 up i_SIU/LMSIU_INST/NOT_ix17096z50934/Y NAND3A 0.343 1.842 up i_SIU/LMSIU_INST/nx17096z5 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix17096z50933/A NAND3A 2.296 up i_SIU/LMSIU_INST/NOT_ix17096z50933/Y NAND3A 0.343 2.639 up i_SIU/LMSIU_INST/nx17096z4 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_ix17096z50932/A NAND3A 3.224 up i_SIU/LMSIU_INST/NOT_ix17096z50932/Y NAND3A 0.343 3.567 up i_SIU/LMSIU_INST/nx17096z3 (net) 0.326 2 i_SIU/LMSIU_INST/ix36096z21034/A XA1C 3.893 up i_SIU/LMSIU_INST/ix36096z21034/Y XA1C 0.376 4.269 dn i_SIU/LMSIU_INST/nx36096z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(8)_dup_334/D DFN1C0 4.460 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.460 ( 44.69% cell delay, 55.31% net delay ) ----------- Slack: 4.130 Critical path #28, (path slack = 4.130): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_sts_present(5)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_sts_present(5)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/sts_present(5) (net) 0.817 6 i_SIU/CMSIU_INST/ix14645z49940/B NAND2B 1.116 dn i_SIU/CMSIU_INST/ix14645z49940/Y NAND2B 0.298 1.414 dn i_SIU/CMSIU_INST/nx14645z7 (net) 1.633 20 i_SIU/CMSIU_INST/ix14645z50935/B NAND3A 3.047 dn i_SIU/CMSIU_INST/ix14645z50935/Y NAND3A 0.244 3.291 up i_SIU/CMSIU_INST/nx14645z6 (net) 0.191 1 i_SIU/CMSIU_INST/ix14645z40561/C AO1C 3.482 up i_SIU/CMSIU_INST/ix14645z40561/Y AO1C 0.298 3.780 dn i_SIU/CMSIU_INST/nx14645z5 (net) 0.191 1 i_SIU/CMSIU_INST/ix14645z40558/C AO1D 3.971 dn i_SIU/CMSIU_INST/ix14645z40558/Y AO1D 0.298 4.269 dn i_SIU/CMSIU_INST/nx14645z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_sts_present(12)/D DFN1C0 4.460 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.460 ( 32.22% cell delay, 67.78% net delay ) ----------- Slack: 4.130 Critical path #29, (path slack = 4.133): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(3)/CLK DFN1C0 0.000 up i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(3)/Q DFN1C0 0.299 0.299 dn i_SIU/INST_PMIF/bit_cnt(3) (net) 1.409 13 i_SIU/INST_PMIF/ix51283z49934/A NAND2B 1.708 dn i_SIU/INST_PMIF/ix51283z49934/Y NAND2B 0.236 1.944 dn i_SIU/INST_PMIF/nx51283z1 (net) 0.326 2 i_SIU/INST_PMIF/ix9569z2958/C AND3C 2.270 dn i_SIU/INST_PMIF/ix9569z2958/Y AND3C 0.342 2.612 up i_SIU/INST_PMIF/nx9569z1 (net) 1.470 14 i_SIU/INST_PMIF/ix47302z14896/S MX2 4.082 up i_SIU/INST_PMIF/ix47302z14896/Y MX2 0.184 4.266 dn i_SIU/INST_PMIF/nx47302z1 (net) 0.191 1 i_SIU/INST_PMIF/reg_pm_value(12)/D DFN1C0 4.457 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.457 ( 23.81% cell delay, 76.19% net delay ) ----------- Slack: 4.133 Critical path #30, (path slack = 4.221): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(2)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(2)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx54262z3 (net) 0.454 3 i_SIU/CMSIU_INST/NOT_ix22081z50933/C NAND3A 0.753 dn i_SIU/CMSIU_INST/NOT_ix22081z50933/Y NAND3A 0.294 1.047 up i_SIU/CMSIU_INST/nx22081z4 (net) 1.123 9 i_SIU/CMSIU_INST/NOT_ix22081z50934/A NAND3C 2.170 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.227 2.397 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.316 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.659 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.850 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.278 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.469 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.469 ( 35.60% cell delay, 64.40% net delay ) ----------- Slack: 4.221 Critical path #31, (path slack = 4.222): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/INST_PMIF/reg_clkdiv_cnt(0)/CLK DFN1P0 0.000 up i_SIU/INST_PMIF/reg_clkdiv_cnt(0)/Q DFN1P0 0.299 0.299 dn i_SIU/INST_PMIF/clkdiv_cnt(0) (net) 0.585 4 i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z24342/B NAND2 0.884 dn i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z24342/Y NAND2 0.289 1.173 up i_SIU/INST_PMIF/modgen_inc_1038/nx62798z4 (net) 0.326 2 i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50933/A NAND3A 1.499 up i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50933/Y NAND3A 0.343 1.842 up i_SIU/INST_PMIF/modgen_inc_1038/nx62798z3 (net) 0.714 5 i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50934/A NAND3C 2.556 up i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50934/Y NAND3C 0.227 2.783 up i_SIU/INST_PMIF/modgen_inc_1038/nx62798z2 (net) 0.454 3 i_SIU/INST_PMIF/modgen_inc_1038/ix62798z8205/B AX1B 3.237 up i_SIU/INST_PMIF/modgen_inc_1038/ix62798z8205/Y AX1B 0.460 3.697 dn i_SIU/INST_PMIF/modgen_inc_1038/d(10) (net) 0.191 1 i_SIU/INST_PMIF/ix40940z1959/B AND2A 3.888 dn i_SIU/INST_PMIF/ix40940z1959/Y AND2A 0.289 4.177 dn i_SIU/INST_PMIF/nx40940z1 (net) 0.191 1 i_SIU/INST_PMIF/reg_clkdiv_cnt(10)/D DFN1C0 4.368 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.368 ( 43.66% cell delay, 56.34% net delay ) ----------- Slack: 4.222 Critical path #32, (path slack = 4.231): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(8)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(8)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx60244z3 (net) 0.454 3 i_SIU/CMSIU_INST/NOT_ix22081z24346/B NAND2 0.753 dn i_SIU/CMSIU_INST/NOT_ix22081z24346/Y NAND2 0.289 1.042 up i_SIU/CMSIU_INST/nx22081z13 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/A NAND3C 1.627 up i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/Y NAND3C 0.227 1.854 up i_SIU/CMSIU_INST/nx22081z12 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_ix22081z50934/C NAND3C 2.045 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.342 2.387 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.306 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.649 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.840 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.268 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.459 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.459 ( 43.24% cell delay, 56.76% net delay ) ----------- Slack: 4.231 Critical path #33, (path slack = 4.236): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(2)_dup_378/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(2)_dup_378/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx52542z3 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix32078z50930/C NAND3A 0.753 dn i_SIU/LMSIU_INST/NOT_ix32078z50930/Y NAND3A 0.294 1.047 up i_SIU/LMSIU_INST/nx32078z1 (net) 0.714 5 i_SIU/LMSIU_INST/NOT_a(0)/A NAND3C 1.761 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.227 1.988 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 3.213 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 3.668 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 3.859 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 4.163 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 4.354 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.354 ( 36.27% cell delay, 63.73% net delay ) ----------- Slack: 4.236 Critical path #34, (path slack = 4.243): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(4)/CLK DFN1E1 0.000 up reg_q(4)/Q DFN1E1 0.299 0.299 dn nx56256z3 (net) 0.585 4 ix57253z24340/B NAND2 0.884 dn ix57253z24340/Y NAND2 0.289 1.173 up nx57253z3 (net) 0.454 3 ix59247z50932/A NAND3A 1.627 up ix59247z50932/Y NAND3A 0.343 1.970 up nx59247z3 (net) 0.326 2 NOT_ix24075z50934/B NAND3C 2.296 up NOT_ix24075z50934/Y NAND3C 0.330 2.626 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.912 up ix23078z24338/Y NAND3 0.304 4.216 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.407 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.407 ( 35.51% cell delay, 64.49% net delay ) ----------- Slack: 4.243 Critical path #35, (path slack = 4.292): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_q(1)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_q(1)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/nx58250z6 (net) 0.454 3 i_SIU/FRAMING_INST/NOT_ix58250z24342/A NAND2 0.753 dn i_SIU/FRAMING_INST/NOT_ix58250z24342/Y NAND2 0.241 0.994 up i_SIU/FRAMING_INST/nx58250z5 (net) 0.326 2 i_SIU/FRAMING_INST/NOT_ix58250z50933/A NAND3A 1.320 up i_SIU/FRAMING_INST/NOT_ix58250z50933/Y NAND3A 0.343 1.663 up i_SIU/FRAMING_INST/nx58250z4 (net) 0.454 3 i_SIU/FRAMING_INST/NOT_ix58250z50932/A NAND3A 2.117 up i_SIU/FRAMING_INST/NOT_ix58250z50932/Y NAND3A 0.343 2.460 up i_SIU/FRAMING_INST/nx58250z3 (net) 0.817 6 i_SIU/FRAMING_INST/NOT_ix59247z50931/A NAND3A 3.277 up i_SIU/FRAMING_INST/NOT_ix59247z50931/Y NAND3A 0.343 3.620 up i_SIU/FRAMING_INST/nx59247z2 (net) 0.191 1 i_SIU/FRAMING_INST/ix59247z21034/B XA1C 3.811 up i_SIU/FRAMING_INST/ix59247z21034/Y XA1C 0.296 4.107 dn i_SIU/FRAMING_INST/nx59247z1 (net) 0.191 1 i_SIU/FRAMING_INST/reg_q(8)/D DFN1C0 4.298 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.298 ( 43.39% cell delay, 56.61% net delay ) ----------- Slack: 4.292 Critical path #36, (path slack = 4.301): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(0)/CLK DFN1 0.000 up reg_q(0)/Q DFN1 0.299 0.299 dn nx52268z3 (net) 0.714 5 NOT_ix58250z50933/C NAND3A 1.013 dn NOT_ix58250z50933/Y NAND3A 0.294 1.307 up nx58250z4 (net) 0.919 7 NOT_ix24075z50934/C NAND3C 2.226 up NOT_ix24075z50934/Y NAND3C 0.342 2.568 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.854 up ix23078z24338/Y NAND3 0.304 4.158 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.349 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.349 ( 28.49% cell delay, 71.51% net delay ) ----------- Slack: 4.301 Critical path #37, (path slack = 4.309): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(1)_dup_341/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(1)_dup_341/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx17096z7 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix17096z24343/A NAND2 0.753 dn i_SIU/LMSIU_INST/NOT_ix17096z24343/Y NAND2 0.241 0.994 up i_SIU/LMSIU_INST/nx17096z6 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix17096z50934/A NAND3A 1.320 up i_SIU/LMSIU_INST/NOT_ix17096z50934/Y NAND3A 0.343 1.663 up i_SIU/LMSIU_INST/nx17096z5 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix17096z50933/A NAND3A 2.117 up i_SIU/LMSIU_INST/NOT_ix17096z50933/Y NAND3A 0.343 2.460 up i_SIU/LMSIU_INST/nx17096z4 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_ix17096z50932/A NAND3A 3.045 up i_SIU/LMSIU_INST/NOT_ix17096z50932/Y NAND3A 0.343 3.388 up i_SIU/LMSIU_INST/nx17096z3 (net) 0.326 2 i_SIU/LMSIU_INST/ix36096z21034/A XA1C 3.714 up i_SIU/LMSIU_INST/ix36096z21034/Y XA1C 0.376 4.090 dn i_SIU/LMSIU_INST/nx36096z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(8)_dup_334/D DFN1C0 4.281 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.281 ( 45.43% cell delay, 54.57% net delay ) ----------- Slack: 4.309 Critical path #38, (path slack = 4.338): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(10)/CLK DFN1E1 0.000 up reg_q(10)/Q DFN1E1 0.299 0.299 dn nx18093z4 (net) 0.714 5 ix18093z24339/C NAND3 1.013 dn ix18093z24339/Y NAND3 0.304 1.317 up nx18093z3 (net) 0.454 3 ix24075z50935/C NAND3C 1.771 up ix24075z50935/Y NAND3C 0.342 2.113 up nx24075z4 (net) 0.191 1 NOT_ix24075z50934/A NAND3C 2.304 up NOT_ix24075z50934/Y NAND3C 0.227 2.531 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.817 up ix23078z24338/Y NAND3 0.304 4.121 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.312 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.312 ( 34.23% cell delay, 65.77% net delay ) ----------- Slack: 4.338 Critical path #39, (path slack = 4.359): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(0)/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(0)/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx52268z2 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix59247z24342/B NAND2 0.753 dn i_SIU/LMSIU_INST/NOT_ix59247z24342/Y NAND2 0.289 1.042 up i_SIU/LMSIU_INST/nx59247z5 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix59247z50933/A NAND3A 1.496 up i_SIU/LMSIU_INST/NOT_ix59247z50933/Y NAND3A 0.343 1.839 up i_SIU/LMSIU_INST/nx59247z4 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix59247z50932/A NAND3A 2.293 up i_SIU/LMSIU_INST/NOT_ix59247z50932/Y NAND3A 0.343 2.636 up i_SIU/LMSIU_INST/nx59247z3 (net) 0.454 3 i_SIU/LMSIU_INST/ix58250z14340/A AX1 3.090 up i_SIU/LMSIU_INST/ix58250z14340/Y AX1 0.455 3.545 dn i_SIU/LMSIU_INST/nx58250z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix58250z2956/C AND3A 3.736 dn i_SIU/LMSIU_INST/ix58250z2956/Y AND3A 0.304 4.040 dn i_SIU/LMSIU_INST/nx58250z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(7)/D DFN1C0 4.231 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.231 ( 48.05% cell delay, 51.95% net delay ) ----------- Slack: 4.359 Critical path #40, (path slack = 4.391): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(10)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(10)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx18093z3 (net) 0.585 4 i_SIU/CMSIU_INST/ix22081z24347/B NAND2 0.884 dn i_SIU/CMSIU_INST/ix22081z24347/Y NAND2 0.289 1.173 up i_SIU/CMSIU_INST/nx22081z15 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/B NAND3C 1.364 up i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/Y NAND3C 0.330 1.694 up i_SIU/CMSIU_INST/nx22081z12 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_ix22081z50934/C NAND3C 1.885 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.342 2.227 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.146 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.489 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.680 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.108 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.299 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.299 ( 47.24% cell delay, 52.76% net delay ) ----------- Slack: 4.391 Critical path #41, (path slack = 4.395): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(4)_dup_376/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(4)_dup_376/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx5574z3 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_ix32078z24340/B NAND2 0.884 dn i_SIU/LMSIU_INST/NOT_ix32078z24340/Y NAND2 0.289 1.173 up i_SIU/LMSIU_INST/nx32078z5 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_a(0)/B NAND3C 1.499 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.330 1.829 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 3.054 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 3.509 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 3.700 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 4.004 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 4.195 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.195 ( 39.98% cell delay, 60.02% net delay ) ----------- Slack: 4.395 Critical path #42, (path slack = 4.397): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCMD_INST/reg_v_scmd_data(0)/CLK DFN1C0 0.000 up i_SIU/RXCMD_INST/reg_v_scmd_data(0)/Q DFN1C0 0.299 0.299 dn i_SIU/RXCMD_INST/v_jcmd_data(0) (net) 0.326 2 i_SIU/RXCMD_INST/ix65343z49937/A NAND2A 0.625 dn i_SIU/RXCMD_INST/ix65343z49937/Y NAND2A 0.298 0.923 dn i_SIU/RXCMD_INST/nx65343z4 (net) 0.817 6 i_SIU/RXCMD_INST/not_ix9603z2959/C AND3C 1.740 dn i_SIU/RXCMD_INST/not_ix9603z2959/Y AND3C 0.342 2.082 up i_SIU/RXCMD_INST/nx9603z2 (net) 1.736 25 i_SIU/RXCMD_INST/ix9603z14896/S MX2 3.818 up i_SIU/RXCMD_INST/ix9603z14896/Y MX2 0.184 4.002 dn i_SIU/RXCMD_INST/nx9603z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_scmd_data(30)/D DFN1C0 4.193 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.193 ( 26.78% cell delay, 73.22% net delay ) ----------- Slack: 4.397 Critical path #43, (path slack = 4.399): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(3)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(3)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z7 (net) 0.326 2 i_SIU/CMSIU_INST/NOT_ix22081z50933/B NAND3A 0.625 dn i_SIU/CMSIU_INST/NOT_ix22081z50933/Y NAND3A 0.244 0.869 up i_SIU/CMSIU_INST/nx22081z4 (net) 1.123 9 i_SIU/CMSIU_INST/NOT_ix22081z50934/A NAND3C 1.992 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.227 2.219 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.138 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.481 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.672 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.100 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.291 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.291 ( 35.91% cell delay, 64.09% net delay ) ----------- Slack: 4.399 Critical path #44, (path slack = 4.401): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/INST_PMIF/reg_clkdiv_cnt(1)/CLK DFN1C0 0.000 up i_SIU/INST_PMIF/reg_clkdiv_cnt(1)/Q DFN1C0 0.299 0.299 dn i_SIU/INST_PMIF/clkdiv_cnt(1) (net) 0.454 3 i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z24342/A NAND2 0.753 dn i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z24342/Y NAND2 0.241 0.994 up i_SIU/INST_PMIF/modgen_inc_1038/nx62798z4 (net) 0.326 2 i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50933/A NAND3A 1.320 up i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50933/Y NAND3A 0.343 1.663 up i_SIU/INST_PMIF/modgen_inc_1038/nx62798z3 (net) 0.714 5 i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50934/A NAND3C 2.377 up i_SIU/INST_PMIF/modgen_inc_1038/NOT_ix62798z50934/Y NAND3C 0.227 2.604 up i_SIU/INST_PMIF/modgen_inc_1038/nx62798z2 (net) 0.454 3 i_SIU/INST_PMIF/modgen_inc_1038/ix62798z8205/B AX1B 3.058 up i_SIU/INST_PMIF/modgen_inc_1038/ix62798z8205/Y AX1B 0.460 3.518 dn i_SIU/INST_PMIF/modgen_inc_1038/d(10) (net) 0.191 1 i_SIU/INST_PMIF/ix40940z1959/B AND2A 3.709 dn i_SIU/INST_PMIF/ix40940z1959/Y AND2A 0.289 3.998 dn i_SIU/INST_PMIF/nx40940z1 (net) 0.191 1 i_SIU/INST_PMIF/reg_clkdiv_cnt(10)/D DFN1C0 4.189 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.189 ( 44.38% cell delay, 55.62% net delay ) ----------- Slack: 4.401 Critical path #45, (path slack = 4.407): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(9)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(9)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z14 (net) 0.326 2 i_SIU/CMSIU_INST/NOT_ix22081z24346/A NAND2 0.625 dn i_SIU/CMSIU_INST/NOT_ix22081z24346/Y NAND2 0.241 0.866 up i_SIU/CMSIU_INST/nx22081z13 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/A NAND3C 1.451 up i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/Y NAND3C 0.227 1.678 up i_SIU/CMSIU_INST/nx22081z12 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_ix22081z50934/C NAND3C 1.869 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.342 2.211 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.130 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.473 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.664 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 4.092 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.283 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.283 ( 43.89% cell delay, 56.11% net delay ) ----------- Slack: 4.407 Critical path #46, (path slack = 4.414): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(3)_dup_377/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(3)_dup_377/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx32078z4 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix32078z50930/B NAND3A 0.625 dn i_SIU/LMSIU_INST/NOT_ix32078z50930/Y NAND3A 0.244 0.869 up i_SIU/LMSIU_INST/nx32078z1 (net) 0.714 5 i_SIU/LMSIU_INST/NOT_a(0)/A NAND3C 1.583 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.227 1.810 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 3.035 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 3.490 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 3.681 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 3.985 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 4.176 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.176 ( 36.61% cell delay, 63.39% net delay ) ----------- Slack: 4.414 Critical path #47, (path slack = 4.422): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(5)/CLK DFN1E1 0.000 up reg_q(5)/Q DFN1E1 0.299 0.299 dn nx58250z8 (net) 0.454 3 ix57253z24340/A NAND2 0.753 dn ix57253z24340/Y NAND2 0.241 0.994 up nx57253z3 (net) 0.454 3 ix59247z50932/A NAND3A 1.448 up ix59247z50932/Y NAND3A 0.343 1.791 up nx59247z3 (net) 0.326 2 NOT_ix24075z50934/B NAND3C 2.117 up NOT_ix24075z50934/Y NAND3C 0.330 2.447 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.733 up ix23078z24338/Y NAND3 0.304 4.037 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.228 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.228 ( 35.88% cell delay, 64.12% net delay ) ----------- Slack: 4.422 Critical path #48, (path slack = 4.422): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_lm_present(3)/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_lm_present(3)/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/lm_present(3) (net) 1.286 11 i_SIU/LMSIU_INST/NOT_ix47518z49937/B NAND2A 1.585 dn i_SIU/LMSIU_INST/NOT_ix47518z49937/Y NAND2A 0.251 1.836 up i_SIU/LMSIU_INST/nx47518z5 (net) 0.919 7 i_SIU/LMSIU_INST/ix47518z40558/C AO1B 2.755 up i_SIU/LMSIU_INST/ix47518z40558/Y AO1B 0.298 3.053 dn i_SIU/LMSIU_INST/nx47518z3 (net) 0.191 1 i_SIU/LMSIU_INST/ix47518z50932/C NAND3B 3.244 dn i_SIU/LMSIU_INST/ix47518z50932/Y NAND3B 0.244 3.488 up i_SIU/LMSIU_INST/nx47518z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix47518z40556/C AO1B 3.679 up i_SIU/LMSIU_INST/ix47518z40556/Y AO1B 0.298 3.977 dn i_SIU/LMSIU_INST/nx47518z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_lm_present(3)/D DFN1C0 4.168 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.168 ( 33.35% cell delay, 66.65% net delay ) ----------- Slack: 4.422 Critical path #49, (path slack = 4.424): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(10)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(10)/Q DFN1C0 0.240 0.240 up i_SIU/FRAMING_INST/tx_present(10) (net) 0.585 4 i_SIU/FRAMING_INST/ix29942z49935/B NAND2B 0.825 up i_SIU/FRAMING_INST/ix29942z49935/Y NAND2B 0.298 1.123 up i_SIU/FRAMING_INST/nx29942z2 (net) 0.326 2 i_SIU/FRAMING_INST/ix29942z40558/C AO1D 1.449 up i_SIU/FRAMING_INST/ix29942z40558/Y AO1D 0.298 1.747 up i_SIU/FRAMING_INST/nx29942z1 (net) 1.470 14 i_SIU/FRAMING_INST/ix29942z40557/B AO1A 3.217 up i_SIU/FRAMING_INST/ix29942z40557/Y AO1A 0.269 3.486 up i_SIU/FRAMING_INST/nx29942z3 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/C AO1C 3.677 up i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/Y AO1C 0.298 3.975 dn i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts1(14)/D DFN1C0 4.166 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.166 ( 33.68% cell delay, 66.32% net delay ) ----------- Slack: 4.424 Critical path #50, (path slack = 4.426): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(2)/CLK DFN1C0 0.000 up i_SIU/reg_q(2)/Q DFN1C0 0.299 0.299 dn i_SIU/nx54262z3 (net) 0.454 3 i_SIU/NOT_ix32078z50930/C NAND3A 0.753 dn i_SIU/NOT_ix32078z50930/Y NAND3A 0.294 1.047 up i_SIU/nx32078z1 (net) 0.714 5 i_SIU/NOT_a(0)/A NAND3C 1.761 up i_SIU/NOT_a(0)/Y NAND3C 0.227 1.988 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 3.111 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 3.454 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 3.645 up i_SIU/ix17096z21032/Y XA1A 0.428 4.073 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 4.264 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.264 ( 37.31% cell delay, 62.69% net delay ) ----------- Slack: 4.426 Critical path #51, (path slack = 4.444): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCMD_INST/reg_rxc_present(6)/CLK DFN1C0 0.000 up i_SIU/RXCMD_INST/reg_rxc_present(6)/Q DFN1C0 0.299 0.299 dn i_SIU/RXCMD_INST/rxc_present(6) (net) 0.326 2 i_SIU/RXCMD_INST/ix65343z49937/B NAND2A 0.625 dn i_SIU/RXCMD_INST/ix65343z49937/Y NAND2A 0.251 0.876 up i_SIU/RXCMD_INST/nx65343z4 (net) 0.817 6 i_SIU/RXCMD_INST/not_ix9603z2959/C AND3C 1.693 up i_SIU/RXCMD_INST/not_ix9603z2959/Y AND3C 0.342 2.035 dn i_SIU/RXCMD_INST/nx9603z2 (net) 1.736 25 i_SIU/RXCMD_INST/ix9603z14896/S MX2 3.771 dn i_SIU/RXCMD_INST/ix9603z14896/Y MX2 0.184 3.955 dn i_SIU/RXCMD_INST/nx9603z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_scmd_data(30)/D DFN1C0 4.146 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.146 ( 25.95% cell delay, 74.05% net delay ) ----------- Slack: 4.444 Critical path #52, (path slack = 4.445): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(8)/CLK DFN1C0 0.000 up i_SIU/reg_q(8)/Q DFN1C0 0.299 0.299 dn i_SIU/nx60244z3 (net) 0.585 4 i_SIU/NOT_ix33075z24338/B NAND2 0.884 dn i_SIU/NOT_ix33075z24338/Y NAND2 0.289 1.173 up i_SIU/nx33075z1 (net) 0.326 2 i_SIU/NOT_a(1)/A NAND3A 1.499 up i_SIU/NOT_a(1)/Y NAND3A 0.343 1.842 up i_SIU/NOT_a(1) (net) 0.454 3 i_SIU/NOT_modgen_and_1171_ix22081z50932/A NAND3A 2.296 up i_SIU/NOT_modgen_and_1171_ix22081z50932/Y NAND3A 0.343 2.639 up i_SIU/nx22081z3 (net) 0.454 3 i_SIU/NOT_ix23078z50933/C NAND3C 3.093 up i_SIU/NOT_ix23078z50933/Y NAND3C 0.342 3.435 up i_SIU/nx23078z2 (net) 0.191 1 i_SIU/ix23078z21032/B XA1A 3.626 up i_SIU/ix23078z21032/Y XA1A 0.428 4.054 up i_SIU/nx23078z1 (net) 0.191 1 i_SIU/reg_q(16)/D DFN1C0 4.245 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.245 ( 48.15% cell delay, 51.85% net delay ) ----------- Slack: 4.445 Critical path #53, (path slack = 4.477): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(8)/CLK DFN1E1 0.000 up reg_q(8)/Q DFN1E1 0.299 0.299 dn nx60244z3 (net) 0.585 4 ix18093z24339/B NAND3 0.884 dn ix18093z24339/Y NAND3 0.294 1.178 up nx18093z3 (net) 0.454 3 ix24075z50935/C NAND3C 1.632 up ix24075z50935/Y NAND3C 0.342 1.974 up nx24075z4 (net) 0.191 1 NOT_ix24075z50934/A NAND3C 2.165 up NOT_ix24075z50934/Y NAND3C 0.227 2.392 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.678 up ix23078z24338/Y NAND3 0.304 3.982 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.173 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.173 ( 35.13% cell delay, 64.87% net delay ) ----------- Slack: 4.477 Critical path #54, (path slack = 4.479): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(11)/CLK DFN1E1 0.000 up reg_q(11)/Q DFN1E1 0.299 0.299 dn nx20087z7 (net) 0.585 4 ix22081z24340/C NAND3 0.884 dn ix22081z24340/Y NAND3 0.304 1.188 up nx22081z4 (net) 0.454 3 ix24075z50935/B NAND3C 1.642 up ix24075z50935/Y NAND3C 0.330 1.972 up nx24075z4 (net) 0.191 1 NOT_ix24075z50934/A NAND3C 2.163 up NOT_ix24075z50934/Y NAND3C 0.227 2.390 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.676 up ix23078z24338/Y NAND3 0.304 3.980 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.171 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.171 ( 35.10% cell delay, 64.90% net delay ) ----------- Slack: 4.479 Critical path #55, (path slack = 4.488): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_lm_present(7)/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_lm_present(7)/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/lm_present(7) (net) 1.123 9 i_SIU/LMSIU_INST/NOT_ix33974z49934/B NAND2A 1.422 dn i_SIU/LMSIU_INST/NOT_ix33974z49934/Y NAND2A 0.251 1.673 up i_SIU/LMSIU_INST/nx33974z3 (net) 1.531 15 i_SIU/LMSIU_INST/ix25072z2960/A AND3A 3.204 up i_SIU/LMSIU_INST/ix25072z2960/Y AND3A 0.227 3.431 dn i_SIU/LMSIU_INST/nx25072z6 (net) 0.191 1 i_SIU/LMSIU_INST/ix25072z1959/B AND2A 3.622 dn i_SIU/LMSIU_INST/ix25072z1959/Y AND2A 0.289 3.911 dn i_SIU/LMSIU_INST/nx25072z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(18)/D DFN1C0 4.102 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.102 ( 25.99% cell delay, 74.01% net delay ) ----------- Slack: 4.488 Critical path #56, (path slack = 4.497): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(3)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(3)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(3) (net) 1.470 14 i_SIU/FRAMING_INST/b_txdiag_2n7ss1/A AO1A 1.769 dn i_SIU/FRAMING_INST/b_txdiag_2n7ss1/Y AO1A 0.223 1.992 up i_SIU/FRAMING_INST/b_txdiag_2n7ss1 (net) 0.817 6 i_SIU/FRAMING_INST/ix52379z50932/A NAND3B 2.809 up i_SIU/FRAMING_INST/ix52379z50932/Y NAND3B 0.342 3.151 up i_SIU/FRAMING_INST/nx52379z2 (net) 0.326 2 i_SIU/FRAMING_INST/ix52379z47388/B AOI1A 3.477 up i_SIU/FRAMING_INST/ix52379z47388/Y AOI1A 0.425 3.902 dn i_SIU/FRAMING_INST/nx52379z1 (net) 0.191 1 i_SIU/FRAMING_INST/reg_tx_present(16)/D DFN1C0 4.093 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.093 ( 31.49% cell delay, 68.51% net delay ) ----------- Slack: 4.497 Critical path #57, (path slack = 4.510): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(12)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(12)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx20087z3 (net) 0.454 3 i_SIU/CMSIU_INST/ix22081z24348/B NAND2 0.753 dn i_SIU/CMSIU_INST/ix22081z24348/Y NAND2 0.289 1.042 up i_SIU/CMSIU_INST/nx22081z17 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/C NAND3C 1.233 up i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/Y NAND3C 0.342 1.575 up i_SIU/CMSIU_INST/nx22081z12 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_ix22081z50934/C NAND3C 1.766 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.342 2.108 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.027 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.370 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.561 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 3.989 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.180 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.180 ( 48.88% cell delay, 51.12% net delay ) ----------- Slack: 4.510 Critical path #58, (path slack = 4.512): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(17)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(17)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(17) (net) 1.470 14 i_SIU/FRAMING_INST/ix50636z50933/A NAND3C 1.769 dn i_SIU/FRAMING_INST/ix50636z50933/Y NAND3C 0.227 1.996 dn i_SIU/FRAMING_INST/nx50636z2 (net) 1.695 23 i_SIU/FRAMING_INST/txd_dat_2n22ss1(14)/C AOI1D 3.691 dn i_SIU/FRAMING_INST/txd_dat_2n22ss1(14)/Y AOI1D 0.196 3.887 dn i_SIU/FRAMING_INST/txd_dat_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_dat(14)/D DFN1C0 4.078 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.078 ( 17.70% cell delay, 82.30% net delay ) ----------- Slack: 4.512 Critical path #59, (path slack = 4.519): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(15)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(15)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/tx_present(15) (net) 1.348 12 i_SIU/FRAMING_INST/ix50636z50933/C NAND3C 1.647 dn i_SIU/FRAMING_INST/ix50636z50933/Y NAND3C 0.342 1.989 dn i_SIU/FRAMING_INST/nx50636z2 (net) 1.695 23 i_SIU/FRAMING_INST/txd_dat_2n22ss1(14)/C AOI1D 3.684 dn i_SIU/FRAMING_INST/txd_dat_2n22ss1(14)/Y AOI1D 0.196 3.880 dn i_SIU/FRAMING_INST/txd_dat_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_dat(14)/D DFN1C0 4.071 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.071 ( 20.56% cell delay, 79.44% net delay ) ----------- Slack: 4.519 Critical path #60, (path slack = 4.525): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(6)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(6)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx58250z3 (net) 0.585 4 i_SIU/CMSIU_INST/ix22081z50935/C NAND3A 0.884 dn i_SIU/CMSIU_INST/ix22081z50935/Y NAND3A 0.294 1.178 up i_SIU/CMSIU_INST/nx22081z8 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_ix22081z50934/B NAND3C 1.763 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.330 2.093 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 3.012 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.355 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.546 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 3.974 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.165 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.165 ( 40.67% cell delay, 59.33% net delay ) ----------- Slack: 4.525 Critical path #61, (path slack = 4.535): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(1)/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(1)/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx59247z6 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix59247z24342/A NAND2 0.625 dn i_SIU/LMSIU_INST/NOT_ix59247z24342/Y NAND2 0.241 0.866 up i_SIU/LMSIU_INST/nx59247z5 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix59247z50933/A NAND3A 1.320 up i_SIU/LMSIU_INST/NOT_ix59247z50933/Y NAND3A 0.343 1.663 up i_SIU/LMSIU_INST/nx59247z4 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix59247z50932/A NAND3A 2.117 up i_SIU/LMSIU_INST/NOT_ix59247z50932/Y NAND3A 0.343 2.460 up i_SIU/LMSIU_INST/nx59247z3 (net) 0.454 3 i_SIU/LMSIU_INST/ix58250z14340/A AX1 2.914 up i_SIU/LMSIU_INST/ix58250z14340/Y AX1 0.455 3.369 dn i_SIU/LMSIU_INST/nx58250z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix58250z2956/C AND3A 3.560 dn i_SIU/LMSIU_INST/ix58250z2956/Y AND3A 0.304 3.864 dn i_SIU/LMSIU_INST/nx58250z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(7)/D DFN1C0 4.055 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.055 ( 48.95% cell delay, 51.05% net delay ) ----------- Slack: 4.535 Critical path #62, (path slack = 4.570): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(11)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(11)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z16 (net) 0.454 3 i_SIU/CMSIU_INST/ix22081z24347/A NAND2 0.753 dn i_SIU/CMSIU_INST/ix22081z24347/Y NAND2 0.241 0.994 up i_SIU/CMSIU_INST/nx22081z15 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/B NAND3C 1.185 up i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/Y NAND3C 0.330 1.515 up i_SIU/CMSIU_INST/nx22081z12 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_ix22081z50934/C NAND3C 1.706 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.342 2.048 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 2.967 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.310 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.501 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 3.929 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.120 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.120 ( 48.13% cell delay, 51.87% net delay ) ----------- Slack: 4.570 Critical path #63, (path slack = 4.574): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(5)_dup_375/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(5)_dup_375/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx32078z6 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix32078z24340/A NAND2 0.753 dn i_SIU/LMSIU_INST/NOT_ix32078z24340/Y NAND2 0.241 0.994 up i_SIU/LMSIU_INST/nx32078z5 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_a(0)/B NAND3C 1.320 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.330 1.650 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 2.875 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 3.330 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 3.521 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 3.825 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 4.016 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.016 ( 40.56% cell delay, 59.44% net delay ) ----------- Slack: 4.574 Critical path #64, (path slack = 4.579): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_frlength(0)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_frlength(0)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/frlength(0) (net) 0.585 4 i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z24340/B NAND2 0.884 dn i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z24340/Y NAND2 0.289 1.173 up i_SIU/FRAMING_INST/frlength_inc8_2i23/nx44952z2 (net) 0.326 2 i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z50931/A NAND3A 1.499 up i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z50931/Y NAND3A 0.343 1.842 up i_SIU/FRAMING_INST/frlength_inc8_2i23/nx44952z1 (net) 0.585 4 i_SIU/FRAMING_INST/frlength_inc8_2i23/ix44952z8205/A AX1B 2.427 up i_SIU/FRAMING_INST/frlength_inc8_2i23/ix44952z8205/Y AX1B 0.455 2.882 dn i_SIU/FRAMING_INST/frlength_inc8_2i23/d(7) (net) 0.191 1 i_SIU/FRAMING_INST/frlength_2n22ss1(7)/B AND2A 3.073 dn i_SIU/FRAMING_INST/frlength_2n22ss1(7)/Y AND2A 0.289 3.362 dn i_SIU/FRAMING_INST/frlength_2n22ss1(7) (net) 0.191 1 i_SIU/FRAMING_INST/ix10419z14896/B MX2 3.553 dn i_SIU/FRAMING_INST/ix10419z14896/Y MX2 0.267 3.820 dn i_SIU/FRAMING_INST/nx10419z1 (net) 0.191 1 i_SIU/FRAMING_INST/reg_frlength(7)/D DFN1C0 4.011 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 4.011 ( 48.42% cell delay, 51.58% net delay ) ----------- Slack: 4.579 Critical path #65, (path slack = 4.585): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(4)/CLK DFN1C0 0.000 up i_SIU/reg_q(4)/Q DFN1C0 0.299 0.299 dn i_SIU/nx56256z3 (net) 0.585 4 i_SIU/NOT_ix32078z24340/B NAND2 0.884 dn i_SIU/NOT_ix32078z24340/Y NAND2 0.289 1.173 up i_SIU/nx32078z6 (net) 0.326 2 i_SIU/NOT_a(0)/B NAND3C 1.499 up i_SIU/NOT_a(0)/Y NAND3C 0.330 1.829 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 2.952 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 3.295 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 3.486 up i_SIU/ix17096z21032/Y XA1A 0.428 3.914 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 4.105 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.105 ( 41.14% cell delay, 58.86% net delay ) ----------- Slack: 4.585 Critical path #66, (path slack = 4.600): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCMD_INST/reg_v_cmd_dest(3)/CLK DFN1C0 0.000 up i_SIU/RXCMD_INST/reg_v_cmd_dest(3)/Q DFN1C0 0.299 0.299 dn i_SIU/RXCMD_INST/v_jcmd_data(3) (net) 0.454 3 i_SIU/RXCMD_INST/ix65343z50938/A NAND3B 0.753 dn i_SIU/RXCMD_INST/ix65343z50938/Y NAND3B 0.342 1.095 dn i_SIU/RXCMD_INST/nx65343z3 (net) 0.454 3 i_SIU/RXCMD_INST/not_ix9603z2959/B AND3C 1.549 dn i_SIU/RXCMD_INST/not_ix9603z2959/Y AND3C 0.330 1.879 up i_SIU/RXCMD_INST/nx9603z2 (net) 1.736 25 i_SIU/RXCMD_INST/ix9603z14896/S MX2 3.615 up i_SIU/RXCMD_INST/ix9603z14896/Y MX2 0.184 3.799 dn i_SIU/RXCMD_INST/nx9603z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_scmd_data(30)/D DFN1C0 3.990 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.990 ( 28.95% cell delay, 71.05% net delay ) ----------- Slack: 4.600 Critical path #67, (path slack = 4.604): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(3)/CLK DFN1C0 0.000 up i_SIU/reg_q(3)/Q DFN1C0 0.299 0.299 dn i_SIU/nx32078z5 (net) 0.326 2 i_SIU/NOT_ix32078z50930/B NAND3A 0.625 dn i_SIU/NOT_ix32078z50930/Y NAND3A 0.244 0.869 up i_SIU/nx32078z1 (net) 0.714 5 i_SIU/NOT_a(0)/A NAND3C 1.583 up i_SIU/NOT_a(0)/Y NAND3C 0.227 1.810 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 2.933 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 3.276 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 3.467 up i_SIU/ix17096z21032/Y XA1A 0.428 3.895 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 4.086 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.086 ( 37.71% cell delay, 62.29% net delay ) ----------- Slack: 4.604 Critical path #68, (path slack = 4.608): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_sts_present(3)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_sts_present(3)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/sts_present(3) (net) 1.817 29 i_SIU/CMSIU_INST/ix15642z49938/B NAND2B 2.116 dn i_SIU/CMSIU_INST/ix15642z49938/Y NAND2B 0.298 2.414 dn i_SIU/CMSIU_INST/nx15642z5 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z40561/B AO1E 2.605 dn i_SIU/CMSIU_INST/ix15642z40561/Y AO1E 0.279 2.884 up i_SIU/CMSIU_INST/nx15642z3 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z40557/C AO1B 3.075 up i_SIU/CMSIU_INST/ix15642z40557/Y AO1B 0.298 3.373 dn i_SIU/CMSIU_INST/nx15642z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z50932/A NAND3C 3.564 dn i_SIU/CMSIU_INST/ix15642z50932/Y NAND3C 0.227 3.791 dn i_SIU/CMSIU_INST/nx15642z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_sts_present(11)/D DFN1C0 3.982 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.982 ( 35.18% cell delay, 64.82% net delay ) ----------- Slack: 4.608 Critical path #69, (path slack = 4.611): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCMD_INST/reg_v_cmd_dest(2)/CLK DFN1C0 0.000 up i_SIU/RXCMD_INST/reg_v_cmd_dest(2)/Q DFN1C0 0.299 0.299 dn i_SIU/RXCMD_INST/v_jcmd_data(2) (net) 0.454 3 i_SIU/RXCMD_INST/ix65343z50938/B NAND3B 0.753 dn i_SIU/RXCMD_INST/ix65343z50938/Y NAND3B 0.331 1.084 dn i_SIU/RXCMD_INST/nx65343z3 (net) 0.454 3 i_SIU/RXCMD_INST/not_ix9603z2959/B AND3C 1.538 dn i_SIU/RXCMD_INST/not_ix9603z2959/Y AND3C 0.330 1.868 up i_SIU/RXCMD_INST/nx9603z2 (net) 1.736 25 i_SIU/RXCMD_INST/ix9603z14896/S MX2 3.604 up i_SIU/RXCMD_INST/ix9603z14896/Y MX2 0.184 3.788 dn i_SIU/RXCMD_INST/nx9603z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_scmd_data(30)/D DFN1C0 3.979 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.979 ( 28.75% cell delay, 71.25% net delay ) ----------- Slack: 4.611 Critical path #70, (path slack = 4.617): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_tx_present(9)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_tx_present(9)/Q DFN1C0 0.240 0.240 up i_SIU/FRAMING_INST/tx_present(9) (net) 0.454 3 i_SIU/FRAMING_INST/ix29942z49935/A NAND2B 0.694 up i_SIU/FRAMING_INST/ix29942z49935/Y NAND2B 0.236 0.930 up i_SIU/FRAMING_INST/nx29942z2 (net) 0.326 2 i_SIU/FRAMING_INST/ix29942z40558/C AO1D 1.256 up i_SIU/FRAMING_INST/ix29942z40558/Y AO1D 0.298 1.554 up i_SIU/FRAMING_INST/nx29942z1 (net) 1.470 14 i_SIU/FRAMING_INST/ix29942z40557/B AO1A 3.024 up i_SIU/FRAMING_INST/ix29942z40557/Y AO1A 0.269 3.293 up i_SIU/FRAMING_INST/nx29942z3 (net) 0.191 1 i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/C AO1C 3.484 up i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14)/Y AO1C 0.298 3.782 dn i_SIU/FRAMING_INST/txd_sts1_2n22ss1(14) (net) 0.191 1 i_SIU/FRAMING_INST/reg_txd_sts1(14)/D DFN1C0 3.973 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.973 ( 33.75% cell delay, 66.25% net delay ) ----------- Slack: 4.617 Critical path #71, (path slack = 4.620): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(12)/CLK DFN1E1 0.000 up reg_q(12)/Q DFN1E1 0.299 0.299 dn nx20087z8 (net) 0.454 3 ix22081z24340/B NAND3 0.753 dn ix22081z24340/Y NAND3 0.294 1.047 up nx22081z4 (net) 0.454 3 ix24075z50935/B NAND3C 1.501 up ix24075z50935/Y NAND3C 0.330 1.831 up nx24075z4 (net) 0.191 1 NOT_ix24075z50934/A NAND3C 2.022 up NOT_ix24075z50934/Y NAND3C 0.227 2.249 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.535 up ix23078z24338/Y NAND3 0.304 3.839 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 4.030 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 4.030 ( 36.08% cell delay, 63.92% net delay ) ----------- Slack: 4.620 Critical path #72, (path slack = 4.624): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(9)/CLK DFN1C0 0.000 up i_SIU/reg_q(9)/Q DFN1C0 0.299 0.299 dn i_SIU/nx33075z2 (net) 0.454 3 i_SIU/NOT_ix33075z24338/A NAND2 0.753 dn i_SIU/NOT_ix33075z24338/Y NAND2 0.241 0.994 up i_SIU/nx33075z1 (net) 0.326 2 i_SIU/NOT_a(1)/A NAND3A 1.320 up i_SIU/NOT_a(1)/Y NAND3A 0.343 1.663 up i_SIU/NOT_a(1) (net) 0.454 3 i_SIU/NOT_modgen_and_1171_ix22081z50932/A NAND3A 2.117 up i_SIU/NOT_modgen_and_1171_ix22081z50932/Y NAND3A 0.343 2.460 up i_SIU/nx22081z3 (net) 0.454 3 i_SIU/NOT_ix23078z50933/C NAND3C 2.914 up i_SIU/NOT_ix23078z50933/Y NAND3C 0.342 3.256 up i_SIU/nx23078z2 (net) 0.191 1 i_SIU/ix23078z21032/B XA1A 3.447 up i_SIU/ix23078z21032/Y XA1A 0.428 3.875 up i_SIU/nx23078z1 (net) 0.191 1 i_SIU/reg_q(16)/D DFN1C0 4.066 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.066 ( 49.09% cell delay, 50.91% net delay ) ----------- Slack: 4.624 Critical path #73, (path slack = 4.627): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXDATA_INST/reg_b_rx_rerr/CLK DFN1C0 0.000 up i_SIU/RXDATA_INST/reg_b_rx_rerr/Q DFN1C0 0.240 0.240 up i_SIU/RXDATA_INST/p_b_rx_rerr (net) 0.326 2 i_SIU/RXDATA_INST/b_ivsof_2n21s1/B NAND2B 0.566 up i_SIU/RXDATA_INST/b_ivsof_2n21s1/Y NAND2B 0.298 0.864 up i_SIU/RXDATA_INST/p_b_ivsof_2n21s1 (net) 0.585 4 i_SIU/RXDATA_INST/ix63900z48516/A AND3 1.449 up i_SIU/RXDATA_INST/ix63900z48516/Y AND3 0.244 1.693 up i_SIU/RXDATA_INST/nx63900z2 (net) 0.919 7 i_SIU/RXCMD_INST/ix62670z40560/A AO1C 2.612 up i_SIU/RXCMD_INST/ix62670z40560/Y AO1C 0.182 2.794 dn i_SIU/RXCMD_INST/nx62670z4 (net) 0.191 1 i_SIU/RXCMD_INST/ix62670z40556/C AO1A 2.985 dn i_SIU/RXCMD_INST/ix62670z40556/Y AO1A 0.298 3.283 dn i_SIU/RXCMD_INST/nx62670z2 (net) 0.191 1 i_SIU/RXCMD_INST/ix62670z5366/C AO1 3.474 dn i_SIU/RXCMD_INST/ix62670z5366/Y AO1 0.298 3.772 dn i_SIU/RXCMD_INST/nx62670z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_rxc_present(7)/D DFN1C0 3.963 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.963 ( 39.36% cell delay, 60.64% net delay ) ----------- Slack: 4.627 Critical path #74, (path slack = 4.627): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_frlength(1)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_frlength(1)/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/frlength(1) (net) 0.585 4 i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z24340/A NAND2 0.884 dn i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z24340/Y NAND2 0.241 1.125 up i_SIU/FRAMING_INST/frlength_inc8_2i23/nx44952z2 (net) 0.326 2 i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z50931/A NAND3A 1.451 up i_SIU/FRAMING_INST/frlength_inc8_2i23/NOT_ix44952z50931/Y NAND3A 0.343 1.794 up i_SIU/FRAMING_INST/frlength_inc8_2i23/nx44952z1 (net) 0.585 4 i_SIU/FRAMING_INST/frlength_inc8_2i23/ix44952z8205/A AX1B 2.379 up i_SIU/FRAMING_INST/frlength_inc8_2i23/ix44952z8205/Y AX1B 0.455 2.834 dn i_SIU/FRAMING_INST/frlength_inc8_2i23/d(7) (net) 0.191 1 i_SIU/FRAMING_INST/frlength_2n22ss1(7)/B AND2A 3.025 dn i_SIU/FRAMING_INST/frlength_2n22ss1(7)/Y AND2A 0.289 3.314 dn i_SIU/FRAMING_INST/frlength_2n22ss1(7) (net) 0.191 1 i_SIU/FRAMING_INST/ix10419z14896/B MX2 3.505 dn i_SIU/FRAMING_INST/ix10419z14896/Y MX2 0.267 3.772 dn i_SIU/FRAMING_INST/nx10419z1 (net) 0.191 1 i_SIU/FRAMING_INST/reg_frlength(7)/D DFN1C0 3.963 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.963 ( 47.79% cell delay, 52.21% net delay ) ----------- Slack: 4.627 Critical path #75, (path slack = 4.647): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCMD_INST/reg_scmd_present(0)/CLK DFN1C0 0.000 up i_SIU/RXCMD_INST/reg_scmd_present(0)/Q DFN1C0 0.299 0.299 dn i_SIU/RXCMD_INST/scmd_present(0) (net) 0.817 6 i_SIU/RXCMD_INST/ix9603z49936/B NAND2B 1.116 dn i_SIU/RXCMD_INST/ix9603z49936/Y NAND2B 0.298 1.414 dn i_SIU/RXCMD_INST/nx9603z3 (net) 0.191 1 i_SIU/RXCMD_INST/not_ix9603z2959/A AND3C 1.605 dn i_SIU/RXCMD_INST/not_ix9603z2959/Y AND3C 0.227 1.832 up i_SIU/RXCMD_INST/nx9603z2 (net) 1.736 25 i_SIU/RXCMD_INST/ix9603z14896/S MX2 3.568 up i_SIU/RXCMD_INST/ix9603z14896/Y MX2 0.184 3.752 dn i_SIU/RXCMD_INST/nx9603z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_scmd_data(30)/D DFN1C0 3.943 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.943 ( 25.56% cell delay, 74.44% net delay ) ----------- Slack: 4.647 Critical path #76, (path slack = 4.649): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(6)_dup_374/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(6)_dup_374/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx24142z3 (net) 0.454 3 i_SIU/LMSIU_INST/ix32078z24341/B NAND2 0.753 dn i_SIU/LMSIU_INST/ix32078z24341/Y NAND2 0.289 1.042 up i_SIU/LMSIU_INST/nx32078z7 (net) 0.191 1 i_SIU/LMSIU_INST/NOT_a(0)/C NAND3C 1.233 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.342 1.575 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 2.800 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 3.255 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 3.446 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 3.750 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 3.941 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.941 ( 42.86% cell delay, 57.14% net delay ) ----------- Slack: 4.649 Critical path #77, (path slack = 4.658): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(9)/CLK DFN1E1 0.000 up reg_q(9)/Q DFN1E1 0.299 0.299 dn nx20087z5 (net) 0.454 3 ix18093z24339/A NAND3 0.753 dn ix18093z24339/Y NAND3 0.244 0.997 up nx18093z3 (net) 0.454 3 ix24075z50935/C NAND3C 1.451 up ix24075z50935/Y NAND3C 0.342 1.793 up nx24075z4 (net) 0.191 1 NOT_ix24075z50934/A NAND3C 1.984 up NOT_ix24075z50934/Y NAND3C 0.227 2.211 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.497 up ix23078z24338/Y NAND3 0.304 3.801 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 3.992 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 3.992 ( 35.47% cell delay, 64.53% net delay ) ----------- Slack: 4.658 Critical path #78, (path slack = 4.664): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCRC_INST/reg_s_crc_srst/CLK DFN1P0 0.000 up i_SIU/RXCRC_INST/reg_s_crc_srst/Q DFN1P0 0.299 0.299 dn i_SIU/RXCRC_INST/s_crc_srst (net) 1.899 33 i_SIU/RXCRC_INST/RXCRC_inst/ix11923z49940/A NAND2B 2.198 dn i_SIU/RXCRC_INST/RXCRC_inst/ix11923z49940/Y NAND2B 0.236 2.434 dn i_SIU/RXCRC_INST/RXCRC_inst/nx11923z6 (net) 1.552 16 i_SIU/RXCRC_INST/RXCRC_inst/reg_q0(15)/E DFN1E1 3.986 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 3.986 ( 13.42% cell delay, 86.58% net delay ) ----------- Slack: 4.664 Critical path #79, (path slack = 4.664): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_s_crc_sld/CLK DFN1P0 0.000 up i_SIU/FRAMING_INST/reg_s_crc_sld/Q DFN1P0 0.299 0.299 dn i_SIU/FRAMING_INST/s_crc_sld (net) 1.899 33 i_SIU/FRAMING_INST/CRC_INST/ix11923z49940/A NAND2B 2.198 dn i_SIU/FRAMING_INST/CRC_INST/ix11923z49940/Y NAND2B 0.236 2.434 dn i_SIU/FRAMING_INST/CRC_INST/nx11923z6 (net) 1.552 16 i_SIU/FRAMING_INST/CRC_INST/reg_q0(15)/E DFN1E1 3.986 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 3.986 ( 13.42% cell delay, 86.58% net delay ) ----------- Slack: 4.664 Critical path #80, (path slack = 4.673): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst/RCLK FIFO4K18 0.000 up i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst/EMPTY FIFO4K18 1.504 1.504 up i_SIU/TXDF_INST_TXDF_CORE_INST_EMPTY_0 (net) 0.326 2 i_SIU/TXDF_INST_txdf_e_i/B NAND2B 1.830 up i_SIU/TXDF_INST_txdf_e_i/Y NAND2B 0.298 2.128 up i_SIU/TXDF_INST_txdf_e_i (net) 0.326 2 i_SIU/ix14207z40557/B AO1B 2.454 up i_SIU/ix14207z40557/Y AO1B 0.273 2.727 up i_SIU/nx14207z2 (net) 0.326 2 i_SIU/NOT_TXDF_INST_ix44315z40560/C AO1E 3.053 up i_SIU/NOT_TXDF_INST_ix44315z40560/Y AO1E 0.298 3.351 dn i_SIU/nx44315z2 (net) 0.191 1 i_SIU/ix44315z14896/S MX2 3.542 dn i_SIU/ix44315z14896/Y MX2 0.184 3.726 dn i_SIU/nx44315z1 (net) 0.191 1 i_SIU/TXDF_INST_reg_txdf_empty/D DFN1P0 3.917 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.917 ( 65.28% cell delay, 34.72% net delay ) ----------- Slack: 4.673 Critical path #81, (path slack = 4.683): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(8)_dup_372/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(8)_dup_372/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx42710z3 (net) 0.454 3 i_SIU/LMSIU_INST/NOT_ix33075z24338/B NAND2 0.753 dn i_SIU/LMSIU_INST/NOT_ix33075z24338/Y NAND2 0.289 1.042 up i_SIU/LMSIU_INST/nx33075z1 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_a(1)/A NAND3A 1.627 up i_SIU/LMSIU_INST/NOT_a(1)/Y NAND3A 0.343 1.970 up i_SIU/LMSIU_INST/NOT_a(1) (net) 0.714 5 i_SIU/LMSIU_INST/NOT_ix25072z50933/B NAND3C 2.684 up i_SIU/LMSIU_INST/NOT_ix25072z50933/Y NAND3C 0.330 3.014 up i_SIU/LMSIU_INST/nx25072z2 (net) 0.326 2 i_SIU/LMSIU_INST/ix23078z21034/A XA1C 3.340 up i_SIU/LMSIU_INST/ix23078z21034/Y XA1C 0.376 3.716 dn i_SIU/LMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(16)/D DFN1C0 3.907 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.907 ( 41.90% cell delay, 58.10% net delay ) ----------- Slack: 4.683 Critical path #82, (path slack = 4.686): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(13)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(13)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z18 (net) 0.326 2 i_SIU/CMSIU_INST/ix22081z24348/A NAND2 0.625 dn i_SIU/CMSIU_INST/ix22081z24348/Y NAND2 0.241 0.866 up i_SIU/CMSIU_INST/nx22081z17 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/C NAND3C 1.057 up i_SIU/CMSIU_INST/NOT_modgen_and_1070_ix22081z50939/Y NAND3C 0.342 1.399 up i_SIU/CMSIU_INST/nx22081z12 (net) 0.191 1 i_SIU/CMSIU_INST/NOT_ix22081z50934/C NAND3C 1.590 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.342 1.932 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 2.851 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.194 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.385 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 3.813 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 4.004 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 4.004 ( 49.83% cell delay, 50.17% net delay ) ----------- Slack: 4.686 Critical path #83, (path slack = 4.692): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_sts_present(6)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_sts_present(6)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/sts_present(6) (net) 1.695 23 i_SIU/CMSIU_INST/ix15642z49937/B NAND2B 1.994 dn i_SIU/CMSIU_INST/ix15642z49937/Y NAND2B 0.298 2.292 dn i_SIU/CMSIU_INST/nx15642z4 (net) 0.326 2 i_SIU/CMSIU_INST/ix15642z40561/A AO1E 2.618 dn i_SIU/CMSIU_INST/ix15642z40561/Y AO1E 0.182 2.800 up i_SIU/CMSIU_INST/nx15642z3 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z40557/C AO1B 2.991 up i_SIU/CMSIU_INST/ix15642z40557/Y AO1B 0.298 3.289 dn i_SIU/CMSIU_INST/nx15642z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z50932/A NAND3C 3.480 dn i_SIU/CMSIU_INST/ix15642z50932/Y NAND3C 0.227 3.707 dn i_SIU/CMSIU_INST/nx15642z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_sts_present(11)/D DFN1C0 3.898 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.898 ( 33.45% cell delay, 66.55% net delay ) ----------- Slack: 4.692 Critical path #84, (path slack = 4.698): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXCMD_INST/reg_v_cmd_dest(1)/CLK DFN1C0 0.000 up i_SIU/RXCMD_INST/reg_v_cmd_dest(1)/Q DFN1C0 0.299 0.299 dn i_SIU/RXCMD_INST/v_jcmd_data(1) (net) 0.454 3 i_SIU/RXCMD_INST/ix65343z50938/C NAND3B 0.753 dn i_SIU/RXCMD_INST/ix65343z50938/Y NAND3B 0.244 0.997 up i_SIU/RXCMD_INST/nx65343z3 (net) 0.454 3 i_SIU/RXCMD_INST/not_ix9603z2959/B AND3C 1.451 up i_SIU/RXCMD_INST/not_ix9603z2959/Y AND3C 0.330 1.781 dn i_SIU/RXCMD_INST/nx9603z2 (net) 1.736 25 i_SIU/RXCMD_INST/ix9603z14896/S MX2 3.517 dn i_SIU/RXCMD_INST/ix9603z14896/Y MX2 0.184 3.701 dn i_SIU/RXCMD_INST/nx9603z1 (net) 0.191 1 i_SIU/RXCMD_INST/reg_scmd_data(30)/D DFN1C0 3.892 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.892 ( 27.16% cell delay, 72.84% net delay ) ----------- Slack: 4.698 Critical path #85, (path slack = 4.704): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(18)/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(18)/Q DFN1C0 0.240 0.240 up i_SIU/LMSIU_INST/poff_timer(18) (net) 0.919 7 i_SIU/LMSIU_INST/NOT_ix33974z49934/A NAND2A 1.159 up i_SIU/LMSIU_INST/NOT_ix33974z49934/Y NAND2A 0.298 1.457 up i_SIU/LMSIU_INST/nx33974z3 (net) 1.531 15 i_SIU/LMSIU_INST/ix25072z2960/A AND3A 2.988 up i_SIU/LMSIU_INST/ix25072z2960/Y AND3A 0.227 3.215 dn i_SIU/LMSIU_INST/nx25072z6 (net) 0.191 1 i_SIU/LMSIU_INST/ix25072z1959/B AND2A 3.406 dn i_SIU/LMSIU_INST/ix25072z1959/Y AND2A 0.289 3.695 dn i_SIU/LMSIU_INST/nx25072z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(18)/D DFN1C0 3.886 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.886 ( 27.12% cell delay, 72.88% net delay ) ----------- Slack: 4.704 Critical path #86, (path slack = 4.706): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_q(7)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_q(7)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/nx22081z11 (net) 0.454 3 i_SIU/CMSIU_INST/ix22081z50935/B NAND3A 0.753 dn i_SIU/CMSIU_INST/ix22081z50935/Y NAND3A 0.244 0.997 up i_SIU/CMSIU_INST/nx22081z8 (net) 0.585 4 i_SIU/CMSIU_INST/NOT_ix22081z50934/B NAND3C 1.582 up i_SIU/CMSIU_INST/NOT_ix22081z50934/Y NAND3C 0.330 1.912 up i_SIU/CMSIU_INST/nx22081z3 (net) 0.919 7 i_SIU/CMSIU_INST/NOT_ix23078z50931/A NAND3A 2.831 up i_SIU/CMSIU_INST/NOT_ix23078z50931/Y NAND3A 0.343 3.174 up i_SIU/CMSIU_INST/nx23078z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix23078z21032/B XA1A 3.365 up i_SIU/CMSIU_INST/ix23078z21032/Y XA1A 0.428 3.793 up i_SIU/CMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_q(16)/D DFN1C0 3.984 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 3.984 ( 41.27% cell delay, 58.73% net delay ) ----------- Slack: 4.706 Critical path #87, (path slack = 4.707): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1)/CLK DFN1C0 0.000 up i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1)/Q DFN1C0 0.299 0.299 dn i_SIU/INST_PMIF/bit_cnt(1) (net) 1.409 13 i_SIU/INST_PMIF/ix9569z2958/B AND3C 1.708 dn i_SIU/INST_PMIF/ix9569z2958/Y AND3C 0.330 2.038 up i_SIU/INST_PMIF/nx9569z1 (net) 1.470 14 i_SIU/INST_PMIF/ix47302z14896/S MX2 3.508 up i_SIU/INST_PMIF/ix47302z14896/Y MX2 0.184 3.692 dn i_SIU/INST_PMIF/nx47302z1 (net) 0.191 1 i_SIU/INST_PMIF/reg_pm_value(12)/D DFN1C0 3.883 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.883 ( 20.94% cell delay, 79.06% net delay ) ----------- Slack: 4.707 Critical path #88, (path slack = 4.735): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst/RCLK FIFO4K18 0.000 up i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst/EMPTY FIFO4K18 1.504 1.504 up i_SIU/TXDF_INST_TXDF_CORE_INST_EMPTY_1 (net) 0.326 2 i_SIU/TXDF_INST_txdf_e_i/A NAND2B 1.830 up i_SIU/TXDF_INST_txdf_e_i/Y NAND2B 0.236 2.066 up i_SIU/TXDF_INST_txdf_e_i (net) 0.326 2 i_SIU/ix14207z40557/B AO1B 2.392 up i_SIU/ix14207z40557/Y AO1B 0.273 2.665 up i_SIU/nx14207z2 (net) 0.326 2 i_SIU/NOT_TXDF_INST_ix44315z40560/C AO1E 2.991 up i_SIU/NOT_TXDF_INST_ix44315z40560/Y AO1E 0.298 3.289 dn i_SIU/nx44315z2 (net) 0.191 1 i_SIU/ix44315z14896/S MX2 3.480 dn i_SIU/ix44315z14896/Y MX2 0.184 3.664 dn i_SIU/nx44315z1 (net) 0.191 1 i_SIU/TXDF_INST_reg_txdf_empty/D DFN1P0 3.855 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.855 ( 64.72% cell delay, 35.28% net delay ) ----------- Slack: 4.735 Critical path #89, (path slack = 4.739): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(3)/CLK DFN1E1 0.000 up reg_q(3)/Q DFN1E1 0.299 0.299 dn nx58250z7 (net) 0.326 2 NOT_ix58250z50933/B NAND3A 0.625 dn NOT_ix58250z50933/Y NAND3A 0.244 0.869 up nx58250z4 (net) 0.919 7 NOT_ix24075z50934/C NAND3C 1.788 up NOT_ix24075z50934/Y NAND3C 0.342 2.130 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.416 up ix23078z24338/Y NAND3 0.304 3.720 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 3.911 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 3.911 ( 30.40% cell delay, 69.60% net delay ) ----------- Slack: 4.739 Critical path #90, (path slack = 4.764): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(5)/CLK DFN1C0 0.000 up i_SIU/reg_q(5)/Q DFN1C0 0.299 0.299 dn i_SIU/nx32078z7 (net) 0.454 3 i_SIU/NOT_ix32078z24340/A NAND2 0.753 dn i_SIU/NOT_ix32078z24340/Y NAND2 0.241 0.994 up i_SIU/nx32078z6 (net) 0.326 2 i_SIU/NOT_a(0)/B NAND3C 1.320 up i_SIU/NOT_a(0)/Y NAND3C 0.330 1.650 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 2.773 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 3.116 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 3.307 up i_SIU/ix17096z21032/Y XA1A 0.428 3.735 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 3.926 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 3.926 ( 41.80% cell delay, 58.20% net delay ) ----------- Slack: 4.764 Critical path #91, (path slack = 4.764): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXDATA_INST/reg_q(0)/CLK DFN1C0 0.000 up i_SIU/RXDATA_INST/reg_q(0)/Q DFN1C0 0.299 0.299 dn i_SIU/RXDATA_INST/nx59247z6 (net) 0.454 3 i_SIU/RXDATA_INST/NOT_ix52268z24340/B NAND2 0.753 dn i_SIU/RXDATA_INST/NOT_ix52268z24340/Y NAND2 0.289 1.042 up i_SIU/RXDATA_INST/nx52268z3 (net) 0.326 2 i_SIU/RXDATA_INST/NOT_ix54262z50932/A NAND3A 1.368 up i_SIU/RXDATA_INST/NOT_ix54262z50932/Y NAND3A 0.343 1.711 up i_SIU/RXDATA_INST/nx54262z3 (net) 0.454 3 i_SIU/RXDATA_INST/NOT_ix57253z50933/B NAND3B 2.165 up i_SIU/RXDATA_INST/NOT_ix57253z50933/Y NAND3B 0.331 2.496 up i_SIU/RXDATA_INST/nx57253z3 (net) 0.191 1 i_SIU/RXDATA_INST/ix57253z64468/B AOI1 2.687 up i_SIU/RXDATA_INST/ix57253z64468/Y AOI1 0.425 3.112 dn i_SIU/RXDATA_INST/nx57253z2 (net) 0.191 1 i_SIU/RXDATA_INST/ix57253z4191/B AXOI5 3.303 dn i_SIU/RXDATA_INST/ix57253z4191/Y AXOI5 0.432 3.735 up i_SIU/RXDATA_INST/nx57253z1 (net) 0.191 1 i_SIU/RXDATA_INST/reg_q(6)/D DFN1C0 3.926 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 3.926 ( 53.97% cell delay, 46.03% net delay ) ----------- Slack: 4.764 Critical path #92, (path slack = 4.798): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT reg_q(13)/CLK DFN1E1 0.000 up reg_q(13)/Q DFN1E1 0.299 0.299 dn nx22081z5 (net) 0.326 2 ix22081z24340/A NAND3 0.625 dn ix22081z24340/Y NAND3 0.244 0.869 up nx22081z4 (net) 0.454 3 ix24075z50935/B NAND3C 1.323 up ix24075z50935/Y NAND3C 0.330 1.653 up nx24075z4 (net) 0.191 1 NOT_ix24075z50934/A NAND3C 1.844 up NOT_ix24075z50934/Y NAND3C 0.227 2.071 up nx24075z3 (net) 1.286 11 ix23078z24338/C NAND3 3.357 up ix23078z24338/Y NAND3 0.304 3.661 dn nx23078z2 (net) 0.191 1 reg_q(16)/E DFN1E1 3.852 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.350 ----------- Data required time: 8.650 Data arrival time: - 3.852 ( 36.45% cell delay, 63.55% net delay ) ----------- Slack: 4.798 Critical path #93, (path slack = 4.810): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(0)/CLK DFN1C0 0.000 up i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(0)/Q DFN1C0 0.299 0.299 dn i_SIU/INST_PMIF/bit_cnt(0) (net) 1.409 13 i_SIU/INST_PMIF/ix9569z2958/A AND3C 1.708 dn i_SIU/INST_PMIF/ix9569z2958/Y AND3C 0.227 1.935 up i_SIU/INST_PMIF/nx9569z1 (net) 1.470 14 i_SIU/INST_PMIF/ix47302z14896/S MX2 3.405 up i_SIU/INST_PMIF/ix47302z14896/Y MX2 0.184 3.589 dn i_SIU/INST_PMIF/nx47302z1 (net) 0.191 1 i_SIU/INST_PMIF/reg_pm_value(12)/D DFN1C0 3.780 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.780 ( 18.78% cell delay, 81.22% net delay ) ----------- Slack: 4.810 Critical path #94, (path slack = 4.816): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/CMSIU_INST/reg_sts_present(8)/CLK DFN1C0 0.000 up i_SIU/CMSIU_INST/reg_sts_present(8)/Q DFN1C0 0.299 0.299 dn i_SIU/CMSIU_INST/sts_present(8) (net) 1.633 20 i_SIU/CMSIU_INST/ix15642z49937/A NAND2B 1.932 dn i_SIU/CMSIU_INST/ix15642z49937/Y NAND2B 0.236 2.168 dn i_SIU/CMSIU_INST/nx15642z4 (net) 0.326 2 i_SIU/CMSIU_INST/ix15642z40561/A AO1E 2.494 dn i_SIU/CMSIU_INST/ix15642z40561/Y AO1E 0.182 2.676 up i_SIU/CMSIU_INST/nx15642z3 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z40557/C AO1B 2.867 up i_SIU/CMSIU_INST/ix15642z40557/Y AO1B 0.298 3.165 dn i_SIU/CMSIU_INST/nx15642z2 (net) 0.191 1 i_SIU/CMSIU_INST/ix15642z50932/A NAND3C 3.356 dn i_SIU/CMSIU_INST/ix15642z50932/Y NAND3C 0.227 3.583 dn i_SIU/CMSIU_INST/nx15642z1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_sts_present(11)/D DFN1C0 3.774 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.774 ( 32.91% cell delay, 67.09% net delay ) ----------- Slack: 4.816 Critical path #95, (path slack = 4.825): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(7)_dup_373/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(7)_dup_373/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx32078z8 (net) 0.326 2 i_SIU/LMSIU_INST/ix32078z24341/A NAND2 0.625 dn i_SIU/LMSIU_INST/ix32078z24341/Y NAND2 0.241 0.866 up i_SIU/LMSIU_INST/nx32078z7 (net) 0.191 1 i_SIU/LMSIU_INST/NOT_a(0)/C NAND3C 1.057 up i_SIU/LMSIU_INST/NOT_a(0)/Y NAND3C 0.342 1.399 up i_SIU/LMSIU_INST/NOT_a(0) (net) 1.225 10 i_SIU/LMSIU_INST/ix19090z8206/A AX1B 2.624 up i_SIU/LMSIU_INST/ix19090z8206/Y AX1B 0.455 3.079 dn i_SIU/LMSIU_INST/nx19090z2 (net) 0.191 1 i_SIU/LMSIU_INST/ix19090z2956/C AND3A 3.270 dn i_SIU/LMSIU_INST/ix19090z2956/Y AND3A 0.304 3.574 dn i_SIU/LMSIU_INST/nx19090z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(12)/D DFN1C0 3.765 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.765 ( 43.59% cell delay, 56.41% net delay ) ----------- Slack: 4.825 Critical path #96, (path slack = 4.839): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/reg_q(6)/CLK DFN1C0 0.000 up i_SIU/reg_q(6)/Q DFN1C0 0.299 0.299 dn i_SIU/nx58250z3 (net) 0.454 3 i_SIU/ix32078z24341/B NAND2 0.753 dn i_SIU/ix32078z24341/Y NAND2 0.289 1.042 up i_SIU/nx32078z8 (net) 0.191 1 i_SIU/NOT_a(0)/C NAND3C 1.233 up i_SIU/NOT_a(0)/Y NAND3C 0.342 1.575 up i_SIU/NOT_a(0) (net) 1.123 9 i_SIU/NOT_ix17096z50931/A NAND3A 2.698 up i_SIU/NOT_ix17096z50931/Y NAND3A 0.343 3.041 up i_SIU/nx17096z2 (net) 0.191 1 i_SIU/ix17096z21032/B XA1A 3.232 up i_SIU/ix17096z21032/Y XA1A 0.428 3.660 up i_SIU/nx17096z1 (net) 0.191 1 i_SIU/reg_q(10)/D DFN1C0 3.851 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 3.851 ( 44.17% cell delay, 55.83% net delay ) ----------- Slack: 4.839 Critical path #97, (path slack = 4.843): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_txst_ack/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_txst_ack/Q DFN1C0 0.299 0.299 dn i_SIU/FRAMING_INST/txst_ack (net) 1.348 12 i_SIU/CMSIU_INST/NOT_ix12651z24339/A NAND2 1.647 dn i_SIU/CMSIU_INST/NOT_ix12651z24339/Y NAND2 0.241 1.888 up i_SIU/CMSIU_INST/nx12651z2 (net) 0.326 2 i_SIU/CMSIU_INST/NOT_ix8141z47394/C AOI1C 2.214 up i_SIU/CMSIU_INST/NOT_ix8141z47394/Y AOI1C 0.247 2.461 dn i_SIU/CMSIU_INST/nx8141z4 (net) 0.191 1 i_SIU/CMSIU_INST/ix8141z14899/S MX2 2.652 dn i_SIU/CMSIU_INST/ix8141z14899/Y MX2 0.223 2.875 up i_SIU/CMSIU_INST/NOT_b_jtag_open_2n3ss1 (net) 0.454 3 i_SIU/CMSIU_INST/b_stjwr_2n48ss1/A AND3C 3.329 up i_SIU/CMSIU_INST/b_stjwr_2n48ss1/Y AND3C 0.227 3.556 dn i_SIU/CMSIU_INST/b_stjwr_2n48ss1 (net) 0.191 1 i_SIU/CMSIU_INST/reg_b_stjwr/D DFN1C0 3.747 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.747 ( 33.01% cell delay, 66.99% net delay ) ----------- Slack: 4.843 Critical path #98, (path slack = 4.853): SOURCE CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_RXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/RXDATA_INST/reg_q(1)/CLK DFN1C0 0.000 up i_SIU/RXDATA_INST/reg_q(1)/Q DFN1C0 0.299 0.299 dn i_SIU/RXDATA_INST/nx59247z7 (net) 0.454 3 i_SIU/RXDATA_INST/NOT_ix59247z24341/C NAND3 0.753 dn i_SIU/RXDATA_INST/NOT_ix59247z24341/Y NAND3 0.304 1.057 up i_SIU/RXDATA_INST/nx59247z5 (net) 0.454 3 i_SIU/RXDATA_INST/NOT_ix59247z50933/A NAND3A 1.511 up i_SIU/RXDATA_INST/NOT_ix59247z50933/Y NAND3A 0.343 1.854 up i_SIU/RXDATA_INST/nx59247z4 (net) 0.326 2 i_SIU/RXDATA_INST/NOT_ix59247z50934/A NAND3C 2.180 up i_SIU/RXDATA_INST/NOT_ix59247z50934/Y NAND3C 0.227 2.407 up i_SIU/RXDATA_INST/nx59247z3 (net) 0.191 1 i_SIU/RXDATA_INST/ix59247z64468/B AOI1 2.598 up i_SIU/RXDATA_INST/ix59247z64468/Y AOI1 0.425 3.023 dn i_SIU/RXDATA_INST/nx59247z2 (net) 0.191 1 i_SIU/RXDATA_INST/ix59247z4191/B AXOI5 3.214 dn i_SIU/RXDATA_INST/ix59247z4191/Y AXOI5 0.432 3.646 up i_SIU/RXDATA_INST/nx59247z1 (net) 0.191 1 i_SIU/RXDATA_INST/reg_q(8)/D DFN1C0 3.837 up Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.310 ----------- Data required time: 8.690 Data arrival time: - 3.837 ( 52.91% cell delay, 47.09% net delay ) ----------- Slack: 4.853 Critical path #99, (path slack = 4.859): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/LMSIU_INST/reg_q(9)_dup_371/CLK DFN1C0 0.000 up i_SIU/LMSIU_INST/reg_q(9)_dup_371/Q DFN1C0 0.299 0.299 dn i_SIU/LMSIU_INST/nx33075z2 (net) 0.326 2 i_SIU/LMSIU_INST/NOT_ix33075z24338/A NAND2 0.625 dn i_SIU/LMSIU_INST/NOT_ix33075z24338/Y NAND2 0.241 0.866 up i_SIU/LMSIU_INST/nx33075z1 (net) 0.585 4 i_SIU/LMSIU_INST/NOT_a(1)/A NAND3A 1.451 up i_SIU/LMSIU_INST/NOT_a(1)/Y NAND3A 0.343 1.794 up i_SIU/LMSIU_INST/NOT_a(1) (net) 0.714 5 i_SIU/LMSIU_INST/NOT_ix25072z50933/B NAND3C 2.508 up i_SIU/LMSIU_INST/NOT_ix25072z50933/Y NAND3C 0.330 2.838 up i_SIU/LMSIU_INST/nx25072z2 (net) 0.326 2 i_SIU/LMSIU_INST/ix23078z21034/A XA1C 3.164 up i_SIU/LMSIU_INST/ix23078z21034/Y XA1C 0.376 3.540 dn i_SIU/LMSIU_INST/nx23078z1 (net) 0.191 1 i_SIU/LMSIU_INST/reg_q(16)/D DFN1C0 3.731 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.731 ( 42.59% cell delay, 57.41% net delay ) ----------- Slack: 4.859 Critical path #100, (path slack = 4.886): SOURCE CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 1st rising edge DEST CLOCK: name: SIU_TXCLK period: 9.000000 Times are relative to the 2nd rising edge NAME GATE DELAY ARRIVAL DIR FANOUT i_SIU/FRAMING_INST/reg_q(11)/CLK DFN1C0 0.000 up i_SIU/FRAMING_INST/reg_q(11)/Q DFN1C0 0.240 0.240 up i_SIU/FRAMING_INST/wd_timer(11) (net) 1.613 19 i_SIU/FRAMING_INST/NOT_ix44644z50933/A NAND3B 1.853 up i_SIU/FRAMING_INST/NOT_ix44644z50933/Y NAND3B 0.342 2.195 up i_SIU/FRAMING_INST/nx44644z3 (net) 0.454 3 i_SIU/FRAMING_INST/ix53376z50933/C NAND3C 2.649 up i_SIU/FRAMING_INST/ix53376z50933/Y NAND3C 0.342 2.991 up i_SIU/FRAMING_INST/nx53376z2 (net) 0.191 1 i_SIU/FRAMING_INST/ix53376z2957/B AND3B 3.182 up i_SIU/FRAMING_INST/ix53376z2957/Y AND3B 0.331 3.513 dn i_SIU/FRAMING_INST/nx53376z1 (net) 0.191 1 i_SIU/FRAMING_INST/reg_tx_present(15)/D DFN1C0 3.704 dn Initial edge separation: 9.000 Source clock delay: - 2.949 Dest clock delay: + 2.949 ----------- Edge separation: 9.000 Setup constraint: - 0.410 ----------- Data required time: 8.590 Data arrival time: - 3.704 ( 33.88% cell delay, 66.12% net delay ) ----------- Slack: 4.886 End CTE Analysis ..... CPU Time Used: 5 sec. -- POST-SYNTHESIS TIMING REPORTS ARE ESTIMATES AND SHOULD NOT BE RELIED ON TO MAKE QoR DECISIONS. For accurate timing information, please run place-and-route (P&R) and review P&R generated timing reports. ================================================================================================ Clock Frequency Report Domain Clock Name Min Period (Freq) Required Period (Freq) ------ ---------- ----------------- ---------------------- ADC1MHZ i_adc/cdiv/reg_q/out 7.950 (125.786 MHz) 100.000 (10.000 MHz) LHC40MHZ i_cbb/clock_generation_ipll_Core/GLA 16.982 (58.886 MHz) 25.000 (40.000 MHz) LHC40MHZ i_cbb/clock_generation_ipll_Core/GLB 6.471 (154.536 MHz) 25.000 (40.000 MHz) LHC40MHZ i_cbb/clock_generation_ipll_Core/GLC 3.412 (293.083 MHz) 12.500 (80.000 MHz) LHC40MHZ lvds_clk40in_U1/Y 16.982 (58.886 MHz) 25.000 (40.000 MHz) TLK_RX SIU_RXCLK 6.089 (164.231 MHz) 9.000 (111.111 MHz) TLK_TX SIU_TXCLK 6.707 (149.098 MHz) 9.000 (111.111 MHz) TLK_TXd2 i_SIU/reg_tx_clk_2/out 6.545 (152.788 MHz) 18.000 (55.556 MHz) -- Device: Actel - ProASIC3E : A3PE1500 : -2 -- CTE report summary.. CTE Report Summary End CTE Report Summary ..... CPU Time Used: 0 sec.