# Info: [9566]: Logging session transcript to file /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/REPORTS/precision_A3PE3000.log // Precision RTL Plus 2010a_Update2.254 (Production Release) Tue Oct 26 22:20:12 PDT 2010 // // Copyright (c) Mentor Graphics Corporation, 1996-2010, All Rights Reserved. // Portions copyright 1991-2008 Compuware Corporation // UNPUBLISHED, LICENSED SOFTWARE. // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS // // Running on Linux angelov@ew-dev #71-Ubuntu SMP Wed Jul 20 17:30:40 UTC 2011 2.6.32-33-generic i686 // // Start time Thu Aug 4 11:36:17 2011 # ------------------------------------------------- # Info: [9566]: Logging session transcript to file /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/REPORTS/precision_A3PE3000.log # Info: A3PE3000 # Info: Device die is A3PE3000 # Info: [9575]: Results directory: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/precision_A3PE3000 # Info: Unable to move logfile: move disabled # Info: [9574]: Input directory: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk # Info: [15295]: Setting up the design to use synthesis library "proasic3e.syn" # Info: [570]: The global max fanout is currently set to 2000 for Actel - ProASIC3E. # Info: [15319]: Setting Part to: "A3PE3000". # Info: [15320]: Setting Process to: "COMWC-2". # Info: [15322]: Setting Package to: "208 PQFP". # Info: [15295]: Setting up the design to use synthesis library "proasic3e.syn" # Warning: [15315]: The specified speedgrade COMWC-2 is not consistent with the resource information in the technology. The correct speedgrade -2 can be used here. # Warning: [15315]: The specified BTW typical is not consistent with the resource information in the technology. The correct BTW can be used here. # Info: [15319]: Setting Part to: "A3PE3000". # Info: [15320]: Setting Process to: "COMTC-2". # Info: [15322]: Setting Package to: "208 PQFP". # Info: [570]: The global max fanout is currently set to 2000 for Actel - ProASIC3E. # Info: [3022]: Reading file: /usr/local/bin/Mgc_home/pkgs/psr/techlibs/proasic3e.syn. # Info: [40000]: vhdlorder, Release 2010a.31 # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_bittiming.vhd", line 65: No such Package mcm_nw_timer is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_bittiming.vhd", line 66: No such Package mcm_nw_destuffing is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_sendtiming.vhd", line 68: No such Package mcm_nw_timer is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_sendtiming.vhd", line 69: No such Package mcm_nw_stuffing is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_dll.vhd", line 59: No such Package mcm_nw_bittiming is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_dll.vhd", line 60: No such Package mcm_nw_inbuf is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_dll.vhd", line 61: No such Package mcm_nw_outbuf is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_dll.vhd", line 62: No such Package mcm_nw_sendtiming is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_nwl.vhd", line 48: No such Package mcm_nw_nwsl is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_network_interface.vhd", line 88: No such Package mcm_nw_pl is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_network_interface.vhd", line 89: No such Package mcm_nw_dll is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_network_interface.vhd", line 90: No such Package mcm_nw_nwl is visible # Warning: [40000]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_network_interface.vhd", line 91: No such Package mcm_nw_apl is visible # Info: [40000]: Files sorted successfully. # Info: [40000]: hdl-analyze, Release RTLC-Precision 2010a.31 # Info: [41002]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/ibufds.v" ... # Info: [41002]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/obuf.v" ... # Info: [41002]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/TOP_PAD/top.v" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/build/buildstamp.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/hamm34enc67.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/hamm67dec34.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/hamm_reg.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_timer.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_destuffing.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_stuffing.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_outbuf.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_inbuf.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_bittiming.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_sendtiming.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_dll.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_nwsl.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_nwl.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_pl.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_network_interface.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/my_utilities.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/my_conversions.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/crc16.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/framing.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/i2c_if.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_in.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/parity_chk.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/parity_gen.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/pm_if.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_cmd.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_crc.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_data.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rxd_fifo.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rxdf_core.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/txd_fifo.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/txdf_core.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/pll40_40d_80.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/dp_sram_actel.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/ram4k9_actel.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/lut_8k_2.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/dp_sram_128x54.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/dp_sram_512x32.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/ram4k_w8_r1.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/bc_cnt.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/pt_align.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ttcex_out.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/cb_ac_sample.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cores/psrg.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/del_coinc_cnt_en.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt_cnt.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/random_pulser.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/shiftreg_piso.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/busy.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/ucrc_par.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_iserdes.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/serialb_com.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/ttc_receiver_top.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/clock_gen.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/bc_trigger.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/timing_analyzer.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ctp_tin.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_emulator.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_generator.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/adc78h89.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/relax.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/sm_adc78h89.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/ds_pack.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/program.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/timeslots.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/byteslots.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/ds_top.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/sfp_read.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/siu_io.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/clk_div.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/mux41nbit.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/adc2scsn.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/oddr2.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/ibuf.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/obufds.vhd" ... # Info: [42502]: Analyzing input file "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/iddr2.vhd" ... # Info: [649]: Current working directory: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/precision_A3PE3000. # Info: [40000]: RTLC-Driver, Release RTLC-Precision 2010a.31 # Info: [40000]: Last compiled on Oct 22 2010 17:45:31 # Info: [44512]: Initializing... # Info: [44504]: Partitioning design .... # Info: [40000]: RTLCompiler, Release RTLC-Precision 2010a.31 # Info: [40000]: Last compiled on Oct 22 2010 16:35:46 # Info: [44512]: Initializing... # Info: [44506]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}: Pre-processing... # Info: [44506]: Module work.clock_gen(behav){generic map (rst_width => 32)}: Pre-processing... # Info: [44506]: Module work.pll40_40d_80(DEF_ARCH): Pre-processing... # Info: [44506]: Module work.mcm_network_interface(structural): Pre-processing... # Info: [44506]: Module work.mcm_nw_pl(structural){generic map (len => 1)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_dll(structural){generic map (timing_count_range => 4 timing_recv_on => 2 stuff_length => 7 timing_sleep_length => 63 BUFSIZ => 69 BUFHALF => 4 COUNTER => 7)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_inbuf(structural){generic map (BUFSIZ => 69 BUFHALF => 4 COUNTER => 7)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_outbuf(structural){generic map (BUFSIZ => 69 COUNTER => 7)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_bittiming(structural){generic map (timing_count_range => 4 timing_recv_on => 2 stuff_length => 7 sync_len => 7 sync_bits => 2)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_timer(structural){generic map (count_range => 4 event_on => 2)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_destuffing(structural){generic map (stuff_length => 7)}: Pre-processing... # Info: [44506]: Module work.hamm_reg(a){generic map (Nbits => 4 Init_value => 0 Bypass => 0)}: Pre-processing... # Info: [44506]: Module work.hamm34enc67(a){generic map (Nbits => 4)}: Pre-processing... # Info: [44506]: Module work.hamm67dec34(a){generic map (Nbits => 4)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_sendtiming(structural){generic map (timing_count_range => 4 stuff_length => 7 timing_sleep_length => 63)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_timer(structural){generic map (count_range => 4 event_on => 0)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_timer(structural){generic map (count_range => 63 event_on => 63)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_stuffing(structural){generic map (stuff_length => 7)}: Pre-processing... # Info: [44506]: Module work.hamm_reg(a){generic map (Nbits => 3 Init_value => 0 Bypass => 0)}: Pre-processing... # Info: [44506]: Module work.hamm34enc67(a){generic map (Nbits => 3)}: Pre-processing... # Info: [44506]: Module work.hamm67dec34(a){generic map (Nbits => 3)}: Pre-processing... # Info: [44506]: Module work.mcm_nw_nwl(structural): Pre-processing... # Info: [44506]: Module work.mcm_nw_nwsl(structural): Pre-processing... # Info: [44506]: Module work.mcm_nw_apl(structural): Pre-processing... # Info: [45144]: Extracted FSM in module work.mcm_nw_apl(structural), with state variable = current_state_dp[2:0], async set/reset state(s) = 001 , number of states = 3. # Warning: [45741]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 164: FSM state variable 'current_state_dp[2:0]' doesn't have asynchronous or synchronous set/reset condition. # Info: [45144]: Preserving the original encoding in 3 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index Literal Encoding # Info: [40000]: FSM: 0 001 001 # Info: [40000]: FSM: 1 010 010 # Info: [40000]: FSM: 2 100 100 # Info: [40000]: This is not a Safe FSM as the default branch is being ignored. To make the FSM truly safe, please specify the attribute safe_fsm on the state variable # Info: [44506]: Module work.sys_config(arc){generic map (trg_cnt_width => 12)}: Pre-processing... # Info: [44506]: Module work.cb_ac_sample(oversample160): Pre-processing... # Info: [44506]: Module work.busy(behav): Pre-processing... # Info: [44506]: Module work.trg_lut(behav): Pre-processing... # Info: [44506]: Module work.lut_8k_2(a){generic map (piperA => false piperB => false)}: Pre-processing... # Info: [44506]: Module work.ram4k9_actel(a){generic map (piperA => false piperB => false Na_A => 9 Nd_A => 8 Na_B => 11 Nd_B => 2)}: Pre-processing... # Info: [44506]: Module work.pt_align(behav){generic map (no_inputs => 15 no_delays => 8)}: Pre-processing... # Info: [44506]: Module work.trg_emulator(behav){generic map (cnt_width => 12)}: Pre-processing... # Info: [44506]: Module work.trg_generator(behav){generic map (cnt_width => 12)}: Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_generator.vhd", line 54: Enumerated type trg_state with 9 elements encoded as onehot. # Info: [45144]: Encodings for trg_state values. # Info: [40000]: value trg_state[8-0] # Info: [40000]: idle --------1 # Info: [40000]: sent_ptrg -------1- # Info: [40000]: wait_l0 ------1-- # Info: [40000]: sent_l0 -----1--- # Info: [40000]: wait_l1 ----1---- # Info: [40000]: dead_nol0 ---1----- # Info: [40000]: dead_nol1 --1------ # Info: [40000]: dead_l1a -1------- # Info: [40000]: err 1-------- # Info: [40000]: FSM: Removing state for un-assigned literal 100000000 # Info: [45144]: Extracted FSM in module work.trg_generator(behav){generic map (cnt_width => 12)}, with state variable = state_next[8:0], async set/reset state(s) = 000000001 000000001 , number of states = 8. # Info: [45144]: Re-encoding 8 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 idle 000000001 00000001 # Info: [40000]: FSM: 1 sent_ptrg 000000010 00000010 # Info: [40000]: FSM: 2 wait_l0 000000100 00000100 # Info: [40000]: FSM: 3 sent_l0 000001000 00001000 # Info: [40000]: FSM: 4 wait_l1 000010000 00010000 # Info: [40000]: FSM: 5 dead_nol0 000100000 00100000 # Info: [40000]: FSM: 6 dead_nol1 001000000 01000000 # Info: [40000]: FSM: 7 dead_l1a 010000000 10000000 # Info: [44506]: Module work.random_pulser(behav): Pre-processing... # Info: [44506]: Module work.psrg(a){generic map (N => 32)}: Pre-processing... # Info: [44506]: Module work.ttcex_out(behav): Pre-processing... # Info: [44506]: Module work.ctp_tin(behav){generic map (signature(6 downto 0) => 53)}: Pre-processing... # Info: [44506]: Module work.shiftreg_piso(behav){generic map (width => 22)}: Pre-processing... # Info: [44506]: Module work.ttc_receiver_top(arc): Pre-processing... # Info: [44506]: Module work.serialb_com(arc){generic map (include_hamming => true)}: Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/serialb_com.vhd", line 57: Enumerated type state with 6 elements encoded as onehot. # Info: [45144]: Encodings for state values. # Info: [40000]: value state[5-0] # Info: [40000]: s_idle -----1 # Info: [40000]: s_fmt ----1- # Info: [40000]: s_get_data ---1-- # Info: [40000]: s_get_broadcast --1--- # Info: [40000]: s_stop -1---- # Info: [40000]: s_error 1----- # Info: [45144]: Extracted FSM in module work.serialb_com(arc){generic map (include_hamming => true)}, with state variable = next_state[5:0], async set/reset state(s) = (none), number of states = 6. # Info: [45144]: Re-encoding 6 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 s_idle 000001 000001 # Info: [40000]: FSM: 1 s_fmt 000010 000010 # Info: [40000]: FSM: 2 s_get_data 000100 000100 # Info: [40000]: FSM: 3 s_get_broadcast 001000 001000 # Info: [40000]: FSM: 4 s_stop 010000 010000 # Info: [40000]: FSM: 5 s_error 100000 100000 # Info: [44506]: Module work.channelB_reg(arch): Pre-processing... # Info: [44506]: Module work.bc_cnt(behav): Pre-processing... # Info: [44506]: Module work.bc_trigger(behav){generic map (no_bcmasks => 2)}: Pre-processing... # Info: [44506]: Module work.ram4k_w8_r1(struct): Pre-processing... # Info: [44506]: Module work.ram4k9_actel(a){generic map (piperA => false piperB => false Na_A => 9 Nd_A => 8 Na_B => 12 Nd_B => 1)}: Pre-processing... # Info: [45144]: Extracted FSM in module work.bc_trigger(behav){generic map (no_bcmasks => 2)}, with state variable = sm[1:0], async set/reset state(s) = (none), number of states = 4. # Info: [45144]: Preserving the original encoding in 4 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index Literal Encoding # Info: [40000]: FSM: 0 00 00 # Info: [40000]: FSM: 1 01 01 # Info: [40000]: FSM: 2 10 10 # Info: [40000]: FSM: 3 11 11 # Info: [44506]: Module work.del_coinc_cnt_en(behav){generic map (depth => 8 ref_offset => 6)}: Pre-processing... # Info: [44506]: Module work.ram_cnt(behav){generic map (width_addr => 7 width_ram => 54 width_fast => 8)}: Pre-processing... # Warning: [45597]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 66: Module: work-ram_cnt-7_54_8-behav, Net: 'cnt_fast_r' is a potential RAM of size 1024 bits. If you think that a RAM should have been inferred here, please set the attribute 'ram_block' on the signal to force a RAM. Syntax: "attribute ram_block: boolean; attribute ram_block of cnt_fast_r: signal is true;". If a RAM is still not inferred, please check warnings for why it was not inferred. # Warning: [45597]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 65: Module: work-ram_cnt-7_54_8-behav, Net: 'cnt_fast' is a potential RAM of size 1024 bits. If you think that a RAM should have been inferred here, please set the attribute 'ram_block' on the signal to force a RAM. Syntax: "attribute ram_block: boolean; attribute ram_block of cnt_fast: signal is true;". If a RAM is still not inferred, please check warnings for why it was not inferred. # Info: [44506]: Module work.dp_sram_128x54(a){generic map (piper => false)}: Pre-processing... # Info: [44506]: Module work.dp_sram_actel(a){generic map (piper => false Na_w => 8 Na_r => 8 Nd_w => 18 Nd_r => 18)}: Pre-processing... # Info: [44506]: Module work.ram_cnt_cnt(behav){generic map (N => 7)}: Pre-processing... # Info: [44506]: Module work.timing_analyzer(behav): Pre-processing... # Info: [44506]: Module work.dp_sram_512x32(a){generic map (piper => false)}: Pre-processing... # Info: [44506]: Module work.dp_sram_actel(a){generic map (piper => false Na_w => 9 Na_r => 9 Nd_w => 8 Nd_r => 8)}: Pre-processing... # Info: [44506]: Module work.cbbr_top(behv){generic map (clkratio => 10)}: Pre-processing... # Info: [44506]: Module work.ucrc_par(rtl){generic map (POLYNOMIAL(0 to 31) => 04c11db7 INIT_VALUE(0 to 31) => 00000000 DATA_WIDTH => 32 SYNC_RESET => 1)}: Pre-processing... # Warning: [45597]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/ucrc_par.vhd", line 80: Module: work-ucrc_par-l0_r31_04c11db7_l0_r31_00000000_32_1-rtl, Net: 'crca' is a potential RAM of size 2048 bits. If you think that a RAM should have been inferred here, please set the attribute 'ram_block' on the signal to force a RAM. Syntax: "attribute ram_block: boolean; attribute ram_block of crca: signal is true;". If a RAM is still not inferred, please check warnings for why it was not inferred. # Info: [44506]: Module work.cbbr_iserdes(behv): Pre-processing... # Info: [44506]: Module work.adc2scsn(a): Pre-processing... # Info: [44506]: Module work.sm_adc78h89(a){generic map (iCLK => false iCNV => false iDIN => false iDOU => false Nstep => 1 Nacc => 19 Ndiv => 40)}: Pre-processing... # Info: [44506]: Module work.adc78h89(a){generic map (iCLK => false iCNV => false iDIN => false iDOU => false Nbit => 16 Ndiv => 40)}: Pre-processing... # Info: [45224]: Treating FSM for "sm" as safe. # Info: [45144]: Extracted safe FSM in module work.adc78h89(a){generic map (iCLK => false iCNV => false iDIN => false iDOU => false Nbit => 16 Ndiv => 40)}, with state variable = sm[1:0], async set/reset state(s) = (none), number of states = 4. # Info: [45144]: Re-encoding 4 state FSM as "gray". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 idle 00 00 # Info: [40000]: FSM: 1 clk0 01 01 # Info: [40000]: FSM: 2 clk1 10 11 # Info: [40000]: FSM: 3 finish 11 10 # Info: [44506]: Module work.relax(a){generic map (Nd => 12 Nf => 0 Ns => 1 Na => 19)}: Pre-processing... # Info: [45224]: Treating FSM for "sm" as safe. # Info: [45144]: Extracted safe FSM in module work.sm_adc78h89(a){generic map (iCLK => false iCNV => false iDIN => false iDOU => false Nstep => 1 Nacc => 19 Ndiv => 40)}, with state variable = sm[1:0], async set/reset state(s) = (none), number of states = 3. # Warning: [45766]: No default specified in safe FSM case statement for sm; binary encoding will be applied to ensure safety. # Info: [45144]: Re-encoding 3 state FSM as "gray". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 idle 00 00 # Info: [40000]: FSM: 1 start_s 01 01 # Info: [40000]: FSM: 2 wait_s 10 11 # Info: [44506]: Module work.clk_div(a){generic map (Nd => 40)}: Pre-processing... # Info: [44506]: Module work.ds_top(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}: Pre-processing... # Info: [44506]: Module work.program(a): Pre-processing... # Info: [44506]: Module work.byteslots(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}: Pre-processing... # Info: [44506]: Module work.timeslots(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}: Pre-processing... # Info: [45224]: Treating FSM for "sm" as safe. # Info: [45144]: Extracted safe FSM in module work.timeslots(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}, with state variable = sm[3:0], async set/reset state(s) = 0000 , number of states = 9. # Info: [45144]: Re-encoding 9 state FSM as "gray". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 idle 0000 0000 # Info: [40000]: FSM: 1 reset_low 0001 0001 # Info: [40000]: FSM: 2 reset_sense 0010 0011 # Info: [40000]: FSM: 3 reset_high 0011 0010 # Info: [40000]: FSM: 4 read_low 0100 0110 # Info: [40000]: FSM: 5 read_sense 0101 0111 # Info: [40000]: FSM: 6 write_0 0110 0101 # Info: [40000]: FSM: 7 write_1 0111 0100 # Info: [40000]: FSM: 8 finish 1000 1100 # Info: [45224]: Treating FSM for "sm" as safe. # Info: [45144]: Extracted safe FSM in module work.byteslots(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}, with state variable = sm[2:0], async set/reset state(s) = 000 , number of states = 5. # Info: [45144]: Re-encoding 5 state FSM as "gray". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 idle 000 000 # Info: [40000]: FSM: 1 reset 010 001 # Info: [40000]: FSM: 2 recv_byte 100 011 # Info: [40000]: FSM: 3 send_byte 011 010 # Info: [40000]: FSM: 4 wait_bitsm 001 110 # Info: [45224]: Treating FSM for "sm" as safe. # Info: [45144]: Extracted safe FSM in module work.ds_top(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}, with state variable = sm[2:0], async set/reset state(s) = 000 , number of states = 7. # Info: [45144]: Re-encoding 7 state FSM as "gray". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 idle 000 000 # Info: [40000]: FSM: 1 resets 001 001 # Info: [40000]: FSM: 2 readb 011 011 # Info: [40000]: FSM: 3 writeb 010 010 # Info: [40000]: FSM: 4 pullH 101 110 # Info: [40000]: FSM: 5 waitp 100 111 # Info: [40000]: FSM: 6 finish 110 101 # Info: [44506]: Module work.sfp_read(a): Pre-processing... # Info: [44506]: Module work.siu_io(a): Pre-processing... # Info: [44506]: Module work.mux41nbit(a){generic map (Nbit => 32)}: Pre-processing... # Info: [44506]: Module work.siu_top_core(SYN): Pre-processing... # Info: [44506]: Module work.rx_in(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_in.vhd", line 46: Enumerated type susp_state with 5 elements encoded as onehot. # Info: [45144]: Encodings for susp_state values. # Info: [40000]: value susp_state[4-0] # Info: [40000]: SUSP_RESET ----1 # Info: [40000]: SUSP_IDLE1 ---1- # Info: [40000]: SUSP_IDLE2 --1-- # Info: [40000]: SUSP_CEXT -1--- # Info: [40000]: SUSP_SUSP 1---- # Info: [45144]: Extracted FSM in module work.rx_in(SYN), with state variable = susp_present[4:0], async set/reset state(s) = 00001 00001 , number of states = 5. # Info: [45144]: Re-encoding 5 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 SUSP_RESET 00001 00001 # Info: [40000]: FSM: 1 SUSP_IDLE1 00010 00010 # Info: [40000]: FSM: 2 SUSP_IDLE2 00100 00100 # Info: [40000]: FSM: 3 SUSP_CEXT 01000 01000 # Info: [40000]: FSM: 4 SUSP_SUSP 10000 10000 # Info: [44506]: Module work.rx_crc(SYN): Pre-processing... # Info: [44506]: Module work.crc16(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_crc.vhd", line 59: Enumerated type crc_state with 7 elements encoded as onehot. # Info: [45144]: Encodings for crc_state values. # Info: [40000]: value crc_state[6-0] # Info: [40000]: CRC_RST ------1 # Info: [40000]: CRC_START -----1- # Info: [40000]: CRC_CALC ----1-- # Info: [40000]: CRC_WAIT ---1--- # Info: [40000]: CRC_TEST --1---- # Info: [40000]: CRC_ERROR -1----- # Info: [40000]: CRC_SKIP 1------ # Info: [45144]: Extracted FSM in module work.rx_crc(SYN), with state variable = crc_present[6:0], async set/reset state(s) = 0000001 0000001 , number of states = 7. # Info: [45144]: Re-encoding 7 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 CRC_RST 0000001 0000001 # Info: [40000]: FSM: 1 CRC_START 0000010 0000010 # Info: [40000]: FSM: 2 CRC_CALC 0000100 0000100 # Info: [40000]: FSM: 3 CRC_WAIT 0001000 0001000 # Info: [40000]: FSM: 4 CRC_TEST 0010000 0010000 # Info: [40000]: FSM: 5 CRC_ERROR 0100000 0100000 # Info: [40000]: FSM: 6 CRC_SKIP 1000000 1000000 # Info: [44506]: Module work.rx_cmd(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_cmd.vhd", line 62: Enumerated type rxc_state with 8 elements encoded as onehot. # Info: [45144]: Encodings for rxc_state values. # Info: [40000]: value rxc_state[7-0] # Info: [40000]: RXC_IDLE -------1 # Info: [40000]: RXC_DIAG ------1- # Info: [40000]: RXC_SOF -----1-- # Info: [40000]: RXC_CWLOW2 ----1--- # Info: [40000]: RXC_CWHIGH1 ---1---- # Info: [40000]: RXC_CWHIGH2 --1----- # Info: [40000]: RXC_CWTEST -1------ # Info: [40000]: RXC_SKIP 1------- # Info: [45144]: Extracted FSM in module work.rx_cmd(SYN), with state variable = rxc_present[7:0], async set/reset state(s) = 00000001 00000001 , number of states = 8. # Info: [45144]: Re-encoding 8 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 RXC_IDLE 00000001 00000001 # Info: [40000]: FSM: 1 RXC_DIAG 00000010 00000010 # Info: [40000]: FSM: 2 RXC_SOF 00000100 00000100 # Info: [40000]: FSM: 3 RXC_CWLOW2 00001000 00001000 # Info: [40000]: FSM: 4 RXC_CWHIGH1 00010000 00010000 # Info: [40000]: FSM: 5 RXC_CWHIGH2 00100000 00100000 # Info: [40000]: FSM: 6 RXC_CWTEST 01000000 01000000 # Info: [40000]: FSM: 7 RXC_SKIP 10000000 10000000 # Info: [45144]: Extracted FSM in module work.rx_cmd(SYN), with state variable = jcmd_present[1:0], async set/reset state(s) = 00 00 , number of states = 3. # Info: [45144]: Preserving the original encoding in 3 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 JCMD_EMPTY 00 00 # Info: [40000]: FSM: 1 JCMD_REQUEST 01 01 # Info: [40000]: FSM: 2 jCMD_GOEMPTY 10 10 # Info: [45144]: Extracted FSM in module work.rx_cmd(SYN), with state variable = scmd_present[1:0], async set/reset state(s) = 00 00 , number of states = 3. # Info: [45144]: Preserving the original encoding in 3 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 SCMD_EMPTY 00 00 # Info: [40000]: FSM: 1 SCMD_REQUEST 01 01 # Info: [40000]: FSM: 2 SCMD_GOEMPTY 10 10 # Info: [44506]: Module work.rx_data(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_data.vhd", line 61: Enumerated type rxd_state with 9 elements encoded as onehot. # Info: [45144]: Encodings for rxd_state values. # Info: [40000]: value rxd_state[8-0] # Info: [40000]: RXD_IDLE --------1 # Info: [40000]: RXD_SOF -------1- # Info: [40000]: RXD_DWLOW ------1-- # Info: [40000]: RXD_DWHIGH -----1--- # Info: [40000]: RXD_CWLOW2 ----1---- # Info: [40000]: RXD_CWHIGH1 ---1----- # Info: [40000]: RXD_CWHIGH2 --1------ # Info: [40000]: RXD_CWTEST -1------- # Info: [40000]: RXD_SKIP 1-------- # Info: [45144]: Extracted FSM in module work.rx_data(SYN), with state variable = rxd_present[8:0], async set/reset state(s) = 000000001 000000001 , number of states = 9. # Info: [45144]: Re-encoding 9 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 RXD_IDLE 000000001 000000001 # Info: [40000]: FSM: 1 RXD_SOF 000000010 000000010 # Info: [40000]: FSM: 2 RXD_DWLOW 000000100 000000100 # Info: [40000]: FSM: 3 RXD_DWHIGH 000001000 000001000 # Info: [40000]: FSM: 4 RXD_CWLOW2 000010000 000010000 # Info: [40000]: FSM: 5 RXD_CWHIGH1 000100000 000100000 # Info: [40000]: FSM: 6 RXD_CWHIGH2 001000000 001000000 # Info: [40000]: FSM: 7 RXD_CWTEST 010000000 010000000 # Info: [40000]: FSM: 8 RXD_SKIP 100000000 100000000 # Info: [45144]: Extracted FSM in module work.rx_data(SYN), with state variable = frc_present[1:0], async set/reset state(s) = 00 00 , number of states = 3. # Info: [45144]: Preserving the original encoding in 3 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 FRC_RESET 00 00 # Info: [40000]: FSM: 1 FRC_DUMMY 01 01 # Info: [40000]: FSM: 2 FRC_ADVANCE 10 10 # Info: [44506]: Module work.lm_siu(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 77: Enumerated type lm_state with 8 elements encoded as onehot. # Info: [45144]: Encodings for lm_state values. # Info: [40000]: value lm_state[7-0] # Info: [40000]: LM_SIURESET -------1 # Info: [40000]: LM_LOWPOWER ------1- # Info: [40000]: LM_POWERONRST -----1-- # Info: [40000]: LM_OFFLINE ----1--- # Info: [40000]: LM_ONLINE ---1---- # Info: [40000]: LM_TESTMODE --1----- # Info: [40000]: LM_RXSUSPEND -1------ # Info: [40000]: LM_GOLOWPWR 1------- # Info: [45144]: Extracted FSM in module work.lm_siu(SYN), with state variable = lm_present[7:0], async set/reset state(s) = 00000001 00000001 , number of states = 8. # Info: [45144]: Re-encoding 8 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 LM_SIURESET 00000001 00000001 # Info: [40000]: FSM: 1 LM_LOWPOWER 00000010 00000010 # Info: [40000]: FSM: 2 LM_POWERONRST 00000100 00000100 # Info: [40000]: FSM: 3 LM_OFFLINE 00001000 00001000 # Info: [40000]: FSM: 4 LM_ONLINE 00010000 00010000 # Info: [40000]: FSM: 5 LM_TESTMODE 00100000 00100000 # Info: [40000]: FSM: 6 LM_RXSUSPEND 01000000 01000000 # Info: [40000]: FSM: 7 LM_GOLOWPWR 10000000 10000000 # Info: [45144]: Extracted FSM in module work.lm_siu(SYN), with state variable = rx_present[1:0], async set/reset state(s) = 00 00 , number of states = 4. # Info: [45144]: Preserving the original encoding in 4 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 RX_DISABLED 00 00 # Info: [40000]: FSM: 1 RX_GOENA 01 01 # Info: [40000]: FSM: 2 RX_ENABLED 10 10 # Info: [40000]: FSM: 3 RX_GODIS 11 11 # Info: [44506]: Module work.cm_siu(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 95: Enumerated type sts_state with 15 elements encoded as onehot. # Info: [45144]: Encodings for sts_state values. # Info: [40000]: value sts_state[14-0] # Info: [40000]: STS_NOCMD --------------1 # Info: [40000]: STS_SIUCMD -------------1- # Info: [40000]: STS_JTAGCMD ------------1-- # Info: [40000]: STS_RCIFST -----------1--- # Info: [40000]: STS_RFWVER ----------1---- # Info: [40000]: STS_RHWVER1 ---------1----- # Info: [40000]: STS_RHWVER2 --------1------ # Info: [40000]: STS_WHWVER -------1------- # Info: [40000]: STS_RPMVAL ------1-------- # Info: [40000]: STS_IFLOOP -----1--------- # Info: [40000]: STS_TESTCMD ----1---------- # Info: [40000]: STS_CTSTW ---1----------- # Info: [40000]: STS_CTSTWNOK --1------------ # Info: [40000]: STS_SWAIT -1------------- # Info: [40000]: STS_JWAIT 1-------------- # Info: [45144]: Extracted FSM in module work.cm_siu(SYN), with state variable = sts_present[14:0], async set/reset state(s) = 000000000000001 000000000000001 , number of states = 15. # Info: [45144]: Re-encoding 15 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 STS_NOCMD 000000000000001 000000000000001 # Info: [40000]: FSM: 1 STS_SIUCMD 000000000000010 000000000000010 # Info: [40000]: FSM: 2 STS_JTAGCMD 000000000000100 000000000000100 # Info: [40000]: FSM: 3 STS_RCIFST 000000000001000 000000000001000 # Info: [40000]: FSM: 4 STS_RFWVER 000000000010000 000000000010000 # Info: [40000]: FSM: 5 STS_RHWVER1 000000000100000 000000000100000 # Info: [40000]: FSM: 6 STS_RHWVER2 000000001000000 000000001000000 # Info: [40000]: FSM: 7 STS_WHWVER 000000010000000 000000010000000 # Info: [40000]: FSM: 8 STS_RPMVAL 000000100000000 000000100000000 # Info: [40000]: FSM: 9 STS_IFLOOP 000001000000000 000001000000000 # Info: [40000]: FSM: 10 STS_TESTCMD 000010000000000 000010000000000 # Info: [40000]: FSM: 11 STS_CTSTW 000100000000000 000100000000000 # Info: [40000]: FSM: 12 STS_CTSTWNOK 001000000000000 001000000000000 # Info: [40000]: FSM: 13 STS_SWAIT 010000000000000 010000000000000 # Info: [40000]: FSM: 14 STS_JWAIT 100000000000000 100000000000000 # Info: [44506]: Module work.framing(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/framing.vhd", line 74: Enumerated type tx_state with 19 elements encoded as onehot. # Info: [45144]: Encodings for tx_state values. # Info: [40000]: value tx_state[18-0] # Info: [40000]: TX_IDLE1 ------------------1 # Info: [40000]: TX_IDLE2 -----------------1- # Info: [40000]: TX_DIAG1 ----------------1-- # Info: [40000]: TX_DIAG2 ---------------1--- # Info: [40000]: TX_IDLE3 --------------1---- # Info: [40000]: TX_IDLE4 -------------1----- # Info: [40000]: TX_CFRSC ------------1------ # Info: [40000]: TX_C1FD1L -----------1------- # Info: [40000]: TX_C1FD1H ----------1-------- # Info: [40000]: TX_C1FD2L ---------1--------- # Info: [40000]: TX_C1FD2H --------1---------- # Info: [40000]: TX_C2FD1L -------1----------- # Info: [40000]: TX_C2FD1H ------1------------ # Info: [40000]: TX_C2FD2L -----1------------- # Info: [40000]: TX_C2FD2H ----1-------------- # Info: [40000]: TX_DFRSD ---1--------------- # Info: [40000]: TX_DFRDWL --1---------------- # Info: [40000]: TX_DFRDWH -1----------------- # Info: [40000]: TX_DFRCRC 1------------------ # Info: [45144]: Extracted FSM in module work.framing(SYN), with state variable = tx_present[18:0], async set/reset state(s) = 0000000000000000001 0000000000000000001 , number of states = 19. # Info: [45144]: Re-encoding 19 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 TX_IDLE1 0000000000000000001 0000000000000000001 # Info: [40000]: FSM: 1 TX_IDLE2 0000000000000000010 0000000000000000010 # Info: [40000]: FSM: 2 TX_DIAG1 0000000000000000100 0000000000000000100 # Info: [40000]: FSM: 3 TX_DIAG2 0000000000000001000 0000000000000001000 # Info: [40000]: FSM: 4 TX_IDLE3 0000000000000010000 0000000000000010000 # Info: [40000]: FSM: 5 TX_IDLE4 0000000000000100000 0000000000000100000 # Info: [40000]: FSM: 6 TX_CFRSC 0000000000001000000 0000000000001000000 # Info: [40000]: FSM: 7 TX_C1FD1L 0000000000010000000 0000000000010000000 # Info: [40000]: FSM: 8 TX_C1FD1H 0000000000100000000 0000000000100000000 # Info: [40000]: FSM: 9 TX_C1FD2L 0000000001000000000 0000000001000000000 # Info: [40000]: FSM: 10 TX_C1FD2H 0000000010000000000 0000000010000000000 # Info: [40000]: FSM: 11 TX_C2FD1L 0000000100000000000 0000000100000000000 # Info: [40000]: FSM: 12 TX_C2FD1H 0000001000000000000 0000001000000000000 # Info: [40000]: FSM: 13 TX_C2FD2L 0000010000000000000 0000010000000000000 # Info: [40000]: FSM: 14 TX_C2FD2H 0000100000000000000 0000100000000000000 # Info: [40000]: FSM: 15 TX_DFRSD 0001000000000000000 0001000000000000000 # Info: [40000]: FSM: 16 TX_DFRDWL 0010000000000000000 0010000000000000000 # Info: [40000]: FSM: 17 TX_DFRDWH 0100000000000000000 0100000000000000000 # Info: [40000]: FSM: 18 TX_DFRCRC 1000000000000000000 1000000000000000000 # Info: [44506]: Module work.fee_if(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd", line 79: Enumerated type bdir_state with 10 elements encoded as onehot. # Info: [45144]: Encodings for bdir_state values. # Info: [40000]: value bdir_state[9-0] # Info: [40000]: BDIR_OUTPUT ---------1 # Info: [40000]: BDIR_TURNIN1 --------1- # Info: [40000]: BDIR_TURNIN2 -------1-- # Info: [40000]: BDIR_TURNIN3 ------1--- # Info: [40000]: BDIR_TURNIN4 -----1---- # Info: [40000]: BDIR_INPUT ----1----- # Info: [40000]: BDIR_TURNOUT1 ---1------ # Info: [40000]: BDIR_TURNOUT2 --1------- # Info: [40000]: BDIR_TURNOUT3 -1-------- # Info: [40000]: BDIR_TURNOUT4 1--------- # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd", line 92: Enumerated type fin_state with 18 elements encoded as onehot. # Info: [45144]: Encodings for fin_state values. # Info: [40000]: value fin_state[17-0] # Info: [40000]: FIN_IDLE -----------------1 # Info: [40000]: FIN_FEECMD ----------------1- # Info: [40000]: FIN_INVCMD ---------------1-- # Info: [40000]: FIN_FCTRLCMD --------------1--- # Info: [40000]: FIN_FSTRDCMD -------------1---- # Info: [40000]: FIN_FSTRDWAIT ------------1----- # Info: [40000]: FIN_FSTRDTERM -----------1------ # Info: [40000]: FIN_BWRCMD ----------1------- # Info: [40000]: FIN_BWRDATA ---------1-------- # Info: [40000]: FIN_BWRWAIT --------1--------- # Info: [40000]: FIN_BWRDTCC -------1---------- # Info: [40000]: FIN_BWRTERM ------1----------- # Info: [40000]: FIN_BRDCMD -----1------------ # Info: [40000]: FIN_BRDWAIT ----1------------- # Info: [40000]: FIN_BRDEND ---1-------------- # Info: [40000]: FIN_BRDTERM --1--------------- # Info: [40000]: FIN_TESTWAIT -1---------------- # Info: [40000]: FIN_TESTDATA 1----------------- # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd", line 113: Enumerated type fout_state with 11 elements encoded as onehot. # Info: [45144]: Encodings for fout_state values. # Info: [40000]: value fout_state[10-0] # Info: [40000]: FOUT_IDLE ----------1 # Info: [40000]: FOUT_CTSTW1 ---------1- # Info: [40000]: FOUT_CTSTW2 --------1-- # Info: [40000]: FOUT_BUSTOSIU -------1--- # Info: [40000]: FOUT_FSTRD ------1---- # Info: [40000]: FOUT_BRDDATA -----1----- # Info: [40000]: FOUT_BRDWAIT ----1------ # Info: [40000]: FOUT_BRDDTSW ---1------- # Info: [40000]: FOUT_BRDGAP --1-------- # Info: [40000]: FOUT_BUSTOFEE -1--------- # Info: [40000]: FOUT_TESTDATA 1---------- # Info: [45144]: Extracted FSM in module work.fee_if(SYN), with state variable = bdir_present[9:0], async set/reset state(s) = 0000000001 0000000001 , number of states = 10. # Info: [45144]: Re-encoding 10 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 BDIR_OUTPUT 0000000001 0000000001 # Info: [40000]: FSM: 1 BDIR_TURNIN1 0000000010 0000000010 # Info: [40000]: FSM: 2 BDIR_TURNIN2 0000000100 0000000100 # Info: [40000]: FSM: 3 BDIR_TURNIN3 0000001000 0000001000 # Info: [40000]: FSM: 4 BDIR_TURNIN4 0000010000 0000010000 # Info: [40000]: FSM: 5 BDIR_INPUT 0000100000 0000100000 # Info: [40000]: FSM: 6 BDIR_TURNOUT1 0001000000 0001000000 # Info: [40000]: FSM: 7 BDIR_TURNOUT2 0010000000 0010000000 # Info: [40000]: FSM: 8 BDIR_TURNOUT3 0100000000 0100000000 # Info: [40000]: FSM: 9 BDIR_TURNOUT4 1000000000 1000000000 # Info: [45144]: Extracted FSM in module work.fee_if(SYN), with state variable = fout_present[10:0], async set/reset state(s) = 00000000001 00000000001 , number of states = 11. # Info: [45144]: Re-encoding 11 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 FOUT_IDLE 00000000001 00000000001 # Info: [40000]: FSM: 1 FOUT_CTSTW1 00000000010 00000000010 # Info: [40000]: FSM: 2 FOUT_CTSTW2 00000000100 00000000100 # Info: [40000]: FSM: 3 FOUT_BUSTOSIU 00000001000 00000001000 # Info: [40000]: FSM: 4 FOUT_FSTRD 00000010000 00000010000 # Info: [40000]: FSM: 5 FOUT_BRDDATA 00000100000 00000100000 # Info: [40000]: FSM: 6 FOUT_BRDWAIT 00001000000 00001000000 # Info: [40000]: FSM: 7 FOUT_BRDDTSW 00010000000 00010000000 # Info: [40000]: FSM: 8 FOUT_BRDGAP 00100000000 00100000000 # Info: [40000]: FSM: 9 FOUT_BUSTOFEE 01000000000 01000000000 # Info: [40000]: FSM: 10 FOUT_TESTDATA 10000000000 10000000000 # Info: [45144]: Extracted FSM in module work.fee_if(SYN), with state variable = fin_present[17:0], async set/reset state(s) = 000000000000000001 000000000000000001 , number of states = 18. # Info: [45144]: Re-encoding 18 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 FIN_IDLE 000000000000000001 000000000000000001 # Info: [40000]: FSM: 1 FIN_FEECMD 000000000000000010 000000000000000010 # Info: [40000]: FSM: 2 FIN_INVCMD 000000000000000100 000000000000000100 # Info: [40000]: FSM: 3 FIN_FCTRLCMD 000000000000001000 000000000000001000 # Info: [40000]: FSM: 4 FIN_FSTRDCMD 000000000000010000 000000000000010000 # Info: [40000]: FSM: 5 FIN_FSTRDWAIT 000000000000100000 000000000000100000 # Info: [40000]: FSM: 6 FIN_FSTRDTERM 000000000001000000 000000000001000000 # Info: [40000]: FSM: 7 FIN_BWRCMD 000000000010000000 000000000010000000 # Info: [40000]: FSM: 8 FIN_BWRDATA 000000000100000000 000000000100000000 # Info: [40000]: FSM: 9 FIN_BWRWAIT 000000001000000000 000000001000000000 # Info: [40000]: FSM: 10 FIN_BWRDTCC 000000010000000000 000000010000000000 # Info: [40000]: FSM: 11 FIN_BWRTERM 000000100000000000 000000100000000000 # Info: [40000]: FSM: 12 FIN_BRDCMD 000001000000000000 000001000000000000 # Info: [40000]: FSM: 13 FIN_BRDWAIT 000010000000000000 000010000000000000 # Info: [40000]: FSM: 14 FIN_BRDEND 000100000000000000 000100000000000000 # Info: [40000]: FSM: 15 FIN_BRDTERM 001000000000000000 001000000000000000 # Info: [40000]: FSM: 16 FIN_TESTWAIT 010000000000000000 010000000000000000 # Info: [40000]: FSM: 17 FIN_TESTDATA 100000000000000000 100000000000000000 # Info: [44506]: Module work.i2c_if(SYN): Pre-processing... # Info: [45143]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/i2c_if.vhd", line 56: Enumerated type i2c_state with 15 elements encoded as onehot. # Info: [45144]: Encodings for i2c_state values. # Info: [40000]: value i2c_state[14-0] # Info: [40000]: I2C_IDLE --------------1 # Info: [40000]: I2C_TXSTART -------------1- # Info: [40000]: I2C_CTRLWR ------------1-- # Info: [40000]: I2C_CTRLWRACK -----------1--- # Info: [40000]: I2C_TXADDR ----------1---- # Info: [40000]: I2C_ADDRACK ---------1----- # Info: [40000]: I2C_TXDATA --------1------ # Info: [40000]: I2C_DATAACK -------1------- # Info: [40000]: I2C_TXSTART2 ------1-------- # Info: [40000]: I2C_CTRLRD -----1--------- # Info: [40000]: I2C_CTRLRDACK ----1---------- # Info: [40000]: I2C_RXDATA ---1----------- # Info: [40000]: I2C_TXNACK --1------------ # Info: [40000]: I2C_TXSTOP -1------------- # Info: [40000]: I2C_READY 1-------------- # Info: [45144]: Extracted FSM in module work.i2c_if(SYN), with state variable = i2c_present[14:0], async set/reset state(s) = 000000000000001 000000000000001 , number of states = 15. # Info: [45144]: Re-encoding 15 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 I2C_IDLE 000000000000001 000000000000001 # Info: [40000]: FSM: 1 I2C_TXSTART 000000000000010 000000000000010 # Info: [40000]: FSM: 2 I2C_CTRLWR 000000000000100 000000000000100 # Info: [40000]: FSM: 3 I2C_CTRLWRACK 000000000001000 000000000001000 # Info: [40000]: FSM: 4 I2C_TXADDR 000000000010000 000000000010000 # Info: [40000]: FSM: 5 I2C_ADDRACK 000000000100000 000000000100000 # Info: [40000]: FSM: 6 I2C_TXDATA 000000001000000 000000001000000 # Info: [40000]: FSM: 7 I2C_DATAACK 000000010000000 000000010000000 # Info: [40000]: FSM: 8 I2C_TXSTART2 000000100000000 000000100000000 # Info: [40000]: FSM: 9 I2C_CTRLRD 000001000000000 000001000000000 # Info: [40000]: FSM: 10 I2C_CTRLRDACK 000010000000000 000010000000000 # Info: [40000]: FSM: 11 I2C_RXDATA 000100000000000 000100000000000 # Info: [40000]: FSM: 12 I2C_TXNACK 001000000000000 001000000000000 # Info: [40000]: FSM: 13 I2C_TXSTOP 010000000000000 010000000000000 # Info: [40000]: FSM: 14 I2C_READY 100000000000000 100000000000000 # Info: [45144]: Extracted FSM in module work.i2c_if(SYN), with state variable = scl_present[1:0], async set/reset state(s) = 00 00 , number of states = 4. # Info: [45144]: Preserving the original encoding in 4 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 SCL_HIGH 00 00 # Info: [40000]: FSM: 1 SCL_GOLOW 01 01 # Info: [40000]: FSM: 2 SCL_LOW 10 10 # Info: [40000]: FSM: 3 SCL_GOHIGH 11 11 # Info: [44506]: Module work.rxd_fifo(SYN): Pre-processing... # Info: [44506]: Module work.rxdf_core(DEF_ARCH): Pre-processing... # Info: [45144]: Extracted FSM in module work.rxd_fifo(SYN), with state variable = read_present[1:0], async set/reset state(s) = 00 00 , number of states = 3. # Info: [45144]: Preserving the original encoding in 3 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 RD_EMPTY 00 00 # Info: [40000]: FSM: 1 RD_FETCH 01 01 # Info: [40000]: FSM: 2 RD_NEMPTY 10 10 # Info: [44506]: Module work.txd_fifo(SYN): Pre-processing... # Info: [44506]: Module work.txdf_core(DEF_ARCH): Pre-processing... # Info: [45144]: Extracted FSM in module work.txd_fifo(SYN), with state variable = read_present[1:0], async set/reset state(s) = 00 00 , number of states = 3. # Info: [45144]: Preserving the original encoding in 3 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index State Name Literal Encoding # Info: [40000]: FSM: 0 RD_EMPTY 00 00 # Info: [40000]: FSM: 1 RD_FETCH 01 01 # Info: [40000]: FSM: 2 RD_NEMPTY 10 10 # Info: [44506]: Module work.pm_if(SYN): Pre-processing... # Info: [44506]: Module work.parity_gen(SYN): Pre-processing... # Info: [44506]: Module work.parity_chk(SYN): Pre-processing... # Info: [45144]: Extracted FSM in module work.siu_top_core(SYN), with state variable = mode_sel[1:0], async set/reset state(s) = 00 , number of states = 4. # Info: [45144]: Preserving the original encoding in 4 state FSM # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index Literal Encoding # Info: [40000]: FSM: 0 00 00 # Info: [40000]: FSM: 1 01 01 # Info: [40000]: FSM: 2 10 10 # Info: [40000]: FSM: 3 11 11 # Info: [44506]: Module work.OBUFDS(a): Pre-processing... # Info: [44506]: Module work.IBUF(a): Pre-processing... # Info: [44506]: Module work.iddr2(a): Pre-processing... # Info: [44506]: Module work.oddr2(a): Pre-processing... # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_bittiming.vhd", line 123: signal sync_debug has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_stuffing.vhd", line 60: signal stuff has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 172: signal req_fall has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 178: signal ack_oase has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 182: signal bus_req_intrnl has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 183: signal bus_we_intrnl has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 105: signal syscfg_addr_r[15:12] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/cb_ac_sample.vhd", line 25: signal cb_par_r[7] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/busy.vhd", line 7: Input port rst has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/busy.vhd", line 10: Input port ctrl[3:2] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/ram4k9_actel.vhd", line 132: signal DO_A[8] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/ram4k9_actel.vhd", line 133: signal DO_B[8:2] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 19: Input port pattern_tof has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 20: Input port pattern_cba has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 21: Input port pattern_cbc has never been used. # Warning: [45731]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 22: Output port pattern_match_tof has never been assigned a value. # Warning: [45731]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 23: Output port pattern_match_cba has never been assigned a value. # Warning: [45731]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 24: Output port pattern_match_cbc has never been assigned a value. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 30: Input port scsn_addr[15:12] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_generator.vhd", line 65: signal pt_ctp_pre_gen has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ttcex_out.vhd", line 17: Input port ctrl[15:4] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 13: Input port data[38:23] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 13: Input port data[4:0] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 87: signal brc_data_r has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/bc_cnt.vhd", line 14: Input port l2a_msg[83:0] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/bc_cnt.vhd", line 30: signal bc_msg_i has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/ram4k9_actel.vhd", line 132: signal DO_A[8] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/ram4k9_actel.vhd", line 133: signal DO_B[8:1] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/bc_trigger.vhd", line 14: Input port clk_scsn has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/bc_trigger.vhd", line 15: Input port rst_scsn has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/bc_trigger.vhd", line 56: signal scsn_dout_byte has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 80: signal req_addr[15:12] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/arch/actel/cores/dp_sram_actel.vhd", line 105: signal RD[17:8] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/timing_analyzer.vhd", line 11: Input port clk_scsn has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/timing_analyzer.vhd", line 12: Input port rst_scsn has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/timing_analyzer.vhd", line 20: Input port scsn_addr[15:9] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd", line 20: Input port cbbr_IBO[31:1] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd", line 24: Input port req has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 264: signal clk40_ps has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 265: signal clk40_ps_180 has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 267: signal clk80_180 has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 301: signal scsn_bus_we_ramcnt has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 303: signal scsn_bus_we_ta has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 327: signal cba_lut[3] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 327: signal cba_lut[1] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 328: signal cbc_lut[3] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 328: signal cbc_lut[1] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 334: signal pt_trg_ctb[2] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 335: signal pt_trg_ctb_r[11] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 335: signal pt_trg_ctb_r[1:0] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 350: signal lut_mon[12:8] has never been used. # Warning: [45730]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 359: signal l0_ctb has no drivers, will be treated as don't care. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 368: signal ttcex_ctrl has never been used. # Warning: [45730]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 369: signal ttcex_status[9:0] has no drivers, will be treated as don't care. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 396: signal tana_trg_mask[31] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 416: signal l1m_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 417: signal l2m_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 418: signal sod_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 419: signal eod_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 422: signal l1_message_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 423: signal l1_message_rdy_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 425: signal l2r_message_ttcrx has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 447: signal coinc_cnt_ctrl[31:2] has never been used. # Warning: [45730]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/cbb_top.vhd", line 449: signal ac_short[1:0] has no drivers, will be treated as don't care. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/sm_adc78h89.vhd", line 26: Input port din[31:3] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/ds_top.vhd", line 103: signal read_reg(4 to 8) has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/sfp_read.vhd", line 16: Input port din[31:3] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/adc2scsn.vhd", line 218: signal bus_addr[11:4] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 34: Input port scmd_data[31] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 34: Input port scmd_data[29:28] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 34: Input port scmd_data[3:0] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 37: Input port jcmd_data[31:12] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 37: Input port jcmd_data[3:0] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 431: signal s_rxdf_q[33] has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/iddr2.vhd", line 5: Input port CE has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/iddr2.vhd", line 6: Input port R has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/iddr2.vhd", line 7: Input port S has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/iddr2.vhd", line 9: Input port C1 has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/oddr2.vhd", line 5: Input port CE has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/oddr2.vhd", line 6: Input port R has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/oddr2.vhd", line 7: Input port S has never been used. # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/cores/oddr2.vhd", line 9: Input port C1 has never been used. # Info: [40000]: FSM: Removing state for un-assigned literal 0101 # Info: [45144]: Extracted FSM in module work.channelB_reg(arch), with state variable = prev_iac_addr[3:0], async set/reset state(s) = (none), number of states = 12. # Info: [45144]: Re-encoding 12 state FSM as "onehot". # Info: [45144]: FSM: State encoding table. # Info: [40000]: FSM: Index Literal Encoding # Info: [40000]: FSM: 0 0100 000000000001 # Info: [40000]: FSM: 1 ---- ------------ # Info: [40000]: FSM: 2 0000 000000000100 # Info: [40000]: FSM: 3 0001 000000001000 # Info: [40000]: FSM: 4 0010 000000010000 # Info: [40000]: FSM: 5 0011 000000100000 # Info: [40000]: FSM: 6 0110 000001000000 # Info: [40000]: FSM: 7 0111 000010000000 # Info: [40000]: FSM: 8 1000 000100000000 # Info: [40000]: FSM: 9 1001 001000000000 # Info: [40000]: FSM: 10 1010 010000000000 # Info: [40000]: FSM: 11 1011 100000000000 # Warning: [45766]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 335: FSM: Comparator b/w rtlc2n118 and unreachable state(s) will always be false. # Warning: [45766]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 430: FSM: Comparator b/w rtlc2n118 and unreachable state(s) will always be false. # Info: [44508]: Module work.pll40_40d_80(DEF_ARCH): Compiling... # Info: [44508]: Module work.clock_gen(behav){generic map (rst_width => 32)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/clock_gen.vhd", line 101: Macro Modgen_Counter "counter_up_aclear_clock_cnt_en_0_6" inferred for node "rst_cnt". # Info: [44508]: Module work.mcm_nw_pl(structural){generic map (len => 1)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_pl.vhd", line 0: Macro Modgen_Counter "counter_dn_sload_aset_clock_cnt_en_0_6" inferred for node "count_to". # Info: [44508]: Module work.mcm_nw_inbuf(structural){generic map (BUFSIZ => 69 BUFHALF => 4 COUNTER => 7)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_inbuf.vhd", line 133: Macro Modgen_Counter "counter_up_sclear_aclear_clock_cnt_en_0_7" inferred for node "bitcounter". # Info: [44508]: Module work.mcm_nw_outbuf(structural){generic map (BUFSIZ => 69 COUNTER => 7)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_outbuf.vhd", line 133: Macro Modgen_Counter "counter_up_sclear_aclear_clock_cnt_en_0_7" inferred for node "bitcounter". # Info: [44508]: Module work.mcm_nw_timer(structural){generic map (count_range => 4 event_on => 2)}: Compiling... # Info: [44508]: Module work.mcm_nw_destuffing(structural){generic map (stuff_length => 7)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_destuffing.vhd", line 78: Macro Modgen_Counter "counter_up_sclear_clock_cnt_en_0_3" inferred for node "counter". # Info: [44508]: Module work.hamm34enc67(a){generic map (Nbits => 4)}: Compiling... # Info: [44508]: Module work.hamm67dec34(a){generic map (Nbits => 4)}: Compiling... # Info: [44508]: Module work.hamm_reg(a){generic map (Nbits => 4 Init_value => 0 Bypass => 0)}: Compiling... # Info: [44508]: Module work.mcm_nw_bittiming(structural){generic map (timing_count_range => 4 timing_recv_on => 2 stuff_length => 7 sync_len => 7 sync_bits => 2)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_bittiming.vhd", line 0: Macro Modgen_Counter "counter_dn_sload_sclear_clock_clk_en_0_3" inferred for node "sync_counter". # Info: [44508]: Module work.mcm_nw_timer(structural){generic map (count_range => 4 event_on => 0)}: Compiling... # Info: [44508]: Module work.mcm_nw_timer(structural){generic map (count_range => 63 event_on => 63)}: Compiling... # Info: [44508]: Module work.mcm_nw_stuffing(structural){generic map (stuff_length => 7)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_stuffing.vhd", line 78: Macro Modgen_Counter "counter_up_sclear_aclear_clock_clk_en_0_3" inferred for node "state". # Info: [44508]: Module work.hamm34enc67(a){generic map (Nbits => 3)}: Compiling... # Info: [44508]: Module work.hamm67dec34(a){generic map (Nbits => 3)}: Compiling... # Info: [44508]: Module work.hamm_reg(a){generic map (Nbits => 3 Init_value => 0 Bypass => 0)}: Compiling... # Info: [44508]: Module work.mcm_nw_sendtiming(structural){generic map (timing_count_range => 4 stuff_length => 7 timing_sleep_length => 63)}: Compiling... # Info: [44508]: Module work.mcm_nw_dll(structural){generic map (timing_count_range => 4 timing_recv_on => 2 stuff_length => 7 timing_sleep_length => 63 BUFSIZ => 69 BUFHALF => 4 COUNTER => 7)}: Compiling... # Info: [44508]: Module work.mcm_nw_nwsl(structural): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/hamm_reg.vhd", line 0: Macro Add_Sub "M_RTLSIM_ADD_SUB_8" inferred for node "msb_inc". # Info: [44508]: Module work.mcm_nw_nwl(structural): Compiling... # Info: [44508]: Module work.mcm_nw_apl(structural): Compiling... # Warning: [45765]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 449: Ignoring Initial value for this signal/variable as initial value is not supported for the specified technology. # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/mcm/mcm_nw_apl.vhd", line 0: Macro Modgen_Counter "counter_dn_sload_aclear_clock_clk_en_cnt_en_0_6" inferred for node "waitcount". # Info: [44508]: Module work.mcm_network_interface(structural): Compiling... # Info: [44508]: Module work.sys_config(arc){generic map (trg_cnt_width => 12)}: Compiling... # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[0] with scsn_dout_com[0] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[1] with scsn_dout_com[1] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[2] with scsn_dout_com[2] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[3] with scsn_dout_com[3] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[4] with scsn_dout_com[4] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[5] with scsn_dout_com[5] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[6] with scsn_dout_com[6] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[7] with scsn_dout_com[7] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[8] with scsn_dout_com[8] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[9] with scsn_dout_com[9] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[10] with scsn_dout_com[10] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[11] with scsn_dout_com[11] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[12] with scsn_dout_com[12] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[13] with scsn_dout_com[13] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[14] with scsn_dout_com[14] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[15] with scsn_dout_com[15] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[16] with scsn_dout_com[16] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[17] with scsn_dout_com[17] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[18] with scsn_dout_com[18] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[19] with scsn_dout_com[19] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[20] with scsn_dout_com[20] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[21] with scsn_dout_com[21] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[22] with scsn_dout_com[22] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[23] with scsn_dout_com[23] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[24] with scsn_dout_com[24] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[25] with scsn_dout_com[25] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[26] with scsn_dout_com[26] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[27] with scsn_dout_com[27] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[28] with scsn_dout_com[28] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[29] with scsn_dout_com[29] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[30] with scsn_dout_com[30] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 290: Sharing register scsn_dout_r[31] with scsn_dout_com[31] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[0] with scsn_addr_com[0] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[1] with scsn_addr_com[1] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[2] with scsn_addr_com[2] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[3] with scsn_addr_com[3] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[4] with scsn_addr_com[4] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[5] with scsn_addr_com[5] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[6] with scsn_addr_com[6] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[7] with scsn_addr_com[7] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[8] with scsn_addr_com[8] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[9] with scsn_addr_com[9] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[10] with scsn_addr_com[10] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/sys_config.vhd", line 271: Sharing register scsn_addr_ta[11] with scsn_addr_com[11] # Info: [44508]: Module work.cb_ac_sample(oversample160): Compiling... # Info: [44508]: Module work.busy(behav): Compiling... # Info: [44508]: Module work.ram4k9_actel(a){generic map (piperA => false piperB => false Na_A => 9 Nd_A => 8 Na_B => 11 Nd_B => 2)}: Compiling... # Info: [44508]: Module work.lut_8k_2(a){generic map (piperA => false piperB => false)}: Compiling... # Info: [44508]: Module work.trg_lut(behav): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/trg_lut.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_clock_0_9" inferred for node "clr_addr". # Info: [44508]: Module work.pt_align(behav){generic map (no_inputs => 15 no_delays => 8)}: Compiling... # Info: [44508]: Module work.trg_emulator(behav){generic map (cnt_width => 12)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_emulator.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aset_clock_cnt_en_0_12" inferred for node "cnt_after_ptrg". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_emulator.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aset_clock_clk_en_cnt_en_0_12" inferred for node "cnt_delay_l0". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_emulator.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aset_clock_clk_en_cnt_en_0_12" inferred for node "cnt_delay_l1". # Info: [44508]: Module work.trg_generator(behav){generic map (cnt_width => 12)}: Compiling... # Info: [44508]: Module work.psrg(a){generic map (N => 32)}: Compiling... # Info: [44508]: Module work.random_pulser(behav): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/random_pulser.vhd", line 67: Macro Modgen_Counter "counter_up_sload_clock_0_10" inferred for node "kn". # Info: [44508]: Module work.ttcex_out(behav): Compiling... # Info: [44508]: Module work.shiftreg_piso(behav){generic map (width => 22)}: Compiling... # Info: [44508]: Module work.ctp_tin(behav){generic map (signature(6 downto 0) => 53)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ctp_tin.vhd", line 53: Macro Modgen_Counter "counter_up_sclear_clock_0_10" inferred for node "cnt_sign". # Info: [44508]: Module work.serialb_com(arc){generic map (include_hamming => true)}: Compiling... # Info: [44508]: Module work.channelB_reg(arch): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 177: Macro Modgen_Counter "counter_up_sclear_clock_cnt_en_16_8" inferred for node "l1_swc_cnt". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 181: Macro Modgen_Counter "counter_up_sclear_clock_cnt_en_0_8" inferred for node "l1_roc_e_cnt". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 185: Macro Modgen_Counter "counter_up_sclear_clock_cnt_en_8_8" inferred for node "l1_roc_f_cnt". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 189: Macro Modgen_Counter "counter_up_sclear_clock_cnt_en_24_8" inferred for node "l2_swc_cnt". # Info: [44508]: Module work.ttc_receiver_top(arc): Compiling... # Info: [44508]: Module work.bc_cnt(behav): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/bc_cnt.vhd", line 50: Macro Modgen_Counter "counter_up_sload_sclear_clock_0_12" inferred for node "bc_i". # Info: [44508]: Module work.ram4k9_actel(a){generic map (piperA => false piperB => false Na_A => 9 Nd_A => 8 Na_B => 12 Nd_B => 1)}: Compiling... # Info: [44508]: Module work.ram4k_w8_r1(struct): Compiling... # Info: [44508]: Module work.bc_trigger(behav){generic map (no_bcmasks => 2)}: Compiling... # Info: [44508]: Module work.del_coinc_cnt_en(behav){generic map (depth => 8 ref_offset => 6)}: Compiling... # Info: [44508]: Module work.dp_sram_actel(a){generic map (piper => false Na_w => 8 Na_r => 8 Nd_w => 18 Nd_r => 18)}: Compiling... # Info: [44508]: Module work.dp_sram_128x54(a){generic map (piper => false)}: Compiling... # Info: [44508]: Module work.ram_cnt_cnt(behav){generic map (N => 7)}: Compiling... # Info: [44508]: Module work.ram_cnt(behav){generic map (width_addr => 7 width_ram => 54 width_fast => 8)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 0: Macro Modgen_Counter "counter_up_aclear_clock_0_7" inferred for node "addr". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 0: Macro Selcounter "selcounter_8_8_8_0_1_flatten" inferred for node "clr_capt_cnt". # Info: [44508]: Module work.dp_sram_actel(a){generic map (piper => false Na_w => 9 Na_r => 9 Nd_w => 8 Nd_r => 8)}: Compiling... # Info: [44508]: Module work.dp_sram_512x32(a){generic map (piper => false)}: Compiling... # Info: [44508]: Module work.timing_analyzer(behav): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/timing_analyzer.vhd", line 0: Macro Modgen_Counter "counter_dn_sload_aset_clock_clk_en_4_9" inferred for node "cnt_posttrg". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/timing_analyzer.vhd", line 0: Macro Modgen_Counter "counter_up_aclear_clock_cnt_en_0_9" inferred for node "addr_counter". # Info: [44508]: Module work.ucrc_par(rtl){generic map (POLYNOMIAL(0 to 31) => 04c11db7 INIT_VALUE(0 to 31) => 00000000 DATA_WIDTH => 32 SYNC_RESET => 1)}: Compiling... # Info: [44508]: Module work.cbbr_iserdes(behv): Compiling... # Info: [44508]: Module work.cbbr_top(behv){generic map (clkratio => 10)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd", line 155: Macro Modgen_Counter "counter_up_sclear_aclear_clock_clk_en_0_4" inferred for node "sample_cnt". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd", line 256: Macro Modgen_Counter "counter_up_sclear_aclear_clock_cnt_en_0_5" inferred for node "wordcounter". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd", line 318: Macro Modgen_Counter "counter_up_sclear_aclear_clock_cnt_en_0_32" inferred for node "packetcounter". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/tlmureceiver/cbbr_top.vhd", line 332: Macro Modgen_Counter "counter_up_sclear_aclear_clock_cnt_en_0_32" inferred for node "crcerrorcounter". # Info: [44508]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}: Compiling... # Info: [44508]: Module work.adc78h89(a){generic map (iCLK => false iCNV => false iDIN => false iDOU => false Nbit => 16 Ndiv => 40)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/adc78h89.vhd", line 137: Macro Add_Sub "M_RTLSIM_ADD_SUB_4" inferred for node "bits". # Info: [44508]: Module work.relax(a){generic map (Nd => 12 Nf => 0 Ns => 1 Na => 19)}: Compiling... # Info: [44508]: Module work.sm_adc78h89(a){generic map (iCLK => false iCNV => false iDIN => false iDOU => false Nstep => 1 Nacc => 19 Ndiv => 40)}: Compiling... # Info: [44508]: Module work.clk_div(a){generic map (Nd => 40)}: Compiling... # Info: [44508]: Module work.program(a): Compiling... # Info: [44508]: Module work.timeslots(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}: Compiling... # Info: [44508]: Module work.byteslots(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}: Compiling... # Info: [44508]: Module work.ds_top(a){generic map (Nrst0 => 512 Nrsts => 100 Nrst1 => 512 Nwr0 => 80 Nwr1 => 8 Nrd => 2 Ntts => 90 Nrds => 8)}: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/ds_top.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_clk_en_cnt_en_0_5" inferred for node "paddr". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/ds_top.vhd", line 0: Macro Modgen_Counter "counter_dn_sload_aclear_clock_clk_en_cnt_en_0_20" inferred for node "counter". # Info: [44508]: Module work.sfp_read(a): Compiling... # Info: [44508]: Module work.siu_io(a): Compiling... # Info: [44508]: Module work.mux41nbit(a){generic map (Nbit => 32)}: Compiling... # Info: [44508]: Module work.adc2scsn(a): Compiling... # Info: [44508]: Module work.rx_in(SYN): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_in.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aset_clock_cnt_en_0_4" inferred for node "rxlos_hold". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_in.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aset_clock_0_5" inferred for node "idle_count". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_in.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_cnt_en_0_17" inferred for node "v_por_timer". # Info: [44508]: Module work.crc16(SYN): Compiling... # Info: [44508]: Module work.rx_crc(SYN): Compiling... # Info: [44508]: Module work.rx_cmd(SYN): Compiling... # Info: [44508]: Module work.rx_data(SYN): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_data.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_clk_en_cnt_en_0_9" inferred for node "dfr_count". # Info: [44508]: Module work.lm_siu(SYN): Compiling... # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 90: Sharing register ot_lon with sd_enable # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 90: Sharing register tx_dxdata[2] with tx_dxdata[3] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 90: Sharing register rx_present_fsm[1] (Encoded FSM State Variable for rx_present) with tx_dxdata[10] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 90: Sharing register rx_present_fsm[1] (Encoded FSM State Variable for rx_present) with tx_dxdata[11] # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_9" inferred for node "srst_timer". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_11" inferred for node "por_timer". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_8" inferred for node "sync_timer". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_19" inferred for node "poff_timer". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_5" inferred for node "sdlos_filt". # Info: [44508]: Module work.cm_siu(SYN): Compiling... # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Sharing register txst_data[0] with txst_data[2] # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_21" inferred for node "rwhwid_timer". # Info: [44508]: Module work.framing(SYN): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/framing.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_12" inferred for node "wd_timer". # Info: [44508]: Module work.fee_if(SYN): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_clk_en_cnt_en_0_21" inferred for node "fstrd_timer". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd", line 0: Macro Selcounter "selcounter_20_20_20_0_1_flatten" inferred for node "dtstw_count". # Info: [44508]: Module work.i2c_if(SYN): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/i2c_if.vhd", line 0: Macro Modgen_Counter "counter_up_sclear_aclear_clock_0_9" inferred for node "scl_timer". # Info: [44508]: Module work.rxdf_core(DEF_ARCH): Compiling... # Info: [44508]: Module work.rxd_fifo(SYN): Compiling... # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rxd_fifo.vhd", line 106: Sharing register read_present_fsm[0] (Encoded FSM State Variable for read_present) with fetch # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rxd_fifo.vhd", line 106: Sharing register read_present_fsm[1] (Encoded FSM State Variable for read_present) with read_ena # Info: [44508]: Module work.txdf_core(DEF_ARCH): Compiling... # Info: [44508]: Module work.txd_fifo(SYN): Compiling... # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/txd_fifo.vhd", line 90: Sharing register read_present_fsm[0] (Encoded FSM State Variable for read_present) with fetch # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/txd_fifo.vhd", line 90: Sharing register read_present_fsm[1] (Encoded FSM State Variable for read_present) with read_ena # Info: [44508]: Module work.pm_if(SYN): Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/pm_if.vhd", line 0: Macro Selcounter "selcounter_11_11_11_0_1_flatten" inferred for node "clkdiv_cnt". # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/pm_if.vhd", line 0: Macro Modgen_Counter "counter_up_aclear_clock_cnt_en_0_4" inferred for node "bit_cnt". # Info: [44508]: Module work.parity_gen(SYN): Compiling... # Info: [44508]: Module work.parity_chk(SYN): Compiling... # Info: [44508]: Module work.siu_top_core(SYN): Compiling... # Warning: [45765]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 707: Ignoring Initial value for this signal/variable as initial value is not supported for the specified technology. # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[0] with s_rxpargen_d[16] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[1] with s_rxpargen_d[17] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[2] with s_rxpargen_d[18] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[3] with s_rxpargen_d[19] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[4] with s_rxpargen_d[20] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[5] with s_rxpargen_d[21] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[6] with s_rxpargen_d[22] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[7] with s_rxpargen_d[23] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[8] with s_rxpargen_d[24] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[9] with s_rxpargen_d[25] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[10] with s_rxpargen_d[26] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[11] with s_rxpargen_d[27] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[12] with s_rxpargen_d[28] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[13] with s_rxpargen_d[29] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[14] with s_rxpargen_d[30] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1054: Sharing register s_rxpargen_d[15] with s_rxpargen_d[31] # Info: [44812]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 538: Sharing register led1 with led2 # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 0: Macro Selcounter "selcounter_24_24_24_0_1_flatten" inferred for node "blink_timer". # Info: [44508]: Module work.OBUFDS(a): Compiling... # Info: [44508]: Module work.IBUF(a): Compiling... # Info: [44508]: Module work.iddr2(a): Compiling... # Info: [44508]: Module work.oddr2(a): Compiling... # Info: [45193]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_generator.vhd", line 20: Net pt_ctp_emu is unused after optimization # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/trg_generator.vhd", line 82: Optimizing state bit(s) error to constant 0 # Info: [45252]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/serialb_com.vhd", line 263: Inferred rom instance 'rtlcI6' of type 'rom_2_6_64_382'. # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/serialb_com.vhd", line 423: Optimizing state bit(s) test_data[0] to constant 1 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/ttcreceiver/channelB_reg.vhd", line 221: Optimizing state bit(s) prev_iac_addr[1] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/bc_cnt.vhd", line 36: Optimizing state bit(s) bc_l0[11:0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/bc_cnt.vhd", line 36: Optimizing state bit(s) bc_msg[11:0] to constant 0 # Info: [45193]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 22: Net scsn_addr[15:12] is unused after optimization # Info: [45193]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/../../CB-B/trunk/src/misc/ram_cnt.vhd", line 22: Net scsn_addr[9:7] is unused after optimization # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[0]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[1]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[2]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[3]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[4]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[5]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[6]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[7]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[8]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance sys_config0, Net(s) ttcex_status[9]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance cba_coinc_cnt, Net(s) sig: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance cbc_coinc_cnt, Net(s) sig: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance tim_ana, Net(s) signals[4]: This input has no drivers, driving zero. # Warning: [45438]: Module work.cbb_top(struct){generic map (no_bcmasks => 2 trg_cnt_width => 12)}, Instance tim_ana, Net(s) signals[10]: This input has no drivers, driving zero. # Info: [45252]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/timeslots.vhd", line 65: Inferred rom instance 'rtlcI7' of type 'rom_5_6_64_384'. # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/timeslots.vhd", line 103: Optimizing state bit(s) dout to constant 0 # Info: [45252]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/ds_top.vhd", line 129: Inferred rom instance 'rtlcI8' of type 'rom_4_7_128_386'. # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/ADC/sfp_read.vhd", line 33: Optimizing state bit(s) dout[31:5] to constant 0 # Info: [45193]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/rx_in.vhd", line 28: Net rxd[15:8] is unused after optimization # Info: [45193]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 36: Net rx_dxdata[15:12] is unused after optimization # Info: [45193]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 36: Net rx_dxdata[9:4] is unused after optimization # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 90: Optimizing state bit(s) tx_dxdata[13:12] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/lm_siu.vhd", line 90: Optimizing state bit(s) tx_dxdata[9:8] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) txst_data[0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_ctstw[31:12] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_ctstw[7:6] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_ctstw[4:2] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_ctstw[0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_jtstw[30:12] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_jtstw[7:6] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_jtstw[2:0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_siustw[5:2] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_siustw[0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_hwidstw[30] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_hwidstw[28] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_hwidstw[7] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_hwidstw[4:2] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_hwidstw[0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[31] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[29:26] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[24] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[22] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[19] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[17] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[15] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[13] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[4:2] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_fwidstw[0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_pmvstw[31:25] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_pmvstw[7] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_pmvstw[3:2] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_pmvstw[0] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 263: Optimizing state bit(s) v_txst_d0[5] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_txst_d1[31] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_txst_d2[30] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_txst_d3[30] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_txst_d4[30] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/cm_siu.vhd", line 115: Optimizing state bit(s) v_txst_d5[31] to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/fee_if.vhd", line 134: Optimizing state bit(s) err_levnt to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/i2c_if.vhd", line 95: Optimizing state bit(s) i2c_error to constant 0 # Info: [45309]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/SIU/siu_top_core.vhd", line 1067: Optimizing state bit(s) s_rxdf_d[33] to constant 0 # Info: [44846]: Rebalanced Expression Tree... # Info: [44842]: Compilation successfully completed. # Info: [44841]: Counter Inferencing === Detected : 67, Inferred (Modgen/Selcounter/AddSub) : 48 (42 / 4 / 2), AcrossDH (Merged/Not-Merged) : (0 / 1), Not-Inferred (Acrossdh/Attempted) : (0 / 8), Local Vars : 11 === # Info: [44856]: Total lines of RTL compiled: 30979. # Info: [44835]: Total CPU time for compilation: 10.0 secs. # Info: [40000]: RTLCompiler, Release RTLC-Precision 2010a.31 # Info: [40000]: Last compiled on Oct 22 2010 16:35:46 # Info: [44512]: Initializing... # Info: [44522]: Root Module top: Pre-processing... # Warning: [45729]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/TOP_PAD/top.v", line 266: LED_SIU_i[1:2] has never been used. # Info: [44508]: Module IBUFDS: Compiling... # Info: [44508]: Module OBUF: Compiling... # Info: [44523]: Root Module top: Compiling... # Info: [44838]: "/home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/src/TOP_PAD/top.v", line 649: Macro Modgen_Counter "counter_up_sclear_clock_0_27" inferred for node "led_cnt". # Info: [44842]: Compilation successfully completed. # Info: [44841]: Counter Inferencing === Detected : 1, Inferred (Modgen/Selcounter/AddSub) : 1 (1 / 0 / 0), AcrossDH (Merged/Not-Merged) : (0 / 0), Not-Inferred (Acrossdh/Attempted) : (0 / 0), Local Vars : 0 === # Info: [44856]: Total lines of RTL compiled: 644. # Info: [44835]: Total CPU time for compilation: 0.0 secs. # Info: [44513]: Overall running time for compilation: 11.0 secs. # Info: [649]: Current working directory: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/precision_A3PE3000. # Info: [9085]: Disconnecting net:i_cbb.trg_lut_inst.pattern_match_tof from port:bbuf_SDA_ID.ix1.out. Net is multiply driven by a disabled tristate as well as by instance:i_cbb.trg_lut_inst.ix121. # Info: [9085]: Disconnecting net:i_cbb.trg_lut_inst.pattern_match_cba from port:bbuf_SDA_ID.ix1.out. Net is multiply driven by a disabled tristate as well as by instance:i_cbb.trg_lut_inst.ix123. # Info: [9085]: Disconnecting net:i_cbb.trg_lut_inst.pattern_match_cbc from port:bbuf_SDA_ID.ix1.out. Net is multiply driven by a disabled tristate as well as by instance:i_cbb.trg_lut_inst.ix125. # Info: [15325]: Doing rtl optimizations. # Info: [652]: Finished compiling design. # Info: Actel # Info: Actel # Info: Actel # Info: Actel # Info: Actel # Info: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/precision_A3PE3000/precision_rtl.sdc # Info: [649]: Current working directory: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/precision_A3PE3000. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.clock_gen_32.behav_unfold_2343. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_6. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.mcm_nw_bittiming_4_2_7_7_2.structural_unfold_2. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_3_0_0.a_unfold_4. # Info: [4554]: 4 Instances are flattened in hierarchical block .work.mcm_nw_sendtiming_4_7_63.structural_unfold_1. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_7. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.mcm_nw_bittiming_4_2_7_7_2.structural_unfold_3. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_3_0_0.a_unfold_5. # Info: [4554]: 4 Instances are flattened in hierarchical block .work.mcm_nw_sendtiming_4_7_63.structural_unfold_2. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_8. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_nwsl.structural_unfold_1. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_9. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_nwsl.structural_unfold_2. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_3_0_0.a_unfold_2. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_nwl.structural_unfold_2946_0. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_1. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_apl.structural. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.mcm_network_interface.structural_unfold_2295. # Info: [4554]: 4 Instances are flattened in hierarchical block .work.lut_8k_2_0_0.a_unfold_1715. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.trg_lut.behav_unfold_2094. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.random_pulser.behav. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.ctp_tin_l6_r0_53.behav_unfold_1. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.ctp_tin_l6_r0_53.behav. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.ram4k_w8_r1.struct_unfold_1. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.ram4k_w8_r1.struct. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.bc_trigger_2.behav_unfold_2277. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.dp_sram_128x54_0.a_unfold_1. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.dp_sram_128x54_0.a_unfold_1655_0. # Info: [4554]: 61 Instances are flattened in hierarchical block .work.ram_cnt_7_54_8.behav_unfold_2065. # Info: [4554]: 4 Instances are flattened in hierarchical block .work.dp_sram_512x32_0.a_unfold_1995. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.timing_analyzer.behav_unfold_1673. # Info: [4554]: 8 Instances are flattened in hierarchical block .work.cbbr_top_10.behv_unfold_1770. # Info: [4554]: 7 Instances are flattened in hierarchical block .work.cbb_top_2_12.struct_unfold_1189. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_2. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.mcm_nw_bittiming_4_2_7_7_2.structural. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_3_0_0.a. # Info: [4554]: 4 Instances are flattened in hierarchical block .work.mcm_nw_sendtiming_4_7_63.structural_unfold_3. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_4. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.mcm_nw_bittiming_4_2_7_7_2.structural_unfold_2451. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_3_0_0.a_unfold_1. # Info: [4554]: 4 Instances are flattened in hierarchical block .work.mcm_nw_sendtiming_4_7_63.structural. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_nwsl.structural_unfold_3. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_5. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_nwsl.structural_unfold_1847_0. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_3_0_0.a_unfold_3. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_nwl.structural_unfold_1. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.hamm_reg_4_0_0.a_unfold_3. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.mcm_nw_apl.structural_unfold_2926. # Info: [4554]: 2 Instances are flattened in hierarchical block .work.mcm_network_interface.structural_unfold_2067. # Info: [4554]: 3 Instances are flattened in hierarchical block .work.adc2scsn.a. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.rxd_fifo.SYN_unfold_1620. # Info: [4554]: 1 Instances are flattened in hierarchical block .work.txd_fifo.SYN. # Info: [4554]: 6 Instances are flattened in hierarchical block .work.siu_top_core.SYN_unfold_804. # Info: [4554]: 109 Instances are flattened in hierarchical block .work.top.INTERFACE. # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_12_fastest_false_12297 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_32_fastest_false_18077 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [2515]: Resolving function gt with module generator modgen_GT_9_fastest_false_28577 from file /usr/local/bin/Mgc_home/pkgs/psr/modgen/proasic3e.vhd # Info: [2531]: Replacing cell:modgen_GT____32719(view:) # Info: [15002]: Optimizing design view:.work.sys_config_12.arc_unfold_1796 # Info: [15002]: Optimizing design view:.work.trg_lut.behav_unfold_2094 # Info: [15002]: Optimizing design view:.work.pt_align_15_8.behav_unfold_2139 # Info: [15002]: Optimizing design view:.work.trg_emulator_12.behav # Info: [15002]: Optimizing design view:.work.trg_generator_12.behav_unfold_1686 # Info: [15002]: Optimizing design view:.work.random_pulser.behav # Info: [15002]: Optimizing design view:.work.ctp_tin_l6_r0_53.behav # Info: [15002]: Optimizing design view:.work.bc_cnt.behav_unfold_1974 # Info: [15002]: Optimizing design view:.work.bc_trigger_2.behav_unfold_2277 # Info: [15002]: Optimizing design view:.work.ram_cnt_cnt_7.behav # Info: [15002]: Optimizing design view:.work.ram_cnt_cnt_7.behav_unfold_2659_0 # Info: [15002]: Optimizing design view:.work.ram_cnt_7_54_8.behav_unfold_2065 # Info: [15002]: Optimizing design view:.work.timing_analyzer.behav_unfold_1673 # Info: [15002]: Optimizing design view:.work.ucrc_par_l0_r31_04c11db7_l0_r31_00000000_32_1.rtl_unfold_1722 # Info: [15002]: Optimizing design view:.work.cbbr_top_10.behv_unfold_1770 # Info: [15002]: Optimizing design view:.work.mcm_nw_nwl.structural_unfold_2946_0 # Info: [15002]: Optimizing design view:.work.mcm_nw_apl.structural # Info: [15002]: Optimizing design view:.work.serialb_com_1.arc_unfold_2357 # Info: [15002]: Optimizing design view:.work.channelB_reg.arch_unfold_2453 # Info: [15002]: Optimizing design view:.work.cbb_top_2_12.struct_unfold_1189 # Info: [15002]: Optimizing design view:.work.adc78h89_0_0_0_0_16_40.a # Info: [15002]: Optimizing design view:.work.relax_12_0_1_19.a_unfold_1 # Info: [15002]: Optimizing design view:.work.relax_12_0_1_19.a # Info: [15002]: Optimizing design view:.work.sm_adc78h89_0_0_0_0_1_19_40.a_unfold_920 # Info: [15002]: Optimizing design view:.work.program.a_unfold_1693 # Info: [15002]: Optimizing design view:.work.timeslots_512_100_512_80_8_2_90_8.a_unfold_1883 # Info: [15002]: Optimizing design view:.work.byteslots_512_100_512_80_8_2_90_8.a # Info: [15002]: Optimizing design view:.work.ds_top_512_100_512_80_8_2_90_8.a_unfold_1331 # Info: [15002]: Optimizing design view:.work.siu_io.a # Info: [15002]: Optimizing design view:.work.mux41nbit_32.a_unfold_885 # Info: [15002]: Optimizing design view:.work.mcm_nw_nwsl.structural_unfold_1847_0 # Info: [15002]: Optimizing design view:.work.mcm_nw_apl.structural_unfold_2926 # Info: [15002]: Optimizing design view:.work.mcm_nw_bittiming_4_2_7_7_2.structural # Info: [15002]: Optimizing design view:.work.mcm_nw_inbuf_69_4_7.structural_unfold_2439_0 # Info: [15002]: Optimizing design view:.work.mcm_nw_outbuf_69_7.structural_unfold_2445_0 # Info: [15002]: Optimizing design view:.work.mcm_nw_bittiming_4_2_7_7_2.structural_unfold_2451 # Info: [15002]: Optimizing design view:.work.mcm_nw_sendtiming_4_7_63.structural # Info: [15002]: Optimizing design view:.work.adc2scsn.a # Info: [15002]: Optimizing design view:.work.crc16.SYN_unfold_1 # Info: [15002]: Optimizing design view:.work.rx_crc.SYN # Info: [15002]: Optimizing design view:.work.rx_cmd.SYN_unfold_1662 # Info: [15002]: Optimizing design view:.work.rx_data.SYN # Info: [15002]: Optimizing design view:.work.lm_siu.SYN_unfold_1674 # Info: [15002]: Optimizing design view:.work.cm_siu.SYN_unfold_1665 # Info: [15002]: Optimizing design view:.work.crc16.SYN # Info: [15002]: Optimizing design view:.work.framing.SYN_unfold_1732 # Info: [15002]: Optimizing design view:.work.fee_if.SYN_unfold_1378 # Info: [15002]: Optimizing design view:.work.i2c_if.SYN_unfold_1613 # Info: [15002]: Optimizing design view:.work.pm_if.SYN # Info: [15002]: Optimizing design view:.work.siu_top_core.SYN_unfold_804 # Info: [15002]: Optimizing design view:.work.top.INTERFACE # Info: -- Quick flow done # Info: [8041]: Using Global Buffer MUXTILE for PLL Inst : instance:i_cbb.clock_generation_ipll_Core and Port : port:.i_cbb.clock_generation.ipll.Core.GLA # Info: [8041]: Using Global Buffer MUXTILE for PLL Inst : instance:i_cbb.clock_generation_ipll_Core and Port : port:.i_cbb.clock_generation.ipll.Core.GLC # Info: [8042]: No Global Buffer left for PLL Inst : instance:i_cbb.clock_generation_ipll_Core and Port : port:.i_cbb.clock_generation.ipll.Core.GLB PnR may give error # Info: [7004]: Starting retiming program ... # Info: [7010]: User constraints were met before retiming. Using tighter constraints may achieve better results # Info: [7005]: Ending retiming program ... # Info: [8027]: Starting DRC check ... # Info: [8028]: End DRC check ... # Info: [12045]: Starting timing reports generation... # Info: [12046]: Timing reports generation done. # Info: [12047]: POST-SYNTHESIS TIMING REPORTS ARE ESTIMATES AND SHOULD NOT BE RELIED ON TO MAKE QoR DECISIONS. For accurate timing information, please run place-and-route (P&R) and review P&R generated timing reports. # Info: [3027]: Writing file: /home/angelov/pretrigger.svn/vhdl/PIMDDL/trunk/precision_A3PE3000/top.edf. # Info: [652]: Finished synthesizing design. # Info: [11019]: Total CPU time for synthesis: 2 m 26.1 s secs. # Info: [11020]: Overall running time for synthesis: 2 m 32.0 s secs.