Timing Report Min Delay Analysis SmartTime Version v9.1 SP3 Actel Corporation - Actel Designer Software Release v9.1 SP3 (Version 9.1.3.4) Copyright (c) 1989-2010 Date: Thu Aug 11 22:21:06 2011 Design: actel_par_A3PE3000 Family: ProASIC3E Die: A3PE3000 Package: 208 PQFP Temperature: COM Voltage: COM Speed Grade: -2 Design State: Post-Layout Data source: Silicon verified Min Operating Condition: BEST Max Operating Condition: WORST Using Enhanced Min Delay Analysis Scenario for Timing Analysis: Primary ----------------------------------------------------- SUMMARY Clock Domain: SIU_RXCLK Period (ns): 6.264 Frequency (MHz): 159.642 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 0.612 External Hold (ns): 0.964 Min Clock-To-Out (ns): N/A Max Clock-To-Out (ns): N/A Clock Domain: SIU_TXCLK Period (ns): 7.517 Frequency (MHz): 133.032 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 8.999 External Hold (ns): 1.489 Min Clock-To-Out (ns): 3.536 Max Clock-To-Out (ns): 16.454 Clock Domain: i_SIU/reg_tx_clk_2:Q Period (ns): 8.289 Frequency (MHz): 120.642 Required Period (ns): 18.182 Required Frequency (MHz): 54.999 External Setup (ns): 7.079 External Hold (ns): -0.468 Min Clock-To-Out (ns): 5.921 Max Clock-To-Out (ns): 15.872 Clock Domain: i_adc/cdiv_reg_q:Q Period (ns): 12.222 Frequency (MHz): 81.820 Required Period (ns): 100.000 Required Frequency (MHz): 10.000 External Setup (ns): 3.387 External Hold (ns): -0.792 Min Clock-To-Out (ns): 5.294 Max Clock-To-Out (ns): 14.369 Clock Domain: i_cbb/clock_generation_ipll_Core:GLA Period (ns): 19.421 Frequency (MHz): 51.491 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): 8.303 External Hold (ns): 2.990 Min Clock-To-Out (ns): 5.765 Max Clock-To-Out (ns): 23.945 Clock Domain: i_cbb/clock_generation_ipll_Core:GLB Period (ns): 0.926 Frequency (MHz): 1079.914 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): 3.924 External Hold (ns): 0.674 Min Clock-To-Out (ns): 8.893 Max Clock-To-Out (ns): 15.347 Clock Domain: i_cbb/clock_generation_ipll_Core:GLC Period (ns): 6.657 Frequency (MHz): 150.218 Required Period (ns): 12.500 Required Frequency (MHz): 80.000 External Setup (ns): -7.554 External Hold (ns): 4.443 Min Clock-To-Out (ns): 10.866 Max Clock-To-Out (ns): 22.751 Clock Domain: CLK40p Period (ns): 2.860 Frequency (MHz): 349.650 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 5.304 Max Clock-To-Out (ns): 10.724 Input to Output Min Delay (ns): 4.464 Max Delay (ns): 14.068 END SUMMARY ----------------------------------------------------- Clock Domain SIU_RXCLK SET Register to Register Path 1 From: i_SIU/reg_s_rxdf_d(34):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD16 Delay (ns): 0.403 Slack (ns): 0.230 Arrival (ns): 2.942 Required (ns): 2.712 Hold (ns): 0.000 Path 2 From: i_SIU/RXDATA_INST/reg_rxdf_d(25):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD7 Delay (ns): 0.424 Slack (ns): 0.251 Arrival (ns): 2.963 Required (ns): 2.712 Hold (ns): 0.000 Path 3 From: i_SIU/RXDATA_INST/reg_rxdf_d(24):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD6 Delay (ns): 0.425 Slack (ns): 0.252 Arrival (ns): 2.964 Required (ns): 2.712 Hold (ns): 0.000 Path 4 From: i_SIU/RXDATA_INST/reg_rxdf_d(23):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD5 Delay (ns): 0.425 Slack (ns): 0.252 Arrival (ns): 2.964 Required (ns): 2.712 Hold (ns): 0.000 Path 5 From: i_SIU/RXDATA_INST/reg_rxdf_d(22):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD4 Delay (ns): 0.425 Slack (ns): 0.252 Arrival (ns): 2.964 Required (ns): 2.712 Hold (ns): 0.000 Path 6 From: i_SIU/RXDATA_INST/reg_rxdf_d(21):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD3 Delay (ns): 0.425 Slack (ns): 0.252 Arrival (ns): 2.964 Required (ns): 2.712 Hold (ns): 0.000 Path 7 From: i_SIU/RXDATA_INST/reg_rxdf_d(7):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD7 Delay (ns): 0.424 Slack (ns): 0.258 Arrival (ns): 2.941 Required (ns): 2.683 Hold (ns): 0.000 Path 8 From: i_SIU/RXDATA_INST/reg_rxdf_d(27):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD9 Delay (ns): 0.432 Slack (ns): 0.259 Arrival (ns): 2.971 Required (ns): 2.712 Hold (ns): 0.000 Path 9 From: i_SIU/reg_srst_pipe(1):CLK To: i_SIU/reg_srst_pipe(2):D Delay (ns): 0.357 Slack (ns): 0.262 Arrival (ns): 2.837 Required (ns): 2.575 Hold (ns): 0.000 Path 10 From: i_SIU/RXDATA_INST/reg_rxdf_d(14):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD14 Delay (ns): 0.431 Slack (ns): 0.265 Arrival (ns): 2.948 Required (ns): 2.683 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/reg_s_rxdf_d(34):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD16 data arrival time 2.942 data required time - 2.712 slack 0.230 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/reg_s_rxdf_d(34):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/reg_s_rxdf_d(34):Q (r) + 0.197 net: i_SIU/s_rxdf_d_34_ 2.942 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD16 (r) 2.942 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD16 2.712 data required time Expanded Path 2 From: i_SIU/RXDATA_INST/reg_rxdf_d(25):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD7 data arrival time 2.963 data required time - 2.712 slack 0.251 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/RXDATA_INST/reg_rxdf_d(25):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/RXDATA_INST/reg_rxdf_d(25):Q (r) + 0.218 net: i_SIU/s_rxdf_d_25_ 2.963 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD7 (r) 2.963 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD7 2.712 data required time Expanded Path 3 From: i_SIU/RXDATA_INST/reg_rxdf_d(24):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD6 data arrival time 2.964 data required time - 2.712 slack 0.252 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/RXDATA_INST/reg_rxdf_d(24):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/RXDATA_INST/reg_rxdf_d(24):Q (r) + 0.219 net: i_SIU/s_rxdf_d_24_ 2.964 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD6 (r) 2.964 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD6 2.712 data required time Expanded Path 4 From: i_SIU/RXDATA_INST/reg_rxdf_d(23):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD5 data arrival time 2.964 data required time - 2.712 slack 0.252 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/RXDATA_INST/reg_rxdf_d(23):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/RXDATA_INST/reg_rxdf_d(23):Q (r) + 0.219 net: i_SIU/s_rxdf_d_23_ 2.964 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD5 (r) 2.964 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD5 2.712 data required time Expanded Path 5 From: i_SIU/RXDATA_INST/reg_rxdf_d(22):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD4 data arrival time 2.964 data required time - 2.712 slack 0.252 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/RXDATA_INST/reg_rxdf_d(22):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/RXDATA_INST/reg_rxdf_d(22):Q (r) + 0.219 net: i_SIU/s_rxdf_d_22_ 2.964 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD4 (r) 2.964 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD4 2.712 data required time Expanded Path 6 From: i_SIU/RXDATA_INST/reg_rxdf_d(21):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD3 data arrival time 2.964 data required time - 2.712 slack 0.252 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/RXDATA_INST/reg_rxdf_d(21):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/RXDATA_INST/reg_rxdf_d(21):Q (r) + 0.219 net: i_SIU/s_rxdf_d_21_ 2.964 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD3 (r) 2.964 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD3 2.712 data required time Expanded Path 7 From: i_SIU/RXDATA_INST/reg_rxdf_d(7):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD7 data arrival time 2.941 data required time - 2.683 slack 0.258 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.392 net: SIU_RXCLK_cb 2.517 i_SIU/RXDATA_INST/reg_rxdf_d(7):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.723 i_SIU/RXDATA_INST/reg_rxdf_d(7):Q (r) + 0.218 net: i_SIU/s_rxdf_d_7_ 2.941 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD7 (r) 2.941 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.558 net: SIU_RXCLK_cb 2.683 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.683 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD7 2.683 data required time Expanded Path 8 From: i_SIU/RXDATA_INST/reg_rxdf_d(27):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD9 data arrival time 2.971 data required time - 2.712 slack 0.259 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.414 net: SIU_RXCLK_cb 2.539 i_SIU/RXDATA_INST/reg_rxdf_d(27):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.745 i_SIU/RXDATA_INST/reg_rxdf_d(27):Q (r) + 0.226 net: i_SIU/s_rxdf_d_27_ 2.971 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD9 (r) 2.971 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.587 net: SIU_RXCLK_cb 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.712 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_1_inst:WD9 2.712 data required time Expanded Path 9 From: i_SIU/reg_srst_pipe(1):CLK To: i_SIU/reg_srst_pipe(2):D data arrival time 2.837 data required time - 2.575 slack 0.262 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.355 net: SIU_RXCLK_cb 2.480 i_SIU/reg_srst_pipe(1):CLK (r) + 0.206 cell: ADLIB:DFN1P1 2.686 i_SIU/reg_srst_pipe(1):Q (r) + 0.151 net: i_SIU/srst_pipe_1_ 2.837 i_SIU/reg_srst_pipe(2):D (r) 2.837 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.450 net: SIU_RXCLK_cb 2.575 i_SIU/reg_srst_pipe(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 2.575 i_SIU/reg_srst_pipe(2):D 2.575 data required time Expanded Path 10 From: i_SIU/RXDATA_INST/reg_rxdf_d(14):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD14 data arrival time 2.948 data required time - 2.683 slack 0.265 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.392 net: SIU_RXCLK_cb 2.517 i_SIU/RXDATA_INST/reg_rxdf_d(14):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.723 i_SIU/RXDATA_INST/reg_rxdf_d(14):Q (r) + 0.225 net: i_SIU/s_rxdf_d_14_ 2.948 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD14 (r) 2.948 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.363 net: SIU_RXCLK_i 1.860 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 2.125 cbuf_SIU_RXCLK:Y (r) + 0.558 net: SIU_RXCLK_cb 2.683 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.683 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD14 2.683 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 2 From: SIU_RXD(2) To: addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 3 From: SIU_RXD(3) To: addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 4 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 5 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 6 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 7 From: SIU_RXD(10) To: addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 8 From: SIU_RXD(0) To: addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 9 From: SIU_RXD(15) To: addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Path 10 From: SIU_RXD(4) To: addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.964 Expanded Path 1 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXDV (f) + 0.000 net: SIU_RXDV 0.000 ibuf_SIU_RXDV_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 ibuf_SIU_RXDV_ib/U0/U0:Y (f) + 0.000 net: ibuf_SIU_RXDV_ib/U0/NET1 2.174 ibuf_SIU_RXDV_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C ibuf_SIU_RXDV_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXDV_ib/U0/U1:YIN Expanded Path 2 From: SIU_RXD(2) To: addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(2) (f) + 0.000 net: SIU_RXD_2_ 0.000 addds[2].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[2].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[2]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 3 From: SIU_RXD(3) To: addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(3) (f) + 0.000 net: SIU_RXD_3_ 0.000 addds[3].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[3].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[3]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 4 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(7) (f) + 0.000 net: SIU_RXD_7_ 0.000 addds[7].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[7].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[7]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 5 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXER (f) + 0.000 net: SIU_RXER 0.000 ibuf_SIU_RXER_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 ibuf_SIU_RXER_ib/U0/U0:Y (f) + 0.000 net: ibuf_SIU_RXER_ib/U0/NET1 2.174 ibuf_SIU_RXER_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C ibuf_SIU_RXER_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXER_ib/U0/U1:YIN Expanded Path 6 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(9) (f) + 0.000 net: SIU_RXD_9_ 0.000 addds[9].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[9].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[9]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 7 From: SIU_RXD(10) To: addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(10) (f) + 0.000 net: SIU_RXD_10_ 0.000 addds[10].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[10].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[10]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[10].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 8 From: SIU_RXD(0) To: addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(0) (f) + 0.000 net: SIU_RXD_0_ 0.000 addds[0].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[0].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[0]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 9 From: SIU_RXD(15) To: addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(15) (f) + 0.000 net: SIU_RXD_15_ 0.000 addds[15].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[15].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[15]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 10 From: SIU_RXD(4) To: addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(4) (f) + 0.000 net: SIU_RXD_4_ 0.000 addds[4].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[4].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[4]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN END SET External Hold ---------------------------------------------------- SET Clock to Output No Path END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: addds[2].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 3.969 Slack (ns): Arrival (ns): 3.969 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.831 Path 2 From: RST_n To: i_SIU/modgen_counter_srst_count_reg_q(1):CLR Delay (ns): 4.011 Slack (ns): Arrival (ns): 4.011 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.894 Path 3 From: RST_n To: addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.041 Slack (ns): Arrival (ns): 4.041 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.903 Path 4 From: RST_n To: addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.041 Slack (ns): Arrival (ns): 4.041 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.903 Path 5 From: RST_n To: addds[9].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.081 Slack (ns): Arrival (ns): 4.081 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.943 Path 6 From: RST_n To: addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.088 Slack (ns): Arrival (ns): 4.088 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.950 Path 7 From: RST_n To: i_SIU/reg_srst_pipe(2):PRE Delay (ns): 4.172 Slack (ns): Arrival (ns): 4.172 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.056 Path 8 From: RST_n To: addds[11].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.191 Slack (ns): Arrival (ns): 4.191 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.059 Path 9 From: RST_n To: i_SIU/reg_srst_pipe(0):PRE Delay (ns): 4.172 Slack (ns): Arrival (ns): 4.172 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.065 Path 10 From: RST_n To: i_SIU/reg_srst_pipe(1):PRE Delay (ns): 4.172 Slack (ns): Arrival (ns): 4.172 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.065 Expanded Path 1 From: RST_n To: addds[2].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 3.969 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.679 net: not_rst_n 3.969 addds[2].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 3.969 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 2 From: RST_n To: i_SIU/modgen_counter_srst_count_reg_q(1):CLR data arrival time 4.011 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.721 net: not_rst_n 4.011 i_SIU/modgen_counter_srst_count_reg_q(1):CLR (f) 4.011 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.451 net: SIU_RXCLK_cb N/C i_SIU/modgen_counter_srst_count_reg_q(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_SIU/modgen_counter_srst_count_reg_q(1):CLR Expanded Path 3 From: RST_n To: addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.041 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.751 net: not_rst_n 4.041 addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.041 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 4 From: RST_n To: addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.041 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.751 net: not_rst_n 4.041 addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.041 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 5 From: RST_n To: addds[9].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.081 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.791 net: not_rst_n 4.081 addds[9].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.081 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 6 From: RST_n To: addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.088 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.798 net: not_rst_n 4.088 addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.088 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.472 net: SIU_RXCLK_cb N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 7 From: RST_n To: i_SIU/reg_srst_pipe(2):PRE data arrival time 4.172 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.882 net: not_rst_n 4.172 i_SIU/reg_srst_pipe(2):PRE (f) 4.172 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.450 net: SIU_RXCLK_cb N/C i_SIU/reg_srst_pipe(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1P1 N/C i_SIU/reg_srst_pipe(2):PRE Expanded Path 8 From: RST_n To: addds[11].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.191 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.901 net: not_rst_n 4.191 addds[11].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.191 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.466 net: SIU_RXCLK_cb N/C addds[11].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[11].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 9 From: RST_n To: i_SIU/reg_srst_pipe(0):PRE data arrival time 4.172 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.882 net: not_rst_n 4.172 i_SIU/reg_srst_pipe(0):PRE (f) 4.172 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.441 net: SIU_RXCLK_cb N/C i_SIU/reg_srst_pipe(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1P1 N/C i_SIU/reg_srst_pipe(0):PRE Expanded Path 10 From: RST_n To: i_SIU/reg_srst_pipe(1):PRE data arrival time 4.172 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.882 net: not_rst_n 4.172 i_SIU/reg_srst_pipe(1):PRE (f) 4.172 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.710 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.441 net: SIU_RXCLK_cb N/C i_SIU/reg_srst_pipe(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1P1 N/C i_SIU/reg_srst_pipe(1):PRE END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain SIU_TXCLK SET Register to Register Path 1 From: i_SIU/FRAMING_INST/reg_tx_en_r2:CLK To: i_SIU/FRAMING_INST/reg_tx_en:D Delay (ns): 0.330 Slack (ns): 0.275 Arrival (ns): 2.858 Required (ns): 2.583 Hold (ns): 0.000 Path 2 From: i_SIU/INST_PMIF/reg_pm_value(9):CLK To: i_SIU/CMSIU_INST/reg_v_pmvstw(21):D Delay (ns): 0.362 Slack (ns): 0.285 Arrival (ns): 2.845 Required (ns): 2.560 Hold (ns): 0.000 Path 3 From: i_SIU/FRAMING_INST/reg_txd_dxd(15):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(15):D Delay (ns): 0.334 Slack (ns): 0.288 Arrival (ns): 2.889 Required (ns): 2.601 Hold (ns): 0.000 Path 4 From: i_SIU/FRAMING_INST/reg_txd_dxd(11):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(11):D Delay (ns): 0.334 Slack (ns): 0.288 Arrival (ns): 2.889 Required (ns): 2.601 Hold (ns): 0.000 Path 5 From: i_SIU/FRAMING_INST/reg_txd_dxd(14):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(14):D Delay (ns): 0.330 Slack (ns): 0.293 Arrival (ns): 2.880 Required (ns): 2.587 Hold (ns): 0.000 Path 6 From: i_SIU/FRAMING_INST/reg_txd_dxd(7):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(7):D Delay (ns): 0.330 Slack (ns): 0.293 Arrival (ns): 2.880 Required (ns): 2.587 Hold (ns): 0.000 Path 7 From: i_SIU/CMSIU_INST/reg_v_txst_d0(28):CLK To: i_SIU/CMSIU_INST/reg_txst_data(28):D Delay (ns): 0.330 Slack (ns): 0.293 Arrival (ns): 2.880 Required (ns): 2.587 Hold (ns): 0.000 Path 8 From: i_SIU/FRAMING_INST/reg_txd_dxd(3):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(3):D Delay (ns): 0.330 Slack (ns): 0.293 Arrival (ns): 2.876 Required (ns): 2.583 Hold (ns): 0.000 Path 9 From: i_SIU/LMSIU_INST/reg_rx_dxdata_d1(3):CLK To: i_SIU/LMSIU_INST/reg_tx_dxdata(7):D Delay (ns): 0.330 Slack (ns): 0.293 Arrival (ns): 2.880 Required (ns): 2.587 Hold (ns): 0.000 Path 10 From: i_SIU/FRAMING_INST/reg_tx_er_r2:CLK To: i_SIU/FRAMING_INST/reg_tx_er:D Delay (ns): 0.330 Slack (ns): 0.293 Arrival (ns): 2.876 Required (ns): 2.583 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/FRAMING_INST/reg_tx_en_r2:CLK To: i_SIU/FRAMING_INST/reg_tx_en:D data arrival time 2.858 data required time - 2.583 slack 0.275 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.673 net: SIU_TXCLK_cb 2.528 i_SIU/FRAMING_INST/reg_tx_en_r2:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.734 i_SIU/FRAMING_INST/reg_tx_en_r2:Q (r) + 0.124 net: i_SIU/FRAMING_INST/tx_en_r2 2.858 i_SIU/FRAMING_INST/reg_tx_en:D (r) 2.858 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.728 net: SIU_TXCLK_cb 2.583 i_SIU/FRAMING_INST/reg_tx_en:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.583 i_SIU/FRAMING_INST/reg_tx_en:D 2.583 data required time Expanded Path 2 From: i_SIU/INST_PMIF/reg_pm_value(9):CLK To: i_SIU/CMSIU_INST/reg_v_pmvstw(21):D data arrival time 2.845 data required time - 2.560 slack 0.285 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.628 net: SIU_TXCLK_cb 2.483 i_SIU/INST_PMIF/reg_pm_value(9):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.689 i_SIU/INST_PMIF/reg_pm_value(9):Q (r) + 0.156 net: i_SIU/s_pm_value_9_ 2.845 i_SIU/CMSIU_INST/reg_v_pmvstw(21):D (r) 2.845 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.705 net: SIU_TXCLK_cb 2.560 i_SIU/CMSIU_INST/reg_v_pmvstw(21):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.560 i_SIU/CMSIU_INST/reg_v_pmvstw(21):D 2.560 data required time Expanded Path 3 From: i_SIU/FRAMING_INST/reg_txd_dxd(15):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(15):D data arrival time 2.889 data required time - 2.601 slack 0.288 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.700 net: SIU_TXCLK_cb 2.555 i_SIU/FRAMING_INST/reg_txd_dxd(15):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.761 i_SIU/FRAMING_INST/reg_txd_dxd(15):Q (r) + 0.128 net: i_SIU/FRAMING_INST/txd_dxd_15_ 2.889 i_SIU/FRAMING_INST/reg_txd_diag(15):D (r) 2.889 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.746 net: SIU_TXCLK_cb 2.601 i_SIU/FRAMING_INST/reg_txd_diag(15):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.601 i_SIU/FRAMING_INST/reg_txd_diag(15):D 2.601 data required time Expanded Path 4 From: i_SIU/FRAMING_INST/reg_txd_dxd(11):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(11):D data arrival time 2.889 data required time - 2.601 slack 0.288 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.700 net: SIU_TXCLK_cb 2.555 i_SIU/FRAMING_INST/reg_txd_dxd(11):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.761 i_SIU/FRAMING_INST/reg_txd_dxd(11):Q (r) + 0.128 net: i_SIU/FRAMING_INST/txd_dxd_11_ 2.889 i_SIU/FRAMING_INST/reg_txd_diag(11):D (r) 2.889 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.746 net: SIU_TXCLK_cb 2.601 i_SIU/FRAMING_INST/reg_txd_diag(11):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.601 i_SIU/FRAMING_INST/reg_txd_diag(11):D 2.601 data required time Expanded Path 5 From: i_SIU/FRAMING_INST/reg_txd_dxd(14):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(14):D data arrival time 2.880 data required time - 2.587 slack 0.293 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/FRAMING_INST/reg_txd_dxd(14):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.756 i_SIU/FRAMING_INST/reg_txd_dxd(14):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_14_ 2.880 i_SIU/FRAMING_INST/reg_txd_diag(14):D (r) 2.880 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.732 net: SIU_TXCLK_cb 2.587 i_SIU/FRAMING_INST/reg_txd_diag(14):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.587 i_SIU/FRAMING_INST/reg_txd_diag(14):D 2.587 data required time Expanded Path 6 From: i_SIU/FRAMING_INST/reg_txd_dxd(7):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(7):D data arrival time 2.880 data required time - 2.587 slack 0.293 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/FRAMING_INST/reg_txd_dxd(7):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.756 i_SIU/FRAMING_INST/reg_txd_dxd(7):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_7_ 2.880 i_SIU/FRAMING_INST/reg_txd_diag(7):D (r) 2.880 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.732 net: SIU_TXCLK_cb 2.587 i_SIU/FRAMING_INST/reg_txd_diag(7):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.587 i_SIU/FRAMING_INST/reg_txd_diag(7):D 2.587 data required time Expanded Path 7 From: i_SIU/CMSIU_INST/reg_v_txst_d0(28):CLK To: i_SIU/CMSIU_INST/reg_txst_data(28):D data arrival time 2.880 data required time - 2.587 slack 0.293 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/CMSIU_INST/reg_v_txst_d0(28):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.756 i_SIU/CMSIU_INST/reg_v_txst_d0(28):Q (r) + 0.124 net: i_SIU/CMSIU_INST/v_txst_d0_28_ 2.880 i_SIU/CMSIU_INST/reg_txst_data(28):D (r) 2.880 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.732 net: SIU_TXCLK_cb 2.587 i_SIU/CMSIU_INST/reg_txst_data(28):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.587 i_SIU/CMSIU_INST/reg_txst_data(28):D 2.587 data required time Expanded Path 8 From: i_SIU/FRAMING_INST/reg_txd_dxd(3):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(3):D data arrival time 2.876 data required time - 2.583 slack 0.293 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.691 net: SIU_TXCLK_cb 2.546 i_SIU/FRAMING_INST/reg_txd_dxd(3):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.752 i_SIU/FRAMING_INST/reg_txd_dxd(3):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_3_ 2.876 i_SIU/FRAMING_INST/reg_txd_diag(3):D (r) 2.876 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.728 net: SIU_TXCLK_cb 2.583 i_SIU/FRAMING_INST/reg_txd_diag(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.583 i_SIU/FRAMING_INST/reg_txd_diag(3):D 2.583 data required time Expanded Path 9 From: i_SIU/LMSIU_INST/reg_rx_dxdata_d1(3):CLK To: i_SIU/LMSIU_INST/reg_tx_dxdata(7):D data arrival time 2.880 data required time - 2.587 slack 0.293 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/LMSIU_INST/reg_rx_dxdata_d1(3):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.756 i_SIU/LMSIU_INST/reg_rx_dxdata_d1(3):Q (r) + 0.124 net: i_SIU/LMSIU_INST/rx_dxdata_d1_3_ 2.880 i_SIU/LMSIU_INST/reg_tx_dxdata(7):D (r) 2.880 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.732 net: SIU_TXCLK_cb 2.587 i_SIU/LMSIU_INST/reg_tx_dxdata(7):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.587 i_SIU/LMSIU_INST/reg_tx_dxdata(7):D 2.587 data required time Expanded Path 10 From: i_SIU/FRAMING_INST/reg_tx_er_r2:CLK To: i_SIU/FRAMING_INST/reg_tx_er:D data arrival time 2.876 data required time - 2.583 slack 0.293 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.691 net: SIU_TXCLK_cb 2.546 i_SIU/FRAMING_INST/reg_tx_er_r2:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.752 i_SIU/FRAMING_INST/reg_tx_er_r2:Q (r) + 0.124 net: i_SIU/FRAMING_INST/tx_er_r2 2.876 i_SIU/FRAMING_INST/reg_tx_er:D (r) 2.876 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.728 net: SIU_TXCLK_cb 2.583 i_SIU/FRAMING_INST/reg_tx_er:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.583 i_SIU/FRAMING_INST/reg_tx_er:D 2.583 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SFP_TX_FAULT To: i_SIU/reg_s_ot_tf:D Delay (ns): 1.594 Slack (ns): Arrival (ns): 1.594 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.489 Path 2 From: RST_n To: reg_q(16):E Delay (ns): 2.533 Slack (ns): Arrival (ns): 2.533 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.561 Path 3 From: RST_n To: reg_q(25):D Delay (ns): 2.550 Slack (ns): Arrival (ns): 2.550 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.533 Path 4 From: RST_n To: reg_q(0):D Delay (ns): 2.618 Slack (ns): Arrival (ns): 2.618 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.473 Path 5 From: RST_n To: reg_q(20):D Delay (ns): 2.632 Slack (ns): Arrival (ns): 2.632 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.462 Path 6 From: RST_n To: reg_q(16):D Delay (ns): 2.632 Slack (ns): Arrival (ns): 2.632 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.462 Path 7 From: RST_n To: reg_q(18):D Delay (ns): 2.630 Slack (ns): Arrival (ns): 2.630 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.455 Path 8 From: RST_n To: reg_q(23):D Delay (ns): 2.635 Slack (ns): Arrival (ns): 2.635 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.450 Path 9 From: RST_n To: reg_q(5):D Delay (ns): 2.658 Slack (ns): Arrival (ns): 2.658 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.449 Path 10 From: RST_n To: reg_q(4):E Delay (ns): 2.682 Slack (ns): Arrival (ns): 2.682 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.425 Expanded Path 1 From: SFP_TX_FAULT To: i_SIU/reg_s_ot_tf:D data arrival time 1.594 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFP_TX_FAULT (f) + 0.000 net: SFP_TX_FAULT 0.000 ibuf_SFP_TX_FAULT_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFP_TX_FAULT_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFP_TX_FAULT_ib/U0/NET1 0.470 ibuf_SFP_TX_FAULT_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFP_TX_FAULT_ib/U0/U1:Y (f) + 1.110 net: SFP_TX_FAULT_i 1.594 i_SIU/reg_s_ot_tf:D (f) 1.594 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.755 net: SIU_TXCLK_cb N/C i_SIU/reg_s_ot_tf:CLK (r) + 0.000 Library hold time: ADLIB:DFN1 N/C i_SIU/reg_s_ot_tf:D Expanded Path 2 From: RST_n To: reg_q(16):E data arrival time 2.533 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.802 net: RST_n_i 2.286 ix23078z24338:A (f) + 0.128 cell: ADLIB:NAND3 2.414 ix23078z24338:Y (r) + 0.119 net: nx23078z2 2.533 reg_q(16):E (r) 2.533 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.766 net: SIU_TXCLK_cb N/C reg_q(16):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(16):E Expanded Path 3 From: RST_n To: reg_q(25):D data arrival time 2.550 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.721 net: RST_n_i 2.205 ix33050z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.428 ix33050z2956:Y (f) + 0.122 net: nx33050z1 2.550 reg_q(25):D (f) 2.550 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.755 net: SIU_TXCLK_cb N/C reg_q(25):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(25):D Expanded Path 4 From: RST_n To: reg_q(0):D data arrival time 2.618 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.788 net: RST_n_i 2.272 ix51271z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.495 ix51271z2956:Y (f) + 0.123 net: nx51271z1 2.618 reg_q(0):D (f) 2.618 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.763 net: SIU_TXCLK_cb N/C reg_q(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1 N/C reg_q(0):D Expanded Path 5 From: RST_n To: reg_q(20):D data arrival time 2.632 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.807 net: RST_n_i 2.291 ix28065z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.514 ix28065z2956:Y (f) + 0.118 net: nx28065z1 2.632 reg_q(20):D (f) 2.632 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.766 net: SIU_TXCLK_cb N/C reg_q(20):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(20):D Expanded Path 6 From: RST_n To: reg_q(16):D data arrival time 2.632 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.807 net: RST_n_i 2.291 ix23078z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.514 ix23078z2956:Y (f) + 0.118 net: nx23078z1 2.632 reg_q(16):D (f) 2.632 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.766 net: SIU_TXCLK_cb N/C reg_q(16):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(16):D Expanded Path 7 From: RST_n To: reg_q(18):D data arrival time 2.630 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.807 net: RST_n_i 2.291 ix25072z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.514 ix25072z2956:Y (f) + 0.116 net: nx25072z1 2.630 reg_q(18):D (f) 2.630 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.757 net: SIU_TXCLK_cb N/C reg_q(18):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(18):D Expanded Path 8 From: RST_n To: reg_q(23):D data arrival time 2.635 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.807 net: RST_n_i 2.291 ix31056z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.514 ix31056z2956:Y (f) + 0.121 net: nx31056z1 2.635 reg_q(23):D (f) 2.635 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.757 net: SIU_TXCLK_cb N/C reg_q(23):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(23):D Expanded Path 9 From: RST_n To: reg_q(5):D data arrival time 2.658 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.830 net: RST_n_i 2.314 ix56256z2956:B (f) + 0.223 cell: ADLIB:AND3A 2.537 ix56256z2956:Y (f) + 0.121 net: nx56256z1 2.658 reg_q(5):D (f) 2.658 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.779 net: SIU_TXCLK_cb N/C reg_q(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(5):D Expanded Path 10 From: RST_n To: reg_q(4):E data arrival time 2.682 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (f) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_RST_n_ib/U0/U0:Y (f) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.470 ibuf_RST_n_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_RST_n_ib/U0/U1:Y (f) + 1.946 net: RST_n_i 2.430 ix55259z24338:A (f) + 0.128 cell: ADLIB:NAND3 2.558 ix55259z24338:Y (r) + 0.124 net: nx55259z2 2.682 reg_q(4):E (r) 2.682 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.779 net: SIU_TXCLK_cb N/C reg_q(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(4):E END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(2) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.536 Required (ns): Clock to Out (ns): 3.536 Path 2 From: addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(6) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.536 Required (ns): Clock to Out (ns): 3.536 Path 3 From: addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(9) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.536 Required (ns): Clock to Out (ns): 3.536 Path 4 From: addds[10].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(10) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.536 Required (ns): Clock to Out (ns): 3.536 Path 5 From: addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(3) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.537 Required (ns): Clock to Out (ns): 3.537 Path 6 From: addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(7) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.538 Required (ns): Clock to Out (ns): 3.538 Path 7 From: addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(0) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.539 Required (ns): Clock to Out (ns): 3.539 Path 8 From: addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(1) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.539 Required (ns): Clock to Out (ns): 3.539 Path 9 From: addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(4) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.539 Required (ns): Clock to Out (ns): 3.539 Path 10 From: addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(5) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.539 Required (ns): Clock to Out (ns): 3.539 Expanded Path 1 From: addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(2) data arrival time 3.536 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.611 net: SIU_TXCLK_cb 2.466 addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.745 addds[2].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[2]_obuf_SIU_TXD_U1/U0/NET1 2.745 addds[2].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.536 addds[2].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_2_ 3.536 SIU_TXD(2) (r) 3.536 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(2) (r) Expanded Path 2 From: addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(6) data arrival time 3.536 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.611 net: SIU_TXCLK_cb 2.466 addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.745 addds[6].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[6]_obuf_SIU_TXD_U1/U0/NET1 2.745 addds[6].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.536 addds[6].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_6_ 3.536 SIU_TXD(6) (r) 3.536 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(6) (r) Expanded Path 3 From: addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(9) data arrival time 3.536 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.611 net: SIU_TXCLK_cb 2.466 addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.745 addds[9].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[9]_obuf_SIU_TXD_U1/U0/NET1 2.745 addds[9].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.536 addds[9].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_9_ 3.536 SIU_TXD(9) (r) 3.536 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(9) (r) Expanded Path 4 From: addds[10].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(10) data arrival time 3.536 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.611 net: SIU_TXCLK_cb 2.466 addds[10].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.745 addds[10].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[10]_obuf_SIU_TXD_U1/U0/NET1 2.745 addds[10].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.536 addds[10].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_10_ 3.536 SIU_TXD(10) (r) 3.536 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(10) (r) Expanded Path 5 From: addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(3) data arrival time 3.537 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.612 net: SIU_TXCLK_cb 2.467 addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.746 addds[3].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[3]_obuf_SIU_TXD_U1/U0/NET1 2.746 addds[3].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.537 addds[3].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_3_ 3.537 SIU_TXD(3) (r) 3.537 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(3) (r) Expanded Path 6 From: addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(7) data arrival time 3.538 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.613 net: SIU_TXCLK_cb 2.468 addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.747 addds[7].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[7]_obuf_SIU_TXD_U1/U0/NET1 2.747 addds[7].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.538 addds[7].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_7_ 3.538 SIU_TXD(7) (r) 3.538 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(7) (r) Expanded Path 7 From: addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(0) data arrival time 3.539 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.614 net: SIU_TXCLK_cb 2.469 addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.748 addds[0].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[0]_obuf_SIU_TXD_U1/U0/NET1 2.748 addds[0].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.539 addds[0].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_0_ 3.539 SIU_TXD(0) (r) 3.539 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(0) (r) Expanded Path 8 From: addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(1) data arrival time 3.539 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.614 net: SIU_TXCLK_cb 2.469 addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.748 addds[1].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[1]_obuf_SIU_TXD_U1/U0/NET1 2.748 addds[1].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.539 addds[1].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_1_ 3.539 SIU_TXD(1) (r) 3.539 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(1) (r) Expanded Path 9 From: addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(4) data arrival time 3.539 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.614 net: SIU_TXCLK_cb 2.469 addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.748 addds[4].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[4]_obuf_SIU_TXD_U1/U0/NET1 2.748 addds[4].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.539 addds[4].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_4_ 3.539 SIU_TXD(4) (r) 3.539 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(4) (r) Expanded Path 10 From: addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(5) data arrival time 3.539 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.614 net: SIU_TXCLK_cb 2.469 addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.748 addds[5].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[5]_obuf_SIU_TXD_U1/U0/NET1 2.748 addds[5].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.539 addds[5].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_5_ 3.539 SIU_TXD(5) (r) 3.539 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(5) (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_tx_er_r1:CLR Delay (ns): 0.616 Slack (ns): 0.583 Arrival (ns): 3.166 Required (ns): 2.583 Removal (ns): 0.000 Skew (ns): -0.033 Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_hwidstw(22):CLR Delay (ns): 0.685 Slack (ns): 0.642 Arrival (ns): 3.235 Required (ns): 2.593 Removal (ns): 0.000 Skew (ns): -0.043 Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd(10):CLR Delay (ns): 0.695 Slack (ns): 0.662 Arrival (ns): 3.245 Required (ns): 2.583 Removal (ns): 0.000 Skew (ns): -0.033 Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_sts_present(2):CLR Delay (ns): 0.650 Slack (ns): 0.667 Arrival (ns): 3.200 Required (ns): 2.533 Removal (ns): 0.000 Skew (ns): 0.017 Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_sts_present(13):CLR Delay (ns): 0.650 Slack (ns): 0.667 Arrival (ns): 3.200 Required (ns): 2.533 Removal (ns): 0.000 Skew (ns): 0.017 Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts1(15):CLR Delay (ns): 0.673 Slack (ns): 0.681 Arrival (ns): 3.223 Required (ns): 2.542 Removal (ns): 0.000 Skew (ns): 0.008 Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(6):CLR Delay (ns): 0.673 Slack (ns): 0.681 Arrival (ns): 3.223 Required (ns): 2.542 Removal (ns): 0.000 Skew (ns): 0.008 Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/LMSIU_INST/reg_tx_txdiag:CLR Delay (ns): 0.673 Slack (ns): 0.688 Arrival (ns): 3.223 Required (ns): 2.535 Removal (ns): 0.000 Skew (ns): 0.015 Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_pmvstw(24):CLR Delay (ns): 0.680 Slack (ns): 0.692 Arrival (ns): 3.230 Required (ns): 2.538 Removal (ns): 0.000 Skew (ns): 0.012 Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value(11):CLR Delay (ns): 0.682 Slack (ns): 0.694 Arrival (ns): 3.232 Required (ns): 2.538 Removal (ns): 0.000 Skew (ns): 0.012 Expanded Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_tx_er_r1:CLR data arrival time 3.166 data required time - 2.583 slack 0.583 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.410 net: i_SIU/s_arstn 3.166 i_SIU/FRAMING_INST/reg_tx_er_r1:CLR (r) 3.166 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.728 net: SIU_TXCLK_cb 2.583 i_SIU/FRAMING_INST/reg_tx_er_r1:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.583 i_SIU/FRAMING_INST/reg_tx_er_r1:CLR 2.583 data required time Expanded Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_hwidstw(22):CLR data arrival time 3.235 data required time - 2.593 slack 0.642 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.479 net: i_SIU/s_arstn 3.235 i_SIU/CMSIU_INST/reg_v_hwidstw(22):CLR (r) 3.235 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.738 net: SIU_TXCLK_cb 2.593 i_SIU/CMSIU_INST/reg_v_hwidstw(22):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.593 i_SIU/CMSIU_INST/reg_v_hwidstw(22):CLR 2.593 data required time Expanded Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd(10):CLR data arrival time 3.245 data required time - 2.583 slack 0.662 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.489 net: i_SIU/s_arstn 3.245 i_SIU/FRAMING_INST/reg_txd(10):CLR (r) 3.245 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.728 net: SIU_TXCLK_cb 2.583 i_SIU/FRAMING_INST/reg_txd(10):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.583 i_SIU/FRAMING_INST/reg_txd(10):CLR 2.583 data required time Expanded Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_sts_present(2):CLR data arrival time 3.200 data required time - 2.533 slack 0.667 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.444 net: i_SIU/s_arstn 3.200 i_SIU/CMSIU_INST/reg_sts_present(2):CLR (r) 3.200 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.678 net: SIU_TXCLK_cb 2.533 i_SIU/CMSIU_INST/reg_sts_present(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.533 i_SIU/CMSIU_INST/reg_sts_present(2):CLR 2.533 data required time Expanded Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_sts_present(13):CLR data arrival time 3.200 data required time - 2.533 slack 0.667 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.444 net: i_SIU/s_arstn 3.200 i_SIU/CMSIU_INST/reg_sts_present(13):CLR (r) 3.200 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.678 net: SIU_TXCLK_cb 2.533 i_SIU/CMSIU_INST/reg_sts_present(13):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.533 i_SIU/CMSIU_INST/reg_sts_present(13):CLR 2.533 data required time Expanded Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts1(15):CLR data arrival time 3.223 data required time - 2.542 slack 0.681 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.467 net: i_SIU/s_arstn 3.223 i_SIU/FRAMING_INST/reg_txd_sts1(15):CLR (r) 3.223 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.687 net: SIU_TXCLK_cb 2.542 i_SIU/FRAMING_INST/reg_txd_sts1(15):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.542 i_SIU/FRAMING_INST/reg_txd_sts1(15):CLR 2.542 data required time Expanded Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(6):CLR data arrival time 3.223 data required time - 2.542 slack 0.681 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.467 net: i_SIU/s_arstn 3.223 i_SIU/CMSIU_INST/reg_txst_data(6):CLR (r) 3.223 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.687 net: SIU_TXCLK_cb 2.542 i_SIU/CMSIU_INST/reg_txst_data(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.542 i_SIU/CMSIU_INST/reg_txst_data(6):CLR 2.542 data required time Expanded Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/LMSIU_INST/reg_tx_txdiag:CLR data arrival time 3.223 data required time - 2.535 slack 0.688 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.467 net: i_SIU/s_arstn 3.223 i_SIU/LMSIU_INST/reg_tx_txdiag:CLR (r) 3.223 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.680 net: SIU_TXCLK_cb 2.535 i_SIU/LMSIU_INST/reg_tx_txdiag:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.535 i_SIU/LMSIU_INST/reg_tx_txdiag:CLR 2.535 data required time Expanded Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_pmvstw(24):CLR data arrival time 3.230 data required time - 2.538 slack 0.692 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.474 net: i_SIU/s_arstn 3.230 i_SIU/CMSIU_INST/reg_v_pmvstw(24):CLR (r) 3.230 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.683 net: SIU_TXCLK_cb 2.538 i_SIU/CMSIU_INST/reg_v_pmvstw(24):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.538 i_SIU/CMSIU_INST/reg_v_pmvstw(24):CLR 2.538 data required time Expanded Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value(11):CLR data arrival time 3.232 data required time - 2.538 slack 0.694 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.695 net: SIU_TXCLK_cb 2.550 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.756 i_SIU/reg_s_arstn:Q (r) + 0.476 net: i_SIU/s_arstn 3.232 i_SIU/INST_PMIF/reg_pm_value(11):CLR (r) 3.232 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.093 net: SIU_TXCLK_i 1.590 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.855 cbuf_SIU_TXCLK:Y (r) + 0.683 net: SIU_TXCLK_cb 2.538 i_SIU/INST_PMIF/reg_pm_value(11):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.538 i_SIU/INST_PMIF/reg_pm_value(11):CLR 2.538 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: i_SIU/reg_s_arstn:CLR Delay (ns): 3.962 Slack (ns): Arrival (ns): 3.962 Required (ns): Removal (ns): 0.000 External Removal (ns): -0.772 Path 2 From: RST_n To: obuf_SIU_TXEN_U1/U0/U1:CLR Delay (ns): 5.407 Slack (ns): Arrival (ns): 5.407 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.277 Path 3 From: RST_n To: obuf_SIU_TXER_U1/U0/U1:CLR Delay (ns): 5.526 Slack (ns): Arrival (ns): 5.526 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.396 Path 4 From: RST_n To: addds[12].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.499 Slack (ns): Arrival (ns): 5.499 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.409 Path 5 From: RST_n To: addds[11].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.499 Slack (ns): Arrival (ns): 5.499 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.409 Path 6 From: PUSHB To: i_SIU/reg_s_arstn:CLR Delay (ns): 5.770 Slack (ns): Arrival (ns): 5.770 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.580 Path 7 From: RST_n To: addds[14].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.873 Slack (ns): Arrival (ns): 5.873 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.669 Path 8 From: RST_n To: addds[7].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.846 Slack (ns): Arrival (ns): 5.846 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.757 Path 9 From: RST_n To: addds[6].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.919 Slack (ns): Arrival (ns): 5.919 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.833 Path 10 From: RST_n To: addds[8].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 6.060 Slack (ns): Arrival (ns): 6.060 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.968 Expanded Path 1 From: RST_n To: i_SIU/reg_s_arstn:CLR data arrival time 3.962 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.672 net: not_rst_n 3.962 i_SIU/reg_s_arstn:CLR (f) 3.962 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.862 net: SIU_TXCLK_cb N/C i_SIU/reg_s_arstn:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_SIU/reg_s_arstn:CLR Expanded Path 2 From: RST_n To: obuf_SIU_TXEN_U1/U0/U1:CLR data arrival time 5.407 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.117 net: not_rst_n 5.407 obuf_SIU_TXEN_U1/U0/U1:CLR (f) 5.407 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.802 net: SIU_TXCLK_cb N/C obuf_SIU_TXEN_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C obuf_SIU_TXEN_U1/U0/U1:CLR Expanded Path 3 From: RST_n To: obuf_SIU_TXER_U1/U0/U1:CLR data arrival time 5.526 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.236 net: not_rst_n 5.526 obuf_SIU_TXER_U1/U0/U1:CLR (f) 5.526 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.802 net: SIU_TXCLK_cb N/C obuf_SIU_TXER_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C obuf_SIU_TXER_U1/U0/U1:CLR Expanded Path 4 From: RST_n To: addds[12].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.499 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.209 net: not_rst_n 5.499 addds[12].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.499 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.762 net: SIU_TXCLK_cb N/C addds[12].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[12].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 5 From: RST_n To: addds[11].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.499 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.209 net: not_rst_n 5.499 addds[11].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.499 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.762 net: SIU_TXCLK_cb N/C addds[11].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[11].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 6 From: PUSHB To: i_SIU/reg_s_arstn:CLR data arrival time 5.770 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 3.418 net: PUSHB_i 3.893 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 4.098 i_adc/adc/ix4491z24338:Y (f) + 1.672 net: not_rst_n 5.770 i_SIU/reg_s_arstn:CLR (f) 5.770 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.862 net: SIU_TXCLK_cb N/C i_SIU/reg_s_arstn:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_SIU/reg_s_arstn:CLR Expanded Path 7 From: RST_n To: addds[14].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.873 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.583 net: not_rst_n 5.873 addds[14].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.873 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.876 net: SIU_TXCLK_cb N/C addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[14].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 8 From: RST_n To: addds[7].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.846 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.556 net: not_rst_n 5.846 addds[7].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.846 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.761 net: SIU_TXCLK_cb N/C addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[7].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 9 From: RST_n To: addds[6].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.919 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.629 net: not_rst_n 5.919 addds[6].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.919 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.758 net: SIU_TXCLK_cb N/C addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[6].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 10 From: RST_n To: addds[8].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 6.060 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 3.770 net: not_rst_n 6.060 addds[8].obuf_SIU_TXD_U1/U0/U1:CLR (f) 6.060 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.372 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.764 net: SIU_TXCLK_cb N/C addds[8].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[8].obuf_SIU_TXD_U1/U0/U1:CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_SIU/reg_tx_clk_2:Q SET Register to Register Path 1 From: i_SIU/I2CIF_INST/reg_i2c_present(14):CLK To: i_SIU/I2CIF_INST/reg_i2c_ack:D Delay (ns): 0.586 Slack (ns): 0.562 Arrival (ns): 3.169 Required (ns): 2.607 Hold (ns): 0.000 Path 2 From: i_SIU/I2CIF_INST/reg_i2c_present(6):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D Delay (ns): 0.596 Slack (ns): 0.576 Arrival (ns): 3.187 Required (ns): 2.611 Hold (ns): 0.000 Path 3 From: i_SIU/modgen_counter_slot_timer_reg_q(1):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(1):D Delay (ns): 0.595 Slack (ns): 0.578 Arrival (ns): 3.174 Required (ns): 2.596 Hold (ns): 0.000 Path 4 From: i_SIU/I2CIF_INST/reg_scl_present(1):CLK To: i_SIU/I2CIF_INST/reg_scl_present(1):D Delay (ns): 0.623 Slack (ns): 0.607 Arrival (ns): 3.202 Required (ns): 2.595 Hold (ns): 0.000 Path 5 From: i_SIU/modgen_counter_slot_timer_reg_q(0):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(0):D Delay (ns): 0.623 Slack (ns): 0.607 Arrival (ns): 3.202 Required (ns): 2.595 Hold (ns): 0.000 Path 6 From: i_SIU/I2CIF_INST/reg_q(6):CLK To: i_SIU/I2CIF_INST/reg_q(6):D Delay (ns): 0.646 Slack (ns): 0.628 Arrival (ns): 3.229 Required (ns): 2.601 Hold (ns): 0.000 Path 7 From: i_SIU/I2CIF_INST/reg_q(5):CLK To: i_SIU/I2CIF_INST/reg_q(5):D Delay (ns): 0.646 Slack (ns): 0.628 Arrival (ns): 3.229 Required (ns): 2.601 Hold (ns): 0.000 Path 8 From: i_SIU/I2CIF_INST/reg_q(3):CLK To: i_SIU/I2CIF_INST/reg_q(3):D Delay (ns): 0.646 Slack (ns): 0.628 Arrival (ns): 3.229 Required (ns): 2.601 Hold (ns): 0.000 Path 9 From: i_SIU/modgen_counter_slot_timer_reg_q(1):CLK To: i_SIU/reg_b_led_update:D Delay (ns): 0.659 Slack (ns): 0.642 Arrival (ns): 3.238 Required (ns): 2.596 Hold (ns): 0.000 Path 10 From: i_SIU/reg_blink_timer(13):CLK To: i_SIU/reg_blink_timer(13):D Delay (ns): 0.665 Slack (ns): 0.647 Arrival (ns): 3.246 Required (ns): 2.599 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/I2CIF_INST/reg_i2c_present(14):CLK To: i_SIU/I2CIF_INST/reg_i2c_ack:D data arrival time 3.169 data required time - 2.607 slack 0.562 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.623 net: i_SIU/tx_clk_2b 2.583 i_SIU/I2CIF_INST/reg_i2c_present(14):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.789 i_SIU/I2CIF_INST/reg_i2c_present(14):Q (r) + 0.380 net: i_SIU/I2CIF_INST/i2c_present_14_ 3.169 i_SIU/I2CIF_INST/reg_i2c_ack:D (r) 3.169 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.647 net: i_SIU/tx_clk_2b 2.607 i_SIU/I2CIF_INST/reg_i2c_ack:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.607 i_SIU/I2CIF_INST/reg_i2c_ack:D 2.607 data required time Expanded Path 2 From: i_SIU/I2CIF_INST/reg_i2c_present(6):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D data arrival time 3.187 data required time - 2.611 slack 0.576 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.631 net: i_SIU/tx_clk_2b 2.591 i_SIU/I2CIF_INST/reg_i2c_present(6):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.797 i_SIU/I2CIF_INST/reg_i2c_present(6):Q (r) + 0.144 net: i_SIU/I2CIF_INST/i2c_present_6_ 2.941 i_SIU/I2CIF_INST/ix26586z26293:S (r) + 0.130 cell: ADLIB:MX2A 3.071 i_SIU/I2CIF_INST/ix26586z26293:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx26586z1 3.187 i_SIU/I2CIF_INST/reg_i2c_present(6):D (f) 3.187 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.651 net: i_SIU/tx_clk_2b 2.611 i_SIU/I2CIF_INST/reg_i2c_present(6):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.611 i_SIU/I2CIF_INST/reg_i2c_present(6):D 2.611 data required time Expanded Path 3 From: i_SIU/modgen_counter_slot_timer_reg_q(1):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(1):D data arrival time 3.174 data required time - 2.596 slack 0.578 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.619 net: i_SIU/tx_clk_2b 2.579 i_SIU/modgen_counter_slot_timer_reg_q(1):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.785 i_SIU/modgen_counter_slot_timer_reg_q(1):Q (r) + 0.143 net: i_SIU/slot_timer_1_ 2.928 i_SIU/ix22487z8206:C (r) + 0.122 cell: ADLIB:AX1C 3.050 i_SIU/ix22487z8206:Y (r) + 0.124 net: i_SIU/nx22487z1 3.174 i_SIU/modgen_counter_slot_timer_reg_q(1):D (r) 3.174 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.636 net: i_SIU/tx_clk_2b 2.596 i_SIU/modgen_counter_slot_timer_reg_q(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.596 i_SIU/modgen_counter_slot_timer_reg_q(1):D 2.596 data required time Expanded Path 4 From: i_SIU/I2CIF_INST/reg_scl_present(1):CLK To: i_SIU/I2CIF_INST/reg_scl_present(1):D data arrival time 3.202 data required time - 2.595 slack 0.607 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.619 net: i_SIU/tx_clk_2b 2.579 i_SIU/I2CIF_INST/reg_scl_present(1):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.785 i_SIU/I2CIF_INST/reg_scl_present(1):Q (r) + 0.171 net: i_SIU/I2CIF_INST/scl_present_1_ 2.956 i_SIU/I2CIF_INST/ix37211z8206:C (r) + 0.122 cell: ADLIB:AX1C 3.078 i_SIU/I2CIF_INST/ix37211z8206:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx37211z1 3.202 i_SIU/I2CIF_INST/reg_scl_present(1):D (r) 3.202 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.635 net: i_SIU/tx_clk_2b 2.595 i_SIU/I2CIF_INST/reg_scl_present(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.595 i_SIU/I2CIF_INST/reg_scl_present(1):D 2.595 data required time Expanded Path 5 From: i_SIU/modgen_counter_slot_timer_reg_q(0):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(0):D data arrival time 3.202 data required time - 2.595 slack 0.607 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.619 net: i_SIU/tx_clk_2b 2.579 i_SIU/modgen_counter_slot_timer_reg_q(0):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.785 i_SIU/modgen_counter_slot_timer_reg_q(0):Q (r) + 0.171 net: i_SIU/slot_timer_0_ 2.956 i_SIU/ix23484z10876:A (r) + 0.122 cell: ADLIB:XOR2 3.078 i_SIU/ix23484z10876:Y (r) + 0.124 net: i_SIU/nx23484z1 3.202 i_SIU/modgen_counter_slot_timer_reg_q(0):D (r) 3.202 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.635 net: i_SIU/tx_clk_2b 2.595 i_SIU/modgen_counter_slot_timer_reg_q(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.595 i_SIU/modgen_counter_slot_timer_reg_q(0):D 2.595 data required time Expanded Path 6 From: i_SIU/I2CIF_INST/reg_q(6):CLK To: i_SIU/I2CIF_INST/reg_q(6):D data arrival time 3.229 data required time - 2.601 slack 0.628 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.623 net: i_SIU/tx_clk_2b 2.583 i_SIU/I2CIF_INST/reg_q(6):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.789 i_SIU/I2CIF_INST/reg_q(6):Q (r) + 0.143 net: i_SIU/I2CIF_INST/nx59247z9 2.932 i_SIU/I2CIF_INST/ix57253z4192:C (r) + 0.173 cell: ADLIB:AXOI4 3.105 i_SIU/I2CIF_INST/ix57253z4192:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx57253z1 3.229 i_SIU/I2CIF_INST/reg_q(6):D (r) 3.229 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.641 net: i_SIU/tx_clk_2b 2.601 i_SIU/I2CIF_INST/reg_q(6):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.601 i_SIU/I2CIF_INST/reg_q(6):D 2.601 data required time Expanded Path 7 From: i_SIU/I2CIF_INST/reg_q(5):CLK To: i_SIU/I2CIF_INST/reg_q(5):D data arrival time 3.229 data required time - 2.601 slack 0.628 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.623 net: i_SIU/tx_clk_2b 2.583 i_SIU/I2CIF_INST/reg_q(5):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.789 i_SIU/I2CIF_INST/reg_q(5):Q (r) + 0.143 net: i_SIU/I2CIF_INST/nx59247z8 2.932 i_SIU/I2CIF_INST/ix56256z4192:C (r) + 0.173 cell: ADLIB:AXOI4 3.105 i_SIU/I2CIF_INST/ix56256z4192:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx56256z1 3.229 i_SIU/I2CIF_INST/reg_q(5):D (r) 3.229 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.641 net: i_SIU/tx_clk_2b 2.601 i_SIU/I2CIF_INST/reg_q(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.601 i_SIU/I2CIF_INST/reg_q(5):D 2.601 data required time Expanded Path 8 From: i_SIU/I2CIF_INST/reg_q(3):CLK To: i_SIU/I2CIF_INST/reg_q(3):D data arrival time 3.229 data required time - 2.601 slack 0.628 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.623 net: i_SIU/tx_clk_2b 2.583 i_SIU/I2CIF_INST/reg_q(3):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.789 i_SIU/I2CIF_INST/reg_q(3):Q (r) + 0.143 net: i_SIU/I2CIF_INST/nx59247z6 2.932 i_SIU/I2CIF_INST/ix54262z4192:C (r) + 0.173 cell: ADLIB:AXOI4 3.105 i_SIU/I2CIF_INST/ix54262z4192:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx54262z1 3.229 i_SIU/I2CIF_INST/reg_q(3):D (r) 3.229 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.641 net: i_SIU/tx_clk_2b 2.601 i_SIU/I2CIF_INST/reg_q(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.601 i_SIU/I2CIF_INST/reg_q(3):D 2.601 data required time Expanded Path 9 From: i_SIU/modgen_counter_slot_timer_reg_q(1):CLK To: i_SIU/reg_b_led_update:D data arrival time 3.238 data required time - 2.596 slack 0.642 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.619 net: i_SIU/tx_clk_2b 2.579 i_SIU/modgen_counter_slot_timer_reg_q(1):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.785 i_SIU/modgen_counter_slot_timer_reg_q(1):Q (r) + 0.143 net: i_SIU/slot_timer_1_ 2.928 i_SIU/b_led_update_5n11s1:A (r) + 0.186 cell: ADLIB:AND3 3.114 i_SIU/b_led_update_5n11s1:Y (r) + 0.124 net: i_SIU/b_led_update_5n11s1 3.238 i_SIU/reg_b_led_update:D (r) 3.238 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.636 net: i_SIU/tx_clk_2b 2.596 i_SIU/reg_b_led_update:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.596 i_SIU/reg_b_led_update:D 2.596 data required time Expanded Path 10 From: i_SIU/reg_blink_timer(13):CLK To: i_SIU/reg_blink_timer(13):D data arrival time 3.246 data required time - 2.599 slack 0.647 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.621 net: i_SIU/tx_clk_2b 2.581 i_SIU/reg_blink_timer(13):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.787 i_SIU/reg_blink_timer(13):Q (r) + 0.151 net: i_SIU/blink_timer_13_ 2.938 i_SIU/ix60910z21034:B (r) + 0.184 cell: ADLIB:XA1C 3.122 i_SIU/ix60910z21034:Y (r) + 0.124 net: i_SIU/nx60910z1 3.246 i_SIU/reg_blink_timer(13):D (r) 3.246 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.639 net: i_SIU/tx_clk_2b 2.599 i_SIU/reg_blink_timer(13):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.599 i_SIU/reg_blink_timer(13):D 2.599 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(1):D Delay (ns): 3.705 Slack (ns): Arrival (ns): 3.705 Required (ns): Hold (ns): 0.000 External Hold (ns): -0.468 Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Delay (ns): 3.726 Slack (ns): Arrival (ns): 3.726 Required (ns): Hold (ns): 0.000 External Hold (ns): -0.488 Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Delay (ns): 4.314 Slack (ns): Arrival (ns): 4.314 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.079 Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Delay (ns): 4.410 Slack (ns): Arrival (ns): 4.410 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.186 Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Delay (ns): 4.440 Slack (ns): Arrival (ns): 4.440 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.198 Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(1):D Delay (ns): 4.436 Slack (ns): Arrival (ns): 4.436 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.212 Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Delay (ns): 4.482 Slack (ns): Arrival (ns): 4.482 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.244 Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Delay (ns): 4.486 Slack (ns): Arrival (ns): 4.486 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.248 Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Delay (ns): 4.557 Slack (ns): Arrival (ns): 4.557 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.319 Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(5):D Delay (ns): 5.114 Slack (ns): Arrival (ns): 5.114 Required (ns): Hold (ns): 0.000 External Hold (ns): -1.877 Expanded Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(1):D data arrival time 3.705 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 2.600 net: SDA_ID_i 3.084 i_SIU/I2CIF_INST/ix31571z50932:B (f) + 0.128 cell: ADLIB:NAND3A 3.212 i_SIU/I2CIF_INST/ix31571z50932:Y (r) + 0.125 net: i_SIU/I2CIF_INST/nx31571z3 3.337 i_SIU/I2CIF_INST/ix31571z24337:B (r) + 0.249 cell: ADLIB:NAND3 3.586 i_SIU/I2CIF_INST/ix31571z24337:Y (f) + 0.119 net: i_SIU/I2CIF_INST/nx31571z1 3.705 i_SIU/I2CIF_INST/reg_i2c_present(1):D (f) 3.705 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.778 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(1):D Expanded Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D data arrival time 3.726 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 2.909 net: SDA_ID_i 3.393 i_SIU/I2CIF_INST/ix10529z14896:A (f) + 0.215 cell: ADLIB:MX2 3.608 i_SIU/I2CIF_INST/ix10529z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx10529z1 3.726 i_SIU/I2CIF_INST/reg_i2c_rddata(2):D (f) 3.726 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.779 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Expanded Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D data arrival time 4.314 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.497 net: SDA_ID_i 3.981 i_SIU/I2CIF_INST/ix14517z14896:A (f) + 0.215 cell: ADLIB:MX2 4.196 i_SIU/I2CIF_INST/ix14517z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx14517z1 4.314 i_SIU/I2CIF_INST/reg_i2c_rddata(6):D (f) 4.314 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.776 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Expanded Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D data arrival time 4.410 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.595 net: SDA_ID_i 4.079 i_SIU/I2CIF_INST/ix11526z14896:A (f) + 0.215 cell: ADLIB:MX2 4.294 i_SIU/I2CIF_INST/ix11526z14896:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx11526z1 4.410 i_SIU/I2CIF_INST/reg_i2c_rddata(3):D (f) 4.410 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.765 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Expanded Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D data arrival time 4.440 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.623 net: SDA_ID_i 4.107 i_SIU/I2CIF_INST/ix8535z14896:A (f) + 0.215 cell: ADLIB:MX2 4.322 i_SIU/I2CIF_INST/ix8535z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx8535z1 4.440 i_SIU/I2CIF_INST/reg_i2c_rddata(0):D (f) 4.440 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.783 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Expanded Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(1):D data arrival time 4.436 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.619 net: SDA_ID_i 4.103 i_SIU/I2CIF_INST/ix9532z14896:A (f) + 0.215 cell: ADLIB:MX2 4.318 i_SIU/I2CIF_INST/ix9532z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx9532z1 4.436 i_SIU/I2CIF_INST/reg_i2c_rddata(1):D (f) 4.436 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.765 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(1):D Expanded Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D data arrival time 4.482 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.665 net: SDA_ID_i 4.149 i_SIU/I2CIF_INST/ix15514z14896:A (f) + 0.215 cell: ADLIB:MX2 4.364 i_SIU/I2CIF_INST/ix15514z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx15514z1 4.482 i_SIU/I2CIF_INST/reg_i2c_rddata(7):D (f) 4.482 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.779 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Expanded Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D data arrival time 4.486 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.669 net: SDA_ID_i 4.153 i_SIU/I2CIF_INST/ix12523z14896:A (f) + 0.215 cell: ADLIB:MX2 4.368 i_SIU/I2CIF_INST/ix12523z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx12523z1 4.486 i_SIU/I2CIF_INST/reg_i2c_rddata(4):D (f) 4.486 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.779 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Expanded Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D data arrival time 4.557 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.742 net: SDA_ID_i 4.226 i_SIU/I2CIF_INST/ix13520z14896:A (f) + 0.215 cell: ADLIB:MX2 4.441 i_SIU/I2CIF_INST/ix13520z14896:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx13520z1 4.557 i_SIU/I2CIF_INST/reg_i2c_rddata(5):D (f) 4.557 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.779 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Expanded Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(5):D data arrival time 5.114 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 3.612 net: SDA_ID_i 4.096 i_SIU/I2CIF_INST/ix29577z26293:A (f) + 0.219 cell: ADLIB:MX2C 4.315 i_SIU/I2CIF_INST/ix29577z26293:Y (r) + 0.125 net: i_SIU/I2CIF_INST/nx29577z3 4.440 i_SIU/I2CIF_INST/ix27583z24339:B (r) + 0.205 cell: ADLIB:NAND2 4.645 i_SIU/I2CIF_INST/ix27583z24339:Y (f) + 0.119 net: i_SIU/I2CIF_INST/nx27583z2 4.764 i_SIU/I2CIF_INST/ix27583z40557:C (f) + 0.225 cell: ADLIB:AO1C 4.989 i_SIU/I2CIF_INST/ix27583z40557:Y (r) + 0.125 net: i_SIU/I2CIF_INST/nx27583z1 5.114 i_SIU/I2CIF_INST/reg_i2c_present(5):D (r) 5.114 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.139 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.778 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(5):D END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: i_SIU/reg_led4:CLK To: LED_SIU(4) Delay (ns): 3.344 Slack (ns): Arrival (ns): 5.921 Required (ns): Clock to Out (ns): 5.921 Path 2 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID Delay (ns): 4.040 Slack (ns): Arrival (ns): 6.617 Required (ns): Clock to Out (ns): 6.617 Path 3 From: i_SIU/reg_led3:CLK To: LED_SIU(3) Delay (ns): 4.301 Slack (ns): Arrival (ns): 6.878 Required (ns): Clock to Out (ns): 6.878 Path 4 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID Delay (ns): 4.413 Slack (ns): Arrival (ns): 6.990 Required (ns): Clock to Out (ns): 6.990 Path 5 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID Delay (ns): 4.433 Slack (ns): Arrival (ns): 7.012 Required (ns): Clock to Out (ns): 7.012 Expanded Path 1 From: i_SIU/reg_led4:CLK To: LED_SIU(4) data arrival time 5.921 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.617 net: i_SIU/tx_clk_2b 2.577 i_SIU/reg_led4:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.783 i_SIU/reg_led4:Q (r) + 0.960 net: LED_SIU_i_4_ 3.743 genblk5[4].leds_siu_U1/U0/U1:D (r) + 0.231 cell: ADLIB:IOTRI_OB_EB 3.974 genblk5[4].leds_siu_U1/U0/U1:DOUT (r) + 0.000 net: genblk5[4]_leds_siu_U1/U0/NET1 3.974 genblk5[4].leds_siu_U1/U0/U0:D (r) + 1.947 cell: ADLIB:IOPAD_TRI 5.921 genblk5[4].leds_siu_U1/U0/U0:PAD (r) + 0.000 net: LED_SIU_4_ 5.921 LED_SIU(4) (r) 5.921 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(4) (r) Expanded Path 2 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID data arrival time 6.617 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.617 net: i_SIU/tx_clk_2b 2.577 i_SIU/I2CIF_INST/reg_s_sda_ena:CLK (r) + 0.256 cell: ADLIB:DFN1P0 2.833 i_SIU/I2CIF_INST/reg_s_sda_ena:Q (f) + 2.564 net: SDA_ID_e 5.397 bbuf_SDA_ID/U0/U1:E (f) + 0.145 cell: ADLIB:IOBI_IB_OB_EB 5.542 bbuf_SDA_ID/U0/U1:EOUT (f) + 0.000 net: bbuf_SDA_ID/U0/NET2 5.542 bbuf_SDA_ID/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 6.617 bbuf_SDA_ID/U0/U0:PAD (r) + 0.000 net: SDA_ID 6.617 SDA_ID (r) 6.617 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (r) Expanded Path 3 From: i_SIU/reg_led3:CLK To: LED_SIU(3) data arrival time 6.878 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.617 net: i_SIU/tx_clk_2b 2.577 i_SIU/reg_led3:CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.783 i_SIU/reg_led3:Q (r) + 1.935 net: LED_SIU_i_3_ 4.718 genblk5[3].leds_siu_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 4.931 genblk5[3].leds_siu_U1/U0/U1:DOUT (r) + 0.000 net: genblk5[3]_leds_siu_U1/U0/NET1 4.931 genblk5[3].leds_siu_U1/U0/U0:D (r) + 1.947 cell: ADLIB:IOPAD_TRI 6.878 genblk5[3].leds_siu_U1/U0/U0:PAD (r) + 0.000 net: LED_SIU_3_ 6.878 LED_SIU(3) (r) 6.878 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(3) (r) Expanded Path 4 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID data arrival time 6.990 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.617 net: i_SIU/tx_clk_2b 2.577 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.783 i_SIU/I2CIF_INST/reg_s_sda_out:Q (r) + 2.393 net: SDA_ID_o 5.176 bbuf_SDA_ID/U0/U1:D (r) + 0.213 cell: ADLIB:IOBI_IB_OB_EB 5.389 bbuf_SDA_ID/U0/U1:DOUT (r) + 0.000 net: bbuf_SDA_ID/U0/NET1 5.389 bbuf_SDA_ID/U0/U0:D (r) + 1.601 cell: ADLIB:IOPAD_BI 6.990 bbuf_SDA_ID/U0/U0:PAD (r) + 0.000 net: SDA_ID 6.990 SDA_ID (r) 6.990 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (r) Expanded Path 5 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID data arrival time 7.012 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.705 net: i_SIU/tx_clk_2 1.705 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.960 i_SIU/cbuf_tx_clk_2:Y (r) + 0.619 net: i_SIU/tx_clk_2b 2.579 i_SIU/I2CIF_INST/reg_i2c_scl:CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.785 i_SIU/I2CIF_INST/reg_i2c_scl:Q (r) + 2.413 net: SCL_ID_i 5.198 obuf_SCL_ID_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 5.411 obuf_SCL_ID_U1/U0/U1:DOUT (r) + 0.000 net: obuf_SCL_ID_U1/U0/NET1 5.411 obuf_SCL_ID_U1/U0/U0:D (r) + 1.601 cell: ADLIB:IOPAD_TRI 7.012 obuf_SCL_ID_U1/U0/U0:PAD (r) + 0.000 net: SCL_ID 7.012 SCL_ID (r) 7.012 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SCL_ID (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_adc/cdiv_reg_q:Q SET Register to Register Path 1 From: i_adc/ds_tsens/reg_valid:CLK To: i_adc/ds_tsens/reg_start:D Delay (ns): 0.330 Slack (ns): 0.308 Arrival (ns): 1.947 Required (ns): 1.639 Hold (ns): 0.000 Path 2 From: i_adc/ds_tsens/ix30739z54531:CLK To: i_adc/ds_tsens/ix30739z21824:D Delay (ns): 0.357 Slack (ns): 0.338 Arrival (ns): 1.963 Required (ns): 1.625 Hold (ns): 0.000 Path 3 From: i_adc/ds_tsens/ix30985z54530:CLK To: i_adc/ds_tsens/ix30985z21823:D Delay (ns): 0.363 Slack (ns): 0.339 Arrival (ns): 1.964 Required (ns): 1.625 Hold (ns): 0.000 Path 4 From: i_adc/ds_tsens/ix32979z54530:CLK To: i_adc/ds_tsens/ix32979z21823:D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 1.978 Required (ns): 1.639 Hold (ns): 0.000 Path 5 From: i_adc/ds_tsens/bsl/ts/ix32979z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix32979z21823:D Delay (ns): 0.357 Slack (ns): 0.341 Arrival (ns): 1.954 Required (ns): 1.613 Hold (ns): 0.000 Path 6 From: i_adc/ds_tsens/bsl/ts/ix29988z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix29988z21823:D Delay (ns): 0.357 Slack (ns): 0.341 Arrival (ns): 1.954 Required (ns): 1.613 Hold (ns): 0.000 Path 7 From: i_adc/ds_tsens/bsl/ts/ix31982z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix31982z21823:D Delay (ns): 0.357 Slack (ns): 0.341 Arrival (ns): 1.954 Required (ns): 1.613 Hold (ns): 0.000 Path 8 From: i_adc/ds_tsens/bsl/ts/ix32979z54535:CLK To: i_adc/ds_tsens/bsl/ts/ix29988z21823:E Delay (ns): 0.360 Slack (ns): 0.347 Arrival (ns): 1.960 Required (ns): 1.613 Hold (ns): 0.000 Path 9 From: i_adc/ds_tsens/ix32979z54531:CLK To: i_adc/ds_tsens/ix30985z21823:E Delay (ns): 0.375 Slack (ns): 0.356 Arrival (ns): 1.981 Required (ns): 1.625 Hold (ns): 0.000 Path 10 From: i_adc/ds_tsens/ix32979z54531:CLK To: i_adc/ds_tsens/ix30739z21824:E Delay (ns): 0.375 Slack (ns): 0.356 Arrival (ns): 1.981 Required (ns): 1.625 Hold (ns): 0.000 Expanded Path 1 From: i_adc/ds_tsens/reg_valid:CLK To: i_adc/ds_tsens/reg_start:D data arrival time 1.947 data required time - 1.639 slack 0.308 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.635 net: i_adc/clk1MHz_b 1.617 i_adc/ds_tsens/reg_valid:CLK (r) + 0.206 cell: ADLIB:DFN1C1 1.823 i_adc/ds_tsens/reg_valid:Q (r) + 0.124 net: i_adc/ds_tsens/valid 1.947 i_adc/ds_tsens/reg_start:D (r) 1.947 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.657 net: i_adc/clk1MHz_b 1.639 i_adc/ds_tsens/reg_start:CLK (r) + 0.000 Library hold time: ADLIB:DFN1 1.639 i_adc/ds_tsens/reg_start:D 1.639 data required time Expanded Path 2 From: i_adc/ds_tsens/ix30739z54531:CLK To: i_adc/ds_tsens/ix30739z21824:D data arrival time 1.963 data required time - 1.625 slack 0.338 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.624 net: i_adc/clk1MHz_b 1.606 i_adc/ds_tsens/ix30739z54531:CLK (r) + 0.206 cell: ADLIB:DFN1 1.812 i_adc/ds_tsens/ix30739z54531:Q (r) + 0.151 net: i_adc/ds_tsens/rd_data1_2_ 1.963 i_adc/ds_tsens/ix30739z21824:D (r) 1.963 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.643 net: i_adc/clk1MHz_b 1.625 i_adc/ds_tsens/ix30739z21824:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.625 i_adc/ds_tsens/ix30739z21824:D 1.625 data required time Expanded Path 3 From: i_adc/ds_tsens/ix30985z54530:CLK To: i_adc/ds_tsens/ix30985z21823:D data arrival time 1.964 data required time - 1.625 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.619 net: i_adc/clk1MHz_b 1.601 i_adc/ds_tsens/ix30985z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.807 i_adc/ds_tsens/ix30985z54530:Q (r) + 0.157 net: i_adc/ds_tsens/rd_data1_3_ 1.964 i_adc/ds_tsens/ix30985z21823:D (r) 1.964 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.643 net: i_adc/clk1MHz_b 1.625 i_adc/ds_tsens/ix30985z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.625 i_adc/ds_tsens/ix30985z21823:D 1.625 data required time Expanded Path 4 From: i_adc/ds_tsens/ix32979z54530:CLK To: i_adc/ds_tsens/ix32979z21823:D data arrival time 1.978 data required time - 1.639 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.639 net: i_adc/clk1MHz_b 1.621 i_adc/ds_tsens/ix32979z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.827 i_adc/ds_tsens/ix32979z54530:Q (r) + 0.151 net: i_adc/ds_tsens/rd_data1_1_ 1.978 i_adc/ds_tsens/ix32979z21823:D (r) 1.978 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.657 net: i_adc/clk1MHz_b 1.639 i_adc/ds_tsens/ix32979z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.639 i_adc/ds_tsens/ix32979z21823:D 1.639 data required time Expanded Path 5 From: i_adc/ds_tsens/bsl/ts/ix32979z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix32979z21823:D data arrival time 1.954 data required time - 1.613 slack 0.341 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.615 net: i_adc/clk1MHz_b 1.597 i_adc/ds_tsens/bsl/ts/ix32979z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.803 i_adc/ds_tsens/bsl/ts/ix32979z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_2_ 1.954 i_adc/ds_tsens/bsl/ts/ix32979z21823:D (r) 1.954 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.631 net: i_adc/clk1MHz_b 1.613 i_adc/ds_tsens/bsl/ts/ix32979z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.613 i_adc/ds_tsens/bsl/ts/ix32979z21823:D 1.613 data required time Expanded Path 6 From: i_adc/ds_tsens/bsl/ts/ix29988z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix29988z21823:D data arrival time 1.954 data required time - 1.613 slack 0.341 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.615 net: i_adc/clk1MHz_b 1.597 i_adc/ds_tsens/bsl/ts/ix29988z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.803 i_adc/ds_tsens/bsl/ts/ix29988z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_0_ 1.954 i_adc/ds_tsens/bsl/ts/ix29988z21823:D (r) 1.954 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.631 net: i_adc/clk1MHz_b 1.613 i_adc/ds_tsens/bsl/ts/ix29988z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.613 i_adc/ds_tsens/bsl/ts/ix29988z21823:D 1.613 data required time Expanded Path 7 From: i_adc/ds_tsens/bsl/ts/ix31982z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix31982z21823:D data arrival time 1.954 data required time - 1.613 slack 0.341 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.615 net: i_adc/clk1MHz_b 1.597 i_adc/ds_tsens/bsl/ts/ix31982z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.803 i_adc/ds_tsens/bsl/ts/ix31982z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_3_ 1.954 i_adc/ds_tsens/bsl/ts/ix31982z21823:D (r) 1.954 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.631 net: i_adc/clk1MHz_b 1.613 i_adc/ds_tsens/bsl/ts/ix31982z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.613 i_adc/ds_tsens/bsl/ts/ix31982z21823:D 1.613 data required time Expanded Path 8 From: i_adc/ds_tsens/bsl/ts/ix32979z54535:CLK To: i_adc/ds_tsens/bsl/ts/ix29988z21823:E data arrival time 1.960 data required time - 1.613 slack 0.347 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.618 net: i_adc/clk1MHz_b 1.600 i_adc/ds_tsens/bsl/ts/ix32979z54535:CLK (r) + 0.206 cell: ADLIB:DFN1 1.806 i_adc/ds_tsens/bsl/ts/ix32979z54535:Q (r) + 0.154 net: i_adc/ds_tsens/bsl/ts/nx32979z6 1.960 i_adc/ds_tsens/bsl/ts/ix29988z21823:E (r) 1.960 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.631 net: i_adc/clk1MHz_b 1.613 i_adc/ds_tsens/bsl/ts/ix29988z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.613 i_adc/ds_tsens/bsl/ts/ix29988z21823:E 1.613 data required time Expanded Path 9 From: i_adc/ds_tsens/ix32979z54531:CLK To: i_adc/ds_tsens/ix30985z21823:E data arrival time 1.981 data required time - 1.625 slack 0.356 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.624 net: i_adc/clk1MHz_b 1.606 i_adc/ds_tsens/ix32979z54531:CLK (r) + 0.206 cell: ADLIB:DFN1 1.812 i_adc/ds_tsens/ix32979z54531:Q (r) + 0.169 net: i_adc/ds_tsens/nx32979z3 1.981 i_adc/ds_tsens/ix30985z21823:E (r) 1.981 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.643 net: i_adc/clk1MHz_b 1.625 i_adc/ds_tsens/ix30985z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.625 i_adc/ds_tsens/ix30985z21823:E 1.625 data required time Expanded Path 10 From: i_adc/ds_tsens/ix32979z54531:CLK To: i_adc/ds_tsens/ix30739z21824:E data arrival time 1.981 data required time - 1.625 slack 0.356 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.624 net: i_adc/clk1MHz_b 1.606 i_adc/ds_tsens/ix32979z54531:CLK (r) + 0.206 cell: ADLIB:DFN1 1.812 i_adc/ds_tsens/ix32979z54531:Q (r) + 0.169 net: i_adc/ds_tsens/nx32979z3 1.981 i_adc/ds_tsens/ix30739z21824:E (r) 1.981 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.643 net: i_adc/clk1MHz_b 1.625 i_adc/ds_tsens/ix30739z21824:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.625 i_adc/ds_tsens/ix30739z21824:E 1.625 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D Delay (ns): 2.785 Slack (ns): Arrival (ns): 2.785 Required (ns): Hold (ns): 0.000 External Hold (ns): -0.792 Expanded Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D data arrival time 2.785 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TSENS (f) + 0.000 net: TSENS 0.000 bbuf_TSENS/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_TSENS/U0/U0:Y (f) + 0.000 net: bbuf_TSENS/U0/NET3 0.470 bbuf_TSENS/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_TSENS/U0/U1:Y (f) + 1.968 net: TSENS_i 2.452 i_adc/ds_tsens/bsl/ts/ix5225z14896:B (f) + 0.215 cell: ADLIB:MX2 2.667 i_adc/ds_tsens/bsl/ts/ix5225z14896:Y (f) + 0.118 net: i_adc/ds_tsens/bsl/ts/nx5225z1 2.785 i_adc/ds_tsens/bsl/ts/reg_retbit:D (f) 2.785 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.762 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_retbit:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_retbit:D END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS Delay (ns): 3.699 Slack (ns): Arrival (ns): 5.294 Required (ns): Clock to Out (ns): 5.294 Path 2 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS Delay (ns): 4.288 Slack (ns): Arrival (ns): 5.892 Required (ns): Clock to Out (ns): 5.892 Expanded Path 1 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS data arrival time 5.294 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.613 net: i_adc/clk1MHz_b 1.595 i_adc/ds_tsens/bsl/ts/reg_oe:CLK (r) + 0.256 cell: ADLIB:DFN1 1.851 i_adc/ds_tsens/bsl/ts/reg_oe:Q (f) + 0.118 net: i_adc/ds_tsens/bsl/oe_i 1.969 i_adc/ds_tsens/bsl/oe:B (f) + 0.226 cell: ADLIB:NAND2B 2.195 i_adc/ds_tsens/bsl/oe:Y (f) + 1.879 net: TSENS_e 4.074 bbuf_TSENS/U0/U1:E (f) + 0.145 cell: ADLIB:IOBI_IB_OB_EB 4.219 bbuf_TSENS/U0/U1:EOUT (f) + 0.000 net: bbuf_TSENS/U0/NET2 4.219 bbuf_TSENS/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 5.294 bbuf_TSENS/U0/U0:PAD (r) + 0.000 net: TSENS 5.294 TSENS (r) 5.294 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (r) Expanded Path 2 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS data arrival time 5.892 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.717 net: i_adc/clk1MHz 0.717 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.982 i_adc/cbuf_1MHz:Y (r) + 0.622 net: i_adc/clk1MHz_b 1.604 i_adc/ds_tsens/bsl/reg_hold_high:CLK (r) + 0.256 cell: ADLIB:DFN1C1 1.860 i_adc/ds_tsens/bsl/reg_hold_high:Q (f) + 0.757 net: TSENS_o 2.617 i_adc/ds_tsens/bsl/oe:A (f) + 0.176 cell: ADLIB:NAND2B 2.793 i_adc/ds_tsens/bsl/oe:Y (f) + 1.879 net: TSENS_e 4.672 bbuf_TSENS/U0/U1:E (f) + 0.145 cell: ADLIB:IOBI_IB_OB_EB 4.817 bbuf_TSENS/U0/U1:EOUT (f) + 0.000 net: bbuf_TSENS/U0/NET2 4.817 bbuf_TSENS/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 5.892 bbuf_TSENS/U0/U0:PAD (r) + 0.000 net: TSENS 5.892 TSENS (r) 5.892 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: i_adc/ds_tsens/reg_q(8):CLR Delay (ns): 3.601 Slack (ns): Arrival (ns): 3.601 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.608 Path 2 From: RST_n To: i_adc/ds_tsens/reg_q(9):CLR Delay (ns): 3.671 Slack (ns): Arrival (ns): 3.671 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.678 Path 3 From: RST_n To: i_adc/ds_tsens/bsl/reg_cmd_bit(1):CLR Delay (ns): 3.778 Slack (ns): Arrival (ns): 3.778 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.787 Path 4 From: RST_n To: i_adc/ds_tsens/reg_q(7):CLR Delay (ns): 3.845 Slack (ns): Arrival (ns): 3.845 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.846 Path 5 From: RST_n To: i_adc/ds_tsens/reg_q(6):CLR Delay (ns): 3.850 Slack (ns): Arrival (ns): 3.850 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.851 Path 6 From: RST_n To: i_adc/ds_tsens/bsl/reg_valid:PRE Delay (ns): 3.866 Slack (ns): Arrival (ns): 3.866 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.869 Path 7 From: RST_n To: i_adc/ds_tsens/reg_q(10):CLR Delay (ns): 3.891 Slack (ns): Arrival (ns): 3.891 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.898 Path 8 From: RST_n To: i_adc/ds_tsens/reg_valid:CLR Delay (ns): 3.967 Slack (ns): Arrival (ns): 3.967 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.948 Path 9 From: RST_n To: i_adc/ds_tsens/ix10077z23817:CLR Delay (ns): 3.979 Slack (ns): Arrival (ns): 3.979 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.982 Path 10 From: RST_n To: i_adc/ds_tsens/reg_q(11):CLR Delay (ns): 4.034 Slack (ns): Arrival (ns): 4.034 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.041 Expanded Path 1 From: RST_n To: i_adc/ds_tsens/reg_q(8):CLR data arrival time 3.601 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.311 net: not_rst_n 3.601 i_adc/ds_tsens/reg_q(8):CLR (f) 3.601 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.762 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(8):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(8):CLR Expanded Path 2 From: RST_n To: i_adc/ds_tsens/reg_q(9):CLR data arrival time 3.671 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.381 net: not_rst_n 3.671 i_adc/ds_tsens/reg_q(9):CLR (f) 3.671 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.762 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(9):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(9):CLR Expanded Path 3 From: RST_n To: i_adc/ds_tsens/bsl/reg_cmd_bit(1):CLR data arrival time 3.778 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.488 net: not_rst_n 3.778 i_adc/ds_tsens/bsl/reg_cmd_bit(1):CLR (f) 3.778 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.760 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_cmd_bit(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_cmd_bit(1):CLR Expanded Path 4 From: RST_n To: i_adc/ds_tsens/reg_q(7):CLR data arrival time 3.845 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.555 net: not_rst_n 3.845 i_adc/ds_tsens/reg_q(7):CLR (f) 3.845 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.768 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(7):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(7):CLR Expanded Path 5 From: RST_n To: i_adc/ds_tsens/reg_q(6):CLR data arrival time 3.850 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.560 net: not_rst_n 3.850 i_adc/ds_tsens/reg_q(6):CLR (f) 3.850 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.768 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(6):CLR Expanded Path 6 From: RST_n To: i_adc/ds_tsens/bsl/reg_valid:PRE data arrival time 3.866 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.576 net: not_rst_n 3.866 i_adc/ds_tsens/bsl/reg_valid:PRE (f) 3.866 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.766 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_valid:CLK (r) + 0.000 Library removal time: ADLIB:DFN1P1 N/C i_adc/ds_tsens/bsl/reg_valid:PRE Expanded Path 7 From: RST_n To: i_adc/ds_tsens/reg_q(10):CLR data arrival time 3.891 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.601 net: not_rst_n 3.891 i_adc/ds_tsens/reg_q(10):CLR (f) 3.891 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.762 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(10):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(10):CLR Expanded Path 8 From: RST_n To: i_adc/ds_tsens/reg_valid:CLR data arrival time 3.967 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.677 net: not_rst_n 3.967 i_adc/ds_tsens/reg_valid:CLR (f) 3.967 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.788 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_valid:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_valid:CLR Expanded Path 9 From: RST_n To: i_adc/ds_tsens/ix10077z23817:CLR data arrival time 3.979 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.689 net: not_rst_n 3.979 i_adc/ds_tsens/ix10077z23817:CLR (f) 3.979 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.766 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/ix10077z23817:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/ix10077z23817:CLR Expanded Path 10 From: RST_n To: i_adc/ds_tsens/reg_q(11):CLR data arrival time 4.034 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 1.744 net: not_rst_n 4.034 i_adc/ds_tsens/reg_q(11):CLR (f) 4.034 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.899 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.762 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(11):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(11):CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLA SET Register to Register Path 1 From: i_SIU/FEEIF/reg_bdir_present(8):CLK To: i_SIU/FEEIF/reg_bdir_present(9):D Delay (ns): 0.335 Slack (ns): 0.290 Arrival (ns): 4.877 Required (ns): 4.587 Hold (ns): 0.000 Path 2 From: i_cbb/sys_config0/reg_scsn_din(0):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(0):D Delay (ns): 0.335 Slack (ns): 0.291 Arrival (ns): 4.881 Required (ns): 4.590 Hold (ns): 0.000 Path 3 From: i_cbb/sys_config0/reg_scsn_req_ta:CLK To: i_cbb/tim_ana/reg_scsn_req_r:D Delay (ns): 0.330 Slack (ns): 0.297 Arrival (ns): 4.884 Required (ns): 4.587 Hold (ns): 0.000 Path 4 From: i_cbb/sys_config0/reg_scsn_dout_r(23):CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(23):D Delay (ns): 0.330 Slack (ns): 0.300 Arrival (ns): 4.918 Required (ns): 4.618 Hold (ns): 0.000 Path 5 From: i_cbb/sys_config0/reg_scsn_din(28):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(28):D Delay (ns): 0.330 Slack (ns): 0.300 Arrival (ns): 4.918 Required (ns): 4.618 Hold (ns): 0.000 Path 6 From: i_cbb/sys_config0/reg_scsn_din(19):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(19):D Delay (ns): 0.330 Slack (ns): 0.300 Arrival (ns): 4.918 Required (ns): 4.618 Hold (ns): 0.000 Path 7 From: i_cbb/sys_config0/reg_scsn_dout_r(22):CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(22):D Delay (ns): 0.330 Slack (ns): 0.300 Arrival (ns): 4.918 Required (ns): 4.618 Hold (ns): 0.000 Path 8 From: i_cbb/sys_config0/reg_scsn_din(24):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(24):D Delay (ns): 0.330 Slack (ns): 0.300 Arrival (ns): 4.918 Required (ns): 4.618 Hold (ns): 0.000 Path 9 From: i_cbb/sys_config0/reg_scsn_dout_r(24):CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(24):D Delay (ns): 0.330 Slack (ns): 0.300 Arrival (ns): 4.918 Required (ns): 4.618 Hold (ns): 0.000 Path 10 From: i_cbb/sys_config0/reg_scsn_din(11):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(11):D Delay (ns): 0.330 Slack (ns): 0.303 Arrival (ns): 4.905 Required (ns): 4.602 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/FEEIF/reg_bdir_present(8):CLK To: i_SIU/FEEIF/reg_bdir_present(9):D data arrival time 4.877 data required time - 4.587 slack 0.290 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.621 net: CLK40out 4.542 i_SIU/FEEIF/reg_bdir_present(8):CLK (r) + 0.206 cell: ADLIB:DFN1C0 4.748 i_SIU/FEEIF/reg_bdir_present(8):Q (r) + 0.129 net: i_SIU/FEEIF/bdir_present_8_ 4.877 i_SIU/FEEIF/reg_bdir_present(9):D (r) 4.877 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.666 net: CLK40out 4.587 i_SIU/FEEIF/reg_bdir_present(9):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 4.587 i_SIU/FEEIF/reg_bdir_present(9):D 4.587 data required time Expanded Path 2 From: i_cbb/sys_config0/reg_scsn_din(0):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(0):D data arrival time 4.881 data required time - 4.590 slack 0.291 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.625 net: CLK40out 4.546 i_cbb/sys_config0/reg_scsn_din(0):CLK (r) + 0.206 cell: ADLIB:DFN1E1 4.752 i_cbb/sys_config0/reg_scsn_din(0):Q (r) + 0.129 net: i_cbb/scsn_bus_din_0_ 4.881 i_cbb/scsn_inst_nw_apl/reg_read_data(0):D (r) 4.881 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.669 net: CLK40out 4.590 i_cbb/scsn_inst_nw_apl/reg_read_data(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 4.590 i_cbb/scsn_inst_nw_apl/reg_read_data(0):D 4.590 data required time Expanded Path 3 From: i_cbb/sys_config0/reg_scsn_req_ta:CLK To: i_cbb/tim_ana/reg_scsn_req_r:D data arrival time 4.884 data required time - 4.587 slack 0.297 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.633 net: CLK40out 4.554 i_cbb/sys_config0/reg_scsn_req_ta:CLK (r) + 0.206 cell: ADLIB:DFN1 4.760 i_cbb/sys_config0/reg_scsn_req_ta:Q (r) + 0.124 net: i_cbb/scsn_bus_req_ta 4.884 i_cbb/tim_ana/reg_scsn_req_r:D (r) 4.884 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.666 net: CLK40out 4.587 i_cbb/tim_ana/reg_scsn_req_r:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.587 i_cbb/tim_ana/reg_scsn_req_r:D 4.587 data required time Expanded Path 4 From: i_cbb/sys_config0/reg_scsn_dout_r(23):CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(23):D data arrival time 4.918 data required time - 4.618 slack 0.300 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.667 net: CLK40out 4.588 i_cbb/sys_config0/reg_scsn_dout_r(23):CLK (r) + 0.206 cell: ADLIB:DFN1 4.794 i_cbb/sys_config0/reg_scsn_dout_r(23):Q (r) + 0.124 net: i_cbb/scsn_bus_dout_r_23_ 4.918 i_cbb/sys_config0/reg_syscfg_wdata_r(23):D (r) 4.918 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.697 net: CLK40out 4.618 i_cbb/sys_config0/reg_syscfg_wdata_r(23):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.618 i_cbb/sys_config0/reg_syscfg_wdata_r(23):D 4.618 data required time Expanded Path 5 From: i_cbb/sys_config0/reg_scsn_din(28):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(28):D data arrival time 4.918 data required time - 4.618 slack 0.300 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.667 net: CLK40out 4.588 i_cbb/sys_config0/reg_scsn_din(28):CLK (r) + 0.206 cell: ADLIB:DFN1E1 4.794 i_cbb/sys_config0/reg_scsn_din(28):Q (r) + 0.124 net: i_cbb/scsn_bus_din_28_ 4.918 i_cbb/scsn_inst_nw_apl/reg_read_data(28):D (r) 4.918 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.697 net: CLK40out 4.618 i_cbb/scsn_inst_nw_apl/reg_read_data(28):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 4.618 i_cbb/scsn_inst_nw_apl/reg_read_data(28):D 4.618 data required time Expanded Path 6 From: i_cbb/sys_config0/reg_scsn_din(19):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(19):D data arrival time 4.918 data required time - 4.618 slack 0.300 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.667 net: CLK40out 4.588 i_cbb/sys_config0/reg_scsn_din(19):CLK (r) + 0.206 cell: ADLIB:DFN1E1 4.794 i_cbb/sys_config0/reg_scsn_din(19):Q (r) + 0.124 net: i_cbb/scsn_bus_din_19_ 4.918 i_cbb/scsn_inst_nw_apl/reg_read_data(19):D (r) 4.918 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.697 net: CLK40out 4.618 i_cbb/scsn_inst_nw_apl/reg_read_data(19):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 4.618 i_cbb/scsn_inst_nw_apl/reg_read_data(19):D 4.618 data required time Expanded Path 7 From: i_cbb/sys_config0/reg_scsn_dout_r(22):CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(22):D data arrival time 4.918 data required time - 4.618 slack 0.300 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.667 net: CLK40out 4.588 i_cbb/sys_config0/reg_scsn_dout_r(22):CLK (r) + 0.206 cell: ADLIB:DFN1 4.794 i_cbb/sys_config0/reg_scsn_dout_r(22):Q (r) + 0.124 net: i_cbb/scsn_bus_dout_r_22_ 4.918 i_cbb/sys_config0/reg_syscfg_wdata_r(22):D (r) 4.918 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.697 net: CLK40out 4.618 i_cbb/sys_config0/reg_syscfg_wdata_r(22):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.618 i_cbb/sys_config0/reg_syscfg_wdata_r(22):D 4.618 data required time Expanded Path 8 From: i_cbb/sys_config0/reg_scsn_din(24):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(24):D data arrival time 4.918 data required time - 4.618 slack 0.300 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.667 net: CLK40out 4.588 i_cbb/sys_config0/reg_scsn_din(24):CLK (r) + 0.206 cell: ADLIB:DFN1E1 4.794 i_cbb/sys_config0/reg_scsn_din(24):Q (r) + 0.124 net: i_cbb/scsn_bus_din_24_ 4.918 i_cbb/scsn_inst_nw_apl/reg_read_data(24):D (r) 4.918 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.697 net: CLK40out 4.618 i_cbb/scsn_inst_nw_apl/reg_read_data(24):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 4.618 i_cbb/scsn_inst_nw_apl/reg_read_data(24):D 4.618 data required time Expanded Path 9 From: i_cbb/sys_config0/reg_scsn_dout_r(24):CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(24):D data arrival time 4.918 data required time - 4.618 slack 0.300 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.667 net: CLK40out 4.588 i_cbb/sys_config0/reg_scsn_dout_r(24):CLK (r) + 0.206 cell: ADLIB:DFN1 4.794 i_cbb/sys_config0/reg_scsn_dout_r(24):Q (r) + 0.124 net: i_cbb/scsn_bus_dout_r_24_ 4.918 i_cbb/sys_config0/reg_syscfg_wdata_r(24):D (r) 4.918 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.697 net: CLK40out 4.618 i_cbb/sys_config0/reg_syscfg_wdata_r(24):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.618 i_cbb/sys_config0/reg_syscfg_wdata_r(24):D 4.618 data required time Expanded Path 10 From: i_cbb/sys_config0/reg_scsn_din(11):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(11):D data arrival time 4.905 data required time - 4.602 slack 0.303 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.654 net: CLK40out 4.575 i_cbb/sys_config0/reg_scsn_din(11):CLK (r) + 0.206 cell: ADLIB:DFN1E1 4.781 i_cbb/sys_config0/reg_scsn_din(11):Q (r) + 0.124 net: i_cbb/scsn_bus_din_11_ 4.905 i_cbb/scsn_inst_nw_apl/reg_read_data(11):D (r) 4.905 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.681 net: CLK40out 4.602 i_cbb/scsn_inst_nw_apl/reg_read_data(11):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 4.602 i_cbb/scsn_inst_nw_apl/reg_read_data(11):D 4.602 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SIU_SDA To: i_adc/sfp_rd_reg_dout(3):D Delay (ns): 1.689 Slack (ns): Arrival (ns): 1.689 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.990 Path 2 From: SFP_PRESENT To: i_adc/sfp_rd_reg_dout(4):D Delay (ns): 1.901 Slack (ns): Arrival (ns): 1.901 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.778 Path 3 From: TLMU_n(1) To: i_cbb/cbbr_top_1/reg_din_syn(1):D Delay (ns): 2.578 Slack (ns): Arrival (ns): 2.578 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.129 Path 4 From: TLMU_p(1) To: i_cbb/cbbr_top_1/reg_din_syn(1):D Delay (ns): 2.590 Slack (ns): Arrival (ns): 2.590 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.117 Path 5 From: ADC_SDO To: i_adc/adc/adci/reg_adc(0):D Delay (ns): 2.710 Slack (ns): Arrival (ns): 2.710 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.986 Path 6 From: TLMU_n(2) To: i_cbb/cbbr_top_1/reg_din_syn(2):D Delay (ns): 2.827 Slack (ns): Arrival (ns): 2.827 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.886 Path 7 From: TLMU_p(2) To: i_cbb/cbbr_top_1/reg_din_syn(2):D Delay (ns): 2.839 Slack (ns): Arrival (ns): 2.839 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.874 Path 8 From: TLMU_n(2) To: i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D Delay (ns): 2.903 Slack (ns): Arrival (ns): 2.903 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.807 Path 9 From: TLMU_n(0) To: i_cbb/cbbr_top_1/reg_din_syn(0):D Delay (ns): 2.922 Slack (ns): Arrival (ns): 2.922 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.803 Path 10 From: TLMU_p(2) To: i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D Delay (ns): 2.915 Slack (ns): Arrival (ns): 2.915 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.795 Expanded Path 1 From: SIU_SDA To: i_adc/sfp_rd_reg_dout(3):D data arrival time 1.689 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_SDA (f) + 0.000 net: SIU_SDA 0.000 bbuf_SIU_SDA/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SIU_SDA/U0/U0:Y (f) + 0.000 net: bbuf_SIU_SDA/U0/NET3 0.470 bbuf_SIU_SDA/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SIU_SDA/U0/U1:Y (f) + 1.205 net: SIU_SDA_i 1.689 i_adc/sfp_rd_reg_dout(3):D (f) 1.689 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.758 net: CLK40out N/C i_adc/sfp_rd_reg_dout(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 N/C i_adc/sfp_rd_reg_dout(3):D Expanded Path 2 From: SFP_PRESENT To: i_adc/sfp_rd_reg_dout(4):D data arrival time 1.901 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFP_PRESENT (f) + 0.000 net: SFP_PRESENT 0.000 ibuf_SFP_PRESENT_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFP_PRESENT_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFP_PRESENT_ib/U0/NET1 0.470 ibuf_SFP_PRESENT_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFP_PRESENT_ib/U0/U1:Y (f) + 1.417 net: SFP_PRESENT_i 1.901 i_adc/sfp_rd_reg_dout(4):D (f) 1.901 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.758 net: CLK40out N/C i_adc/sfp_rd_reg_dout(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 N/C i_adc/sfp_rd_reg_dout(4):D Expanded Path 3 From: TLMU_n(1) To: i_cbb/cbbr_top_1/reg_din_syn(1):D data arrival time 2.578 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(1) (f) + 0.000 net: TLMU_n_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 1.458 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.472 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (f) + 1.106 net: TLMU_i_1_ 2.578 i_cbb/cbbr_top_1/reg_din_syn(1):D (f) 2.578 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.786 net: CLK40out N/C i_cbb/cbbr_top_1/reg_din_syn(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 N/C i_cbb/cbbr_top_1/reg_din_syn(1):D Expanded Path 4 From: TLMU_p(1) To: i_cbb/cbbr_top_1/reg_din_syn(1):D data arrival time 2.590 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(1) (f) + 0.000 net: TLMU_p_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 1.470 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.484 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (f) + 1.106 net: TLMU_i_1_ 2.590 i_cbb/cbbr_top_1/reg_din_syn(1):D (f) 2.590 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.786 net: CLK40out N/C i_cbb/cbbr_top_1/reg_din_syn(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 N/C i_cbb/cbbr_top_1/reg_din_syn(1):D Expanded Path 5 From: ADC_SDO To: i_adc/adc/adci/reg_adc(0):D data arrival time 2.710 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 ADC_SDO (f) + 0.000 net: ADC_SDO 0.000 ibuf_ADC_SDO_ib/U0/U0:PAD (f) + 0.534 cell: ADLIB:IOPAD_IN 0.534 ibuf_ADC_SDO_ib/U0/U0:Y (f) + 0.000 net: ibuf_ADC_SDO_ib/U0/NET1 0.534 ibuf_ADC_SDO_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.548 ibuf_ADC_SDO_ib/U0/U1:Y (f) + 2.162 net: ADC_SDO_i 2.710 i_adc/adc/adci/reg_adc(0):D (f) 2.710 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.775 net: CLK40out N/C i_adc/adc/adci/reg_adc(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C i_adc/adc/adci/reg_adc(0):D Expanded Path 6 From: TLMU_n(2) To: i_cbb/cbbr_top_1/reg_din_syn(2):D data arrival time 2.827 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(2) (f) + 0.000 net: TLMU_n_2_ 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[2]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[2].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[2]_lvds_TLMU_U1/U0/NET1 1.458 tlmu_in[2].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.472 tlmu_in[2].lvds_TLMU_U1/U0/U1:Y (f) + 1.355 net: TLMU_i_2_ 2.827 i_cbb/cbbr_top_1/reg_din_syn(2):D (f) 2.827 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.792 net: CLK40out N/C i_cbb/cbbr_top_1/reg_din_syn(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 N/C i_cbb/cbbr_top_1/reg_din_syn(2):D Expanded Path 7 From: TLMU_p(2) To: i_cbb/cbbr_top_1/reg_din_syn(2):D data arrival time 2.839 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(2) (f) + 0.000 net: TLMU_p_2_ 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[2].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[2]_lvds_TLMU_U1/U0/NET1 1.470 tlmu_in[2].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.484 tlmu_in[2].lvds_TLMU_U1/U0/U1:Y (f) + 1.355 net: TLMU_i_2_ 2.839 i_cbb/cbbr_top_1/reg_din_syn(2):D (f) 2.839 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.792 net: CLK40out N/C i_cbb/cbbr_top_1/reg_din_syn(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 N/C i_cbb/cbbr_top_1/reg_din_syn(2):D Expanded Path 8 From: TLMU_n(2) To: i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D data arrival time 2.903 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(2) (f) + 0.000 net: TLMU_n_2_ 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[2]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[2].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[2]_lvds_TLMU_U1/U0/NET1 1.458 tlmu_in[2].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.472 tlmu_in[2].lvds_TLMU_U1/U0/U1:Y (f) + 1.093 net: TLMU_i_2_ 2.565 i_cbb/pt_align_inst/ix34629z1959:B (f) + 0.220 cell: ADLIB:AND2A 2.785 i_cbb/pt_align_inst/ix34629z1959:Y (f) + 0.118 net: i_cbb/pt_align_inst/nx34629z1 2.903 i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D (f) 2.903 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.789 net: CLK40out N/C i_cbb/pt_align_inst/reg_trg_aligned(4)(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1 N/C i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D Expanded Path 9 From: TLMU_n(0) To: i_cbb/cbbr_top_1/reg_din_syn(0):D data arrival time 2.922 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(0) (f) + 0.000 net: TLMU_n_0_ 0.000 tlmu_in[0].lvds_TLMU_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[0].lvds_TLMU_U1/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[0]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[0].lvds_TLMU_U1/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[0].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[0]_lvds_TLMU_U1/U0/NET1 1.458 tlmu_in[0].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.472 tlmu_in[0].lvds_TLMU_U1/U0/U1:Y (f) + 1.450 net: TLMU_i_0_ 2.922 i_cbb/cbbr_top_1/reg_din_syn(0):D (f) 2.922 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.804 net: CLK40out N/C i_cbb/cbbr_top_1/reg_din_syn(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 N/C i_cbb/cbbr_top_1/reg_din_syn(0):D Expanded Path 10 From: TLMU_p(2) To: i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D data arrival time 2.915 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(2) (f) + 0.000 net: TLMU_p_2_ 0.000 tlmu_in[2].lvds_TLMU_U1/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[2].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[2]_lvds_TLMU_U1/U0/NET1 1.470 tlmu_in[2].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.484 tlmu_in[2].lvds_TLMU_U1/U0/U1:Y (f) + 1.093 net: TLMU_i_2_ 2.577 i_cbb/pt_align_inst/ix34629z1959:B (f) + 0.220 cell: ADLIB:AND2A 2.797 i_cbb/pt_align_inst/ix34629z1959:Y (f) + 0.118 net: i_cbb/pt_align_inst/nx34629z1 2.915 i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D (f) 2.915 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.789 net: CLK40out N/C i_cbb/pt_align_inst/reg_trg_aligned(4)(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1 N/C i_cbb/pt_align_inst/reg_trg_aligned(4)(0):D END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: oddr_PIMLINK_0_ob/U0/U1:OCLK To: PIMLINK(0) Delay (ns): 1.229 Slack (ns): Arrival (ns): 5.765 Required (ns): Clock to Out (ns): 5.765 Path 2 From: i_cbb/ttcex_out_inst_reg_a_channel_out:CLK To: A_ECL Delay (ns): 2.869 Slack (ns): Arrival (ns): 7.401 Required (ns): Clock to Out (ns): 7.401 Path 3 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_p Delay (ns): 3.254 Slack (ns): Arrival (ns): 7.810 Required (ns): Clock to Out (ns): 7.810 Path 4 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_n Delay (ns): 3.266 Slack (ns): Arrival (ns): 7.822 Required (ns): Clock to Out (ns): 7.822 Path 5 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA Delay (ns): 3.331 Slack (ns): Arrival (ns): 7.868 Required (ns): Clock to Out (ns): 7.868 Path 6 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTp Delay (ns): 3.575 Slack (ns): Arrival (ns): 8.112 Required (ns): Clock to Out (ns): 8.112 Path 7 From: i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK To: SCSNOUTp Delay (ns): 3.575 Slack (ns): Arrival (ns): 8.112 Required (ns): Clock to Out (ns): 8.112 Path 8 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTn Delay (ns): 3.587 Slack (ns): Arrival (ns): 8.124 Required (ns): Clock to Out (ns): 8.124 Path 9 From: i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK To: SCSNOUTn Delay (ns): 3.587 Slack (ns): Arrival (ns): 8.124 Required (ns): Clock to Out (ns): 8.124 Path 10 From: i_adc/adc/adci/reg_spi_clk_i:CLK To: ADC_SCLK Delay (ns): 3.646 Slack (ns): Arrival (ns): 8.178 Required (ns): Clock to Out (ns): 8.178 Expanded Path 1 From: oddr_PIMLINK_0_ob/U0/U1:OCLK To: PIMLINK(0) data arrival time 5.765 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.615 net: CLK40out 4.536 oddr_PIMLINK_0_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 4.850 oddr_PIMLINK_0_ob/U0/U1:DOUT (r) + 0.000 net: oddr_PIMLINK_0_ob/U0/NET1 4.850 oddr_PIMLINK_0_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 5.765 oddr_PIMLINK_0_ob/U0/U0:PAD (r) + 0.000 net: PIMLINK_0_ 5.765 PIMLINK(0) (r) 5.765 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C PIMLINK(0) (r) Expanded Path 2 From: i_cbb/ttcex_out_inst_reg_a_channel_out:CLK To: A_ECL data arrival time 7.401 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.611 net: CLK40out 4.532 i_cbb/ttcex_out_inst_reg_a_channel_out:CLK (r) + 0.206 cell: ADLIB:DFN1 4.738 i_cbb/ttcex_out_inst_reg_a_channel_out:Q (r) + 1.535 net: A_ECL_i 6.273 obuf_A_ECL_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 6.486 obuf_A_ECL_U1/U0/U1:DOUT (r) + 0.000 net: obuf_A_ECL_U1/U0/NET1 6.486 obuf_A_ECL_U1/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 7.401 obuf_A_ECL_U1/U0/U0:PAD (r) + 0.000 net: A_ECL 7.401 A_ECL (r) 7.401 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C A_ECL (r) Expanded Path 3 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_p data arrival time 7.810 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.635 net: CLK40out 4.556 i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK (r) + 0.256 cell: ADLIB:DFN1E1 4.812 i_cbb/sys_config0/reg_cbb_ctrl_i(0):Q (f) + 2.176 net: CNRRL_i 6.988 lvds_SPB_iob/U0/U1:D (f) + 0.203 cell: ADLIB:IOTRI_OB_EB 7.191 lvds_SPB_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPB_iob/U0/NET1 7.191 lvds_SPB_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 7.810 lvds_SPB_iob/U0/U0:PAD (f) + 0.000 net: SPB_p 7.810 SPB_p (f) 7.810 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SPB_p (f) Expanded Path 4 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_n data arrival time 7.822 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.635 net: CLK40out 4.556 i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK (r) + 0.256 cell: ADLIB:DFN1E1 4.812 i_cbb/sys_config0/reg_cbb_ctrl_i(0):Q (f) + 2.176 net: CNRRL_i 6.988 lvds_SPB_iob/U0/U1:D (f) + 0.203 cell: ADLIB:IOTRI_OB_EB 7.191 lvds_SPB_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPB_iob/U0/NET1 7.191 lvds_SPB_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 7.822 lvds_SPB_iob/U0/U2:PAD (r) + 0.000 net: SPB_n 7.822 SPB_n (r) 7.822 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SPB_n (r) Expanded Path 5 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA data arrival time 7.868 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK (r) + 0.256 cell: ADLIB:DFN1C1 4.793 i_adc/sfp_rd_reg_SFP_SDA_e_i:Q (f) + 1.832 net: SIU_SDA_e 6.625 bbuf_SIU_SDA/U0/U1:E (f) + 0.168 cell: ADLIB:IOBI_IB_OB_EB 6.793 bbuf_SIU_SDA/U0/U1:EOUT (f) + 0.000 net: bbuf_SIU_SDA/U0/NET2 6.793 bbuf_SIU_SDA/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 7.868 bbuf_SIU_SDA/U0/U0:PAD (r) + 0.000 net: SIU_SDA 7.868 SIU_SDA (r) 7.868 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SIU_SDA (r) Expanded Path 6 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTp data arrival time 8.112 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.793 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d0_out 4.911 i_adc/SCSNOUT:A (f) + 0.215 cell: ADLIB:MX2 5.126 i_adc/SCSNOUT:Y (f) + 2.138 net: SCSNOUT2_i 7.264 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 7.493 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 7.493 lvds_SCSNOUT_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 8.112 lvds_SCSNOUT_iob/U0/U0:PAD (f) + 0.000 net: SCSNOUTp 8.112 SCSNOUTp (f) 8.112 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SCSNOUTp (f) Expanded Path 7 From: i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK To: SCSNOUTp data arrival time 8.112 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.793 i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d1_out 4.911 i_adc/SCSNOUT:B (f) + 0.215 cell: ADLIB:MX2 5.126 i_adc/SCSNOUT:Y (f) + 2.138 net: SCSNOUT2_i 7.264 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 7.493 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 7.493 lvds_SCSNOUT_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 8.112 lvds_SCSNOUT_iob/U0/U0:PAD (f) + 0.000 net: SCSNOUTp 8.112 SCSNOUTp (f) 8.112 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SCSNOUTp (f) Expanded Path 8 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTn data arrival time 8.124 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.793 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d0_out 4.911 i_adc/SCSNOUT:A (f) + 0.215 cell: ADLIB:MX2 5.126 i_adc/SCSNOUT:Y (f) + 2.138 net: SCSNOUT2_i 7.264 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 7.493 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 7.493 lvds_SCSNOUT_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 8.124 lvds_SCSNOUT_iob/U0/U2:PAD (r) + 0.000 net: SCSNOUTn 8.124 SCSNOUTn (r) 8.124 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SCSNOUTn (r) Expanded Path 9 From: i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK To: SCSNOUTn data arrival time 8.124 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.793 i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d1_out 4.911 i_adc/SCSNOUT:B (f) + 0.215 cell: ADLIB:MX2 5.126 i_adc/SCSNOUT:Y (f) + 2.138 net: SCSNOUT2_i 7.264 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 7.493 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 7.493 lvds_SCSNOUT_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 8.124 lvds_SCSNOUT_iob/U0/U2:PAD (r) + 0.000 net: SCSNOUTn 8.124 SCSNOUTn (r) 8.124 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C SCSNOUTn (r) Expanded Path 10 From: i_adc/adc/adci/reg_spi_clk_i:CLK To: ADC_SCLK data arrival time 8.178 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.611 net: CLK40out 4.532 i_adc/adc/adci/reg_spi_clk_i:CLK (r) + 0.206 cell: ADLIB:DFN1 4.738 i_adc/adc/adci/reg_spi_clk_i:Q (r) + 1.626 net: ADC_SCLK_i 6.364 obuf_ADC_SCLK_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 6.577 obuf_ADC_SCLK_U1/U0/U1:DOUT (r) + 0.000 net: obuf_ADC_SCLK_U1/U0/NET1 6.577 obuf_ADC_SCLK_U1/U0/U0:D (r) + 1.601 cell: ADLIB:IOPAD_TRI 8.178 obuf_ADC_SCLK_U1/U0/U0:PAD (r) + 0.000 net: ADC_SCLK 8.178 ADC_SCLK (r) 8.178 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C N/C ADC_SCLK (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_state_out(7):CLR Delay (ns): 0.636 Slack (ns): 0.600 Arrival (ns): 5.187 Required (ns): 4.587 Removal (ns): 0.000 Skew (ns): -0.036 Path 2 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(4):CLR Delay (ns): 0.624 Slack (ns): 0.601 Arrival (ns): 5.184 Required (ns): 4.583 Removal (ns): 0.000 Skew (ns): -0.023 Path 3 From: i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_state_out(0):CLR Delay (ns): 0.639 Slack (ns): 0.616 Arrival (ns): 5.195 Required (ns): 4.579 Removal (ns): 0.000 Skew (ns): -0.023 Path 4 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(2):CLR Delay (ns): 0.644 Slack (ns): 0.620 Arrival (ns): 5.199 Required (ns): 4.579 Removal (ns): 0.000 Skew (ns): -0.024 Path 5 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR Delay (ns): 0.640 Slack (ns): 0.621 Arrival (ns): 5.179 Required (ns): 4.558 Removal (ns): 0.000 Skew (ns): -0.019 Path 6 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(3):CLR Delay (ns): 0.640 Slack (ns): 0.621 Arrival (ns): 5.179 Required (ns): 4.558 Removal (ns): 0.000 Skew (ns): -0.019 Path 7 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLR Delay (ns): 0.644 Slack (ns): 0.622 Arrival (ns): 5.199 Required (ns): 4.577 Removal (ns): 0.000 Skew (ns): -0.022 Path 8 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR Delay (ns): 0.640 Slack (ns): 0.622 Arrival (ns): 5.177 Required (ns): 4.555 Removal (ns): 0.000 Skew (ns): -0.018 Path 9 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(1):CLR Delay (ns): 0.640 Slack (ns): 0.624 Arrival (ns): 5.177 Required (ns): 4.553 Removal (ns): 0.000 Skew (ns): -0.016 Path 10 From: i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_state_out(2):CLR Delay (ns): 0.624 Slack (ns): 0.626 Arrival (ns): 5.187 Required (ns): 4.561 Removal (ns): 0.000 Skew (ns): 0.002 Expanded Path 1 From: i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_state_out(7):CLR data arrival time 5.187 data required time - 4.587 slack 0.600 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.630 net: CLK40out 4.551 i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.757 i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_cbb/scsn_inst_nw_dll_bt1/h1_hm_rst_n 4.876 i_cbb/scsn_inst_nw_dll_bt1/ix65495z49934:B (r) + 0.187 cell: ADLIB:NAND2A 5.063 i_cbb/scsn_inst_nw_dll_bt1/ix65495z49934:Y (f) + 0.124 net: i_cbb/scsn_inst_nw_dll_bt1/h1_not_rst_n_i 5.187 i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_state_out(7):CLR (f) 5.187 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.666 net: CLK40out 4.587 i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_state_out(7):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.587 i_cbb/scsn_inst_nw_dll_bt1/h1_reg_hm_state_out(7):CLR 4.587 data required time Expanded Path 2 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(4):CLR data arrival time 5.184 data required time - 4.583 slack 0.601 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.639 net: CLK40out 4.560 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.766 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_hm_rst_n 4.885 i_cbb/scsn_inst_nw_nwl/sl0/ix63501z49933:B (r) + 0.187 cell: ADLIB:NAND2A 5.072 i_cbb/scsn_inst_nw_nwl/sl0/ix63501z49933:Y (f) + 0.112 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_not_rst_n_i 5.184 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(4):CLR (f) 5.184 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.662 net: CLK40out 4.583 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.583 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(4):CLR 4.583 data required time Expanded Path 3 From: i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_state_out(0):CLR data arrival time 5.195 data required time - 4.579 slack 0.616 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.635 net: CLK40out 4.556 i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.762 i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_rst_n:Q (r) + 0.128 net: i_adc/scsn_slv_nw_dll_bt0/h1_hm_rst_n 4.890 i_adc/scsn_slv_nw_dll_bt0/ix956z24337:A (r) + 0.183 cell: ADLIB:NAND3 5.073 i_adc/scsn_slv_nw_dll_bt0/ix956z24337:Y (f) + 0.122 net: i_adc/scsn_slv_nw_dll_bt0/h1_not_rst_n_i 5.195 i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_state_out(0):CLR (f) 5.195 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.658 net: CLK40out 4.579 i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.579 i_adc/scsn_slv_nw_dll_bt0/h1_reg_hm_state_out(0):CLR 4.579 data required time Expanded Path 4 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(2):CLR data arrival time 5.199 data required time - 4.579 slack 0.620 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.634 net: CLK40out 4.555 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.761 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_rst_n 4.880 i_cbb/scsn_inst_nw_nwl/sl1/ix63501z49933:B (r) + 0.187 cell: ADLIB:NAND2A 5.067 i_cbb/scsn_inst_nw_nwl/sl1/ix63501z49933:Y (f) + 0.132 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_not_rst_n_i 5.199 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(2):CLR (f) 5.199 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.658 net: CLK40out 4.579 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.579 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(2):CLR 4.579 data required time Expanded Path 5 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR data arrival time 5.179 data required time - 4.558 slack 0.621 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.618 net: CLK40out 4.539 i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.745 i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_nwl/h1_hm_rst_n 4.864 i_adc/scsn_slv_nw_nwl/ix956z24342:A (r) + 0.183 cell: ADLIB:NAND3 5.047 i_adc/scsn_slv_nw_nwl/ix956z24342:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/h1_not_rst_n_i 5.179 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR (f) 5.179 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.637 net: CLK40out 4.558 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.558 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR 4.558 data required time Expanded Path 6 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(3):CLR data arrival time 5.179 data required time - 4.558 slack 0.621 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.618 net: CLK40out 4.539 i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.745 i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_nwl/h1_hm_rst_n 4.864 i_adc/scsn_slv_nw_nwl/ix956z24342:A (r) + 0.183 cell: ADLIB:NAND3 5.047 i_adc/scsn_slv_nw_nwl/ix956z24342:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/h1_not_rst_n_i 5.179 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(3):CLR (f) 5.179 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.637 net: CLK40out 4.558 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.558 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(3):CLR 4.558 data required time Expanded Path 7 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLR data arrival time 5.199 data required time - 4.577 slack 0.622 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.634 net: CLK40out 4.555 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.761 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_rst_n 4.880 i_cbb/scsn_inst_nw_nwl/sl1/ix63501z49933:B (r) + 0.187 cell: ADLIB:NAND2A 5.067 i_cbb/scsn_inst_nw_nwl/sl1/ix63501z49933:Y (f) + 0.132 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_not_rst_n_i 5.199 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLR (f) 5.199 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.656 net: CLK40out 4.577 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.577 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLR 4.577 data required time Expanded Path 8 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR data arrival time 5.177 data required time - 4.555 slack 0.622 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.743 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_rst_n 4.862 i_adc/scsn_slv_nw_nwl/sl1/ix63501z24337:A (r) + 0.183 cell: ADLIB:NAND3 5.045 i_adc/scsn_slv_nw_nwl/sl1/ix63501z24337:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/sl1/h1_not_rst_n_i 5.177 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR (f) 5.177 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.634 net: CLK40out 4.555 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.555 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR 4.555 data required time Expanded Path 9 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(1):CLR data arrival time 5.177 data required time - 4.553 slack 0.624 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK40out 4.537 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.743 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_rst_n 4.862 i_adc/scsn_slv_nw_nwl/sl1/ix63501z24337:A (r) + 0.183 cell: ADLIB:NAND3 5.045 i_adc/scsn_slv_nw_nwl/sl1/ix63501z24337:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/sl1/h1_not_rst_n_i 5.177 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(1):CLR (f) 5.177 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.632 net: CLK40out 4.553 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.553 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(1):CLR 4.553 data required time Expanded Path 10 From: i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_state_out(2):CLR data arrival time 5.187 data required time - 4.561 slack 0.626 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.642 net: CLK40out 4.563 i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.769 i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_cbb/scsn_inst_nw_dll_bt0/h1_hm_rst_n 4.888 i_cbb/scsn_inst_nw_dll_bt0/ix956z49933:B (r) + 0.187 cell: ADLIB:NAND2A 5.075 i_cbb/scsn_inst_nw_dll_bt0/ix956z49933:Y (f) + 0.112 net: i_cbb/scsn_inst_nw_dll_bt0/h1_not_rst_n_i 5.187 i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_state_out(2):CLR (f) 5.187 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation 3.921 + 0.640 net: CLK40out 4.561 i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_state_out(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.561 i_cbb/scsn_inst_nw_dll_bt0/h1_reg_hm_state_out(2):CLR 4.561 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: i_adc/sfp_rd_reg_dout(3):CLR Delay (ns): 2.729 Slack (ns): Arrival (ns): 2.729 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.950 Path 2 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data_tx:CLR Delay (ns): 2.773 Slack (ns): Arrival (ns): 2.773 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.906 Path 3 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(0):CLR Delay (ns): 2.809 Slack (ns): Arrival (ns): 2.809 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.879 Path 4 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(6):CLR Delay (ns): 2.809 Slack (ns): Arrival (ns): 2.809 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.879 Path 5 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(2):CLR Delay (ns): 2.809 Slack (ns): Arrival (ns): 2.809 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.879 Path 6 From: RST_n To: i_adc/sfp_rd_reg_dout(4):CLR Delay (ns): 2.835 Slack (ns): Arrival (ns): 2.835 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.844 Path 7 From: RST_n To: i_adc/scsn_slv_nw_dll_ob0/modgen_counter_bitcounter_reg_q(1):CLR Delay (ns): 2.951 Slack (ns): Arrival (ns): 2.951 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.734 Path 8 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data:CLR Delay (ns): 2.960 Slack (ns): Arrival (ns): 2.960 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.725 Path 9 From: RST_n To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_crc(14):CLR Delay (ns): 2.979 Slack (ns): Arrival (ns): 2.979 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.706 Path 10 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(5):CLR Delay (ns): 3.070 Slack (ns): Arrival (ns): 3.070 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.616 Expanded Path 1 From: RST_n To: i_adc/sfp_rd_reg_dout(3):CLR data arrival time 2.729 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 0.439 net: not_rst_n 2.729 i_adc/sfp_rd_reg_dout(3):CLR (f) 2.729 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.758 net: CLK40out N/C i_adc/sfp_rd_reg_dout(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/sfp_rd_reg_dout(3):CLR Expanded Path 2 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data_tx:CLR data arrival time 2.773 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 0.483 net: not_rst_n 2.773 i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data_tx:CLR (f) 2.773 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.758 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data_tx:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data_tx:CLR Expanded Path 3 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(0):CLR data arrival time 2.809 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.892 net: RST_n_i 2.406 i_adc/scsn_slv_nw_dll_st0/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.655 i_adc/scsn_slv_nw_dll_st0/ix956z24337:Y (f) + 0.154 net: i_adc/scsn_slv_nw_dll_st0/h1_not_rst_n_i 2.809 i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(0):CLR (f) 2.809 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.767 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(0):CLR Expanded Path 4 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(6):CLR data arrival time 2.809 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.892 net: RST_n_i 2.406 i_adc/scsn_slv_nw_dll_st0/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.655 i_adc/scsn_slv_nw_dll_st0/ix956z24337:Y (f) + 0.154 net: i_adc/scsn_slv_nw_dll_st0/h1_not_rst_n_i 2.809 i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(6):CLR (f) 2.809 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.767 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(6):CLR Expanded Path 5 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(2):CLR data arrival time 2.809 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.892 net: RST_n_i 2.406 i_adc/scsn_slv_nw_dll_st0/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.655 i_adc/scsn_slv_nw_dll_st0/ix956z24337:Y (f) + 0.154 net: i_adc/scsn_slv_nw_dll_st0/h1_not_rst_n_i 2.809 i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(2):CLR (f) 2.809 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.767 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(2):CLR Expanded Path 6 From: RST_n To: i_adc/sfp_rd_reg_dout(4):CLR data arrival time 2.835 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 0.545 net: not_rst_n 2.835 i_adc/sfp_rd_reg_dout(4):CLR (f) 2.835 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.758 net: CLK40out N/C i_adc/sfp_rd_reg_dout(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/sfp_rd_reg_dout(4):CLR Expanded Path 7 From: RST_n To: i_adc/scsn_slv_nw_dll_ob0/modgen_counter_bitcounter_reg_q(1):CLR data arrival time 2.951 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 0.661 net: not_rst_n 2.951 i_adc/scsn_slv_nw_dll_ob0/modgen_counter_bitcounter_reg_q(1):CLR (f) 2.951 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.764 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob0/modgen_counter_bitcounter_reg_q(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob0/modgen_counter_bitcounter_reg_q(1):CLR Expanded Path 8 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data:CLR data arrival time 2.960 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 0.670 net: not_rst_n 2.960 i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data:CLR (f) 2.960 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.764 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st0/stuff_in_reg_data:CLR Expanded Path 9 From: RST_n To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_crc(14):CLR data arrival time 2.979 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.635 net: RST_n_i 2.149 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.290 i_adc/adc/ix4491z24338:Y (f) + 0.689 net: not_rst_n 2.979 i_adc/scsn_slv_nw_dll_ob0/reg_ob_crc(14):CLR (f) 2.979 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.764 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_crc(14):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_crc(14):CLR Expanded Path 10 From: RST_n To: i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(5):CLR data arrival time 3.070 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.892 net: RST_n_i 2.406 i_adc/scsn_slv_nw_dll_st0/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.655 i_adc/scsn_slv_nw_dll_st0/ix956z24337:Y (f) + 0.415 net: i_adc/scsn_slv_nw_dll_st0/h1_not_rst_n_i 3.070 i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(5):CLR (f) 3.070 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.921 Clock generation N/C + 0.765 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(5):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st0/h1_reg_hm_state_out(5):CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLB Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin oddr_BC_ECL_ob/U0/U1:OCLK SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DF Delay (ns): 7.138 Slack (ns): Arrival (ns): 7.138 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.674 Path 2 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DF Delay (ns): 7.150 Slack (ns): Arrival (ns): 7.150 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.662 Path 3 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DR Delay (ns): 7.174 Slack (ns): Arrival (ns): 7.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.638 Path 4 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DR Delay (ns): 7.186 Slack (ns): Arrival (ns): 7.186 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.626 Expanded Path 1 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DF data arrival time 7.138 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(1) (f) + 0.000 net: TLMU_n_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 1.458 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.472 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (f) + 2.842 net: TLMU_i_1_ 4.314 i_cbb/tin2_inst/ix2401z14896:A (f) + 0.215 cell: ADLIB:MX2 4.529 i_cbb/tin2_inst/ix2401z14896:Y (f) + 0.140 net: nx11205z1 4.669 i_cbb/tin2_inst/NOT_trg_i:A (f) + 0.206 cell: ADLIB:MX2C 4.875 i_cbb/tin2_inst/NOT_trg_i:Y (r) + 2.263 net: PIMLINK_i_2_ 7.138 oddr_PIMLINK_2_ob/U0/U1:DF (r) 7.138 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C + 0.766 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.000 Library hold time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DF Expanded Path 2 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DF data arrival time 7.150 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(1) (f) + 0.000 net: TLMU_p_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 1.470 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.484 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (f) + 2.842 net: TLMU_i_1_ 4.326 i_cbb/tin2_inst/ix2401z14896:A (f) + 0.215 cell: ADLIB:MX2 4.541 i_cbb/tin2_inst/ix2401z14896:Y (f) + 0.140 net: nx11205z1 4.681 i_cbb/tin2_inst/NOT_trg_i:A (f) + 0.206 cell: ADLIB:MX2C 4.887 i_cbb/tin2_inst/NOT_trg_i:Y (r) + 2.263 net: PIMLINK_i_2_ 7.150 oddr_PIMLINK_2_ob/U0/U1:DF (r) 7.150 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C + 0.766 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.000 Library hold time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DF Expanded Path 3 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DR data arrival time 7.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(1) (f) + 0.000 net: TLMU_n_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 1.458 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.472 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (f) + 2.842 net: TLMU_i_1_ 4.314 i_cbb/tin2_inst/ix2401z14896:A (f) + 0.215 cell: ADLIB:MX2 4.529 i_cbb/tin2_inst/ix2401z14896:Y (f) + 0.145 net: nx11205z1 4.674 ix11205z14896:A (f) + 0.202 cell: ADLIB:MX2 4.876 ix11205z14896:Y (f) + 2.298 net: not_PIMLINK_i_2 7.174 oddr_PIMLINK_2_ob/U0/U1:DR (f) 7.174 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C + 0.766 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.000 Library hold time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DR Expanded Path 4 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DR data arrival time 7.186 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(1) (f) + 0.000 net: TLMU_p_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (f) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 1.470 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 1.484 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (f) + 2.842 net: TLMU_i_1_ 4.326 i_cbb/tin2_inst/ix2401z14896:A (f) + 0.215 cell: ADLIB:MX2 4.541 i_cbb/tin2_inst/ix2401z14896:Y (f) + 0.145 net: nx11205z1 4.686 ix11205z14896:A (f) + 0.202 cell: ADLIB:MX2 4.888 ix11205z14896:Y (f) + 2.298 net: not_PIMLINK_i_2 7.186 oddr_PIMLINK_2_ob/U0/U1:DR (f) 7.186 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C + 0.766 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.000 Library hold time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DR END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) Delay (ns): 1.229 Slack (ns): Arrival (ns): 8.893 Required (ns): Clock to Out (ns): 8.893 Path 2 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) Delay (ns): 1.229 Slack (ns): Arrival (ns): 8.893 Required (ns): Clock to Out (ns): 8.893 Path 3 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL Delay (ns): 1.229 Slack (ns): Arrival (ns): 8.894 Required (ns): Clock to Out (ns): 8.894 Expanded Path 1 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) data arrival time 8.893 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation 7.046 + 0.618 net: CLK40out_90 7.664 oddr_PIMLINK_1_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 7.978 oddr_PIMLINK_1_ob/U0/U1:DOUT (r) + 0.000 net: oddr_PIMLINK_1_ob/U0/NET1 7.978 oddr_PIMLINK_1_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 8.893 oddr_PIMLINK_1_ob/U0/U0:PAD (r) + 0.000 net: PIMLINK_1_ 8.893 PIMLINK(1) (r) 8.893 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C N/C PIMLINK(1) (r) Expanded Path 2 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) data arrival time 8.893 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation 7.046 + 0.618 net: CLK40out_90 7.664 oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 7.978 oddr_PIMLINK_2_ob/U0/U1:DOUT (r) + 0.000 net: oddr_PIMLINK_2_ob/U0/NET1 7.978 oddr_PIMLINK_2_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 8.893 oddr_PIMLINK_2_ob/U0/U0:PAD (r) + 0.000 net: PIMLINK_2_ 8.893 PIMLINK(2) (r) 8.893 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C N/C PIMLINK(2) (r) Expanded Path 3 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL data arrival time 8.894 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation 7.046 + 0.619 net: CLK40out_90 7.665 oddr_BC_ECL_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 7.979 oddr_BC_ECL_ob/U0/U1:DOUT (r) + 0.000 net: oddr_BC_ECL_ob/U0/NET1 7.979 oddr_BC_ECL_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 8.894 oddr_BC_ECL_ob/U0/U0:PAD (r) + 0.000 net: BC_ECL 8.894 BC_ECL (r) 8.894 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 7.046 Clock generation N/C N/C BC_ECL (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLC SET Register to Register Path 1 From: i_cbb/cba_sample_reg_cb_par(3):CLK To: i_cbb/cba_sample_reg_cb_par(5):D Delay (ns): 0.357 Slack (ns): 0.338 Arrival (ns): 4.898 Required (ns): 4.560 Hold (ns): 0.000 Path 2 From: i_cbb/cba_sample_reg_cb_par(2):CLK To: i_cbb/cba_sample_reg_cb_par(4):D Delay (ns): 0.357 Slack (ns): 0.338 Arrival (ns): 4.898 Required (ns): 4.560 Hold (ns): 0.000 Path 3 From: i_cbb/cbc_sample_reg_cb_par(3):CLK To: i_cbb/cbc_sample_reg_cb_par(5):D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 4.895 Required (ns): 4.556 Hold (ns): 0.000 Path 4 From: i_cbb/cbc_sample_reg_cb_par(2):CLK To: i_cbb/cbc_sample_reg_cb_par(4):D Delay (ns): 0.362 Slack (ns): 0.345 Arrival (ns): 4.900 Required (ns): 4.555 Hold (ns): 0.000 Path 5 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D Delay (ns): 0.830 Slack (ns): 0.803 Arrival (ns): 5.363 Required (ns): 4.560 Hold (ns): 0.000 Path 6 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D Delay (ns): 1.549 Slack (ns): 1.527 Arrival (ns): 6.083 Required (ns): 4.556 Hold (ns): 0.000 Path 7 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D Delay (ns): 1.775 Slack (ns): 1.752 Arrival (ns): 6.312 Required (ns): 4.560 Hold (ns): 0.000 Path 8 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D Delay (ns): 1.947 Slack (ns): 1.965 Arrival (ns): 6.520 Required (ns): 4.555 Hold (ns): 0.000 Path 9 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D Delay (ns): 2.113 Slack (ns): 2.107 Arrival (ns): 6.663 Required (ns): 4.556 Hold (ns): 0.000 Path 10 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D Delay (ns): 2.521 Slack (ns): 2.525 Arrival (ns): 7.094 Required (ns): 4.569 Hold (ns): 0.000 Expanded Path 1 From: i_cbb/cba_sample_reg_cb_par(3):CLK To: i_cbb/cba_sample_reg_cb_par(5):D data arrival time 4.898 data required time - 4.560 slack 0.338 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.620 net: CLK80out 4.541 i_cbb/cba_sample_reg_cb_par(3):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.747 i_cbb/cba_sample_reg_cb_par(3):Q (r) + 0.151 net: i_cbb/cba_sample_cb_par_3_ 4.898 i_cbb/cba_sample_reg_cb_par(5):D (r) 4.898 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.639 net: CLK80out 4.560 i_cbb/cba_sample_reg_cb_par(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.560 i_cbb/cba_sample_reg_cb_par(5):D 4.560 data required time Expanded Path 2 From: i_cbb/cba_sample_reg_cb_par(2):CLK To: i_cbb/cba_sample_reg_cb_par(4):D data arrival time 4.898 data required time - 4.560 slack 0.338 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.620 net: CLK80out 4.541 i_cbb/cba_sample_reg_cb_par(2):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.747 i_cbb/cba_sample_reg_cb_par(2):Q (r) + 0.151 net: i_cbb/cba_sample_cb_par_2_ 4.898 i_cbb/cba_sample_reg_cb_par(4):D (r) 4.898 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.639 net: CLK80out 4.560 i_cbb/cba_sample_reg_cb_par(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.560 i_cbb/cba_sample_reg_cb_par(4):D 4.560 data required time Expanded Path 3 From: i_cbb/cbc_sample_reg_cb_par(3):CLK To: i_cbb/cbc_sample_reg_cb_par(5):D data arrival time 4.895 data required time - 4.556 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.617 net: CLK80out 4.538 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.744 i_cbb/cbc_sample_reg_cb_par(3):Q (r) + 0.151 net: i_cbb/cbc_sample_cb_par_3_ 4.895 i_cbb/cbc_sample_reg_cb_par(5):D (r) 4.895 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.635 net: CLK80out 4.556 i_cbb/cbc_sample_reg_cb_par(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.556 i_cbb/cbc_sample_reg_cb_par(5):D 4.556 data required time Expanded Path 4 From: i_cbb/cbc_sample_reg_cb_par(2):CLK To: i_cbb/cbc_sample_reg_cb_par(4):D data arrival time 4.900 data required time - 4.555 slack 0.345 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.617 net: CLK80out 4.538 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.744 i_cbb/cbc_sample_reg_cb_par(2):Q (r) + 0.156 net: i_cbb/cbc_sample_cb_par_2_ 4.900 i_cbb/cbc_sample_reg_cb_par(4):D (r) 4.900 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.634 net: CLK80out 4.555 i_cbb/cbc_sample_reg_cb_par(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.555 i_cbb/cbc_sample_reg_cb_par(4):D 4.555 data required time Expanded Path 5 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D data arrival time 5.363 data required time - 4.560 slack 0.803 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.612 net: CLK80out 4.533 i_cbb/cba_sample_reg_cb_par(0):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.739 i_cbb/cba_sample_reg_cb_par(0):Q (r) + 0.624 net: i_cbb/cba_sample_cb_par_0_ 5.363 i_cbb/cba_sample_reg_cb_par(2):D (r) 5.363 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.639 net: CLK80out 4.560 i_cbb/cba_sample_reg_cb_par(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.560 i_cbb/cba_sample_reg_cb_par(2):D 4.560 data required time Expanded Path 6 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D data arrival time 6.083 data required time - 4.556 slack 1.527 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.613 net: CLK80out 4.534 i_cbb/cbc_sample_reg_cb_par(0):CLK (r) + 0.256 cell: ADLIB:DFN1C1 4.790 i_cbb/cbc_sample_reg_cb_par(0):Q (f) + 1.293 net: i_cbb/cbc_sample_cb_par_0_ 6.083 i_cbb/cbc_sample_reg_cb_par(2):D (f) 6.083 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.635 net: CLK80out 4.556 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.556 i_cbb/cbc_sample_reg_cb_par(2):D 4.556 data required time Expanded Path 7 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D data arrival time 6.312 data required time - 4.560 slack 1.752 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.616 net: CLK80out 4.537 i_cbb/cba_sample_reg_cb_par(1):CLK (r) + 0.256 cell: ADLIB:DFN1C1 4.793 i_cbb/cba_sample_reg_cb_par(1):Q (f) + 1.519 net: i_cbb/cba_sample_cb_par_1_ 6.312 i_cbb/cba_sample_reg_cb_par(3):D (f) 6.312 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.639 net: CLK80out 4.560 i_cbb/cba_sample_reg_cb_par(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.560 i_cbb/cba_sample_reg_cb_par(3):D 4.560 data required time Expanded Path 8 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D data arrival time 6.520 data required time - 4.555 slack 1.965 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.652 net: CLK80out 4.573 iddr_CB_A_ib/U0/U1:ICLK (r) + 0.127 cell: ADLIB:IOIN_ID 4.700 iddr_CB_A_ib/U0/U1:YF (f) + 1.820 net: CB_A_i_1_ 6.520 i_cbb/cba_sample_reg_cb_par(1):D (f) 6.520 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.634 net: CLK80out 4.555 i_cbb/cba_sample_reg_cb_par(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.555 i_cbb/cba_sample_reg_cb_par(1):D 4.555 data required time Expanded Path 9 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D data arrival time 6.663 data required time - 4.556 slack 2.107 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.629 net: CLK80out 4.550 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) + 0.256 cell: ADLIB:DFN1C1 4.806 i_cbb/cbc_sample_reg_cb_par(1):Q (f) + 1.857 net: i_cbb/cbc_sample_cb_par_1_ 6.663 i_cbb/cbc_sample_reg_cb_par(3):D (f) 6.663 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.635 net: CLK80out 4.556 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.556 i_cbb/cbc_sample_reg_cb_par(3):D 4.556 data required time Expanded Path 10 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D data arrival time 7.094 data required time - 4.569 slack 2.525 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.652 net: CLK80out 4.573 iddr_CB_C_ib/U0/U1:ICLK (r) + 0.127 cell: ADLIB:IOIN_ID 4.700 iddr_CB_C_ib/U0/U1:YF (f) + 2.394 net: CB_C_i_1_ 7.094 i_cbb/cbc_sample_reg_cb_par(1):D (f) 7.094 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.648 net: CLK80out 4.569 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.569 i_cbb/cbc_sample_reg_cb_par(1):D 4.569 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN Delay (ns): 0.286 Slack (ns): Arrival (ns): 0.286 Required (ns): Hold (ns): 0.000 External Hold (ns): 4.443 Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN Delay (ns): 0.286 Slack (ns): Arrival (ns): 0.286 Required (ns): Hold (ns): 0.000 External Hold (ns): 4.443 Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN Delay (ns): 0.286 Slack (ns): Arrival (ns): 0.286 Required (ns): Hold (ns): 0.000 External Hold (ns): 4.443 Expanded Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN data arrival time 0.286 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_C (f) + 0.000 net: CB_C 0.000 iddr_CB_C_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 iddr_CB_C_ib/U0/U0:Y (f) + 0.000 net: iddr_CB_C_ib/U0/NET1 0.286 iddr_CB_C_ib/U0/U1:YIN (f) 0.286 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation N/C + 0.808 net: CLK80out N/C iddr_CB_C_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C iddr_CB_C_ib/U0/U1:YIN Expanded Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN data arrival time 0.286 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 BUSY (f) + 0.000 net: BUSY 0.000 iddr_busy_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 iddr_busy_ib/U0/U0:Y (f) + 0.000 net: iddr_busy_ib/U0/NET1 0.286 iddr_busy_ib/U0/U1:YIN (f) 0.286 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation N/C + 0.808 net: CLK80out N/C iddr_busy_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C iddr_busy_ib/U0/U1:YIN Expanded Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN data arrival time 0.286 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_A (f) + 0.000 net: CB_A 0.000 iddr_CB_A_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 iddr_CB_A_ib/U0/U0:Y (f) + 0.000 net: iddr_CB_A_ib/U0/NET1 0.286 iddr_CB_A_ib/U0/U1:YIN (f) 0.286 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation N/C + 0.808 net: CLK80out N/C iddr_CB_A_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C iddr_CB_A_ib/U0/U1:YIN END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p Delay (ns): 6.293 Slack (ns): Arrival (ns): 10.866 Required (ns): Clock to Out (ns): 10.866 Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n Delay (ns): 6.305 Slack (ns): Arrival (ns): 10.878 Required (ns): Clock to Out (ns): 10.878 Expanded Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p data arrival time 10.866 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.652 net: CLK80out 4.573 iddr_busy_ib/U0/U1:ICLK (r) + 0.181 cell: ADLIB:IOIN_ID 4.754 iddr_busy_ib/U0/U1:YR (f) + 2.337 net: BUSY_i_0_ 7.091 i_cbb/ix7212z10880:A (f) + 0.182 cell: ADLIB:XOR2 7.273 i_cbb/ix7212z10880:Y (f) + 1.843 net: i_cbb/nx7212z5 9.116 i_cbb/SPA:C (f) + 0.260 cell: ADLIB:XOR3 9.376 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 10.018 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 10.247 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 10.247 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 10.866 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 10.866 SPA_p (f) 10.866 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation N/C N/C SPA_p (f) Expanded Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n data arrival time 10.878 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation 3.921 + 0.652 net: CLK80out 4.573 iddr_busy_ib/U0/U1:ICLK (r) + 0.181 cell: ADLIB:IOIN_ID 4.754 iddr_busy_ib/U0/U1:YR (f) + 2.337 net: BUSY_i_0_ 7.091 i_cbb/ix7212z10880:A (f) + 0.182 cell: ADLIB:XOR2 7.273 i_cbb/ix7212z10880:Y (f) + 1.843 net: i_cbb/nx7212z5 9.116 i_cbb/SPA:C (f) + 0.260 cell: ADLIB:XOR3 9.376 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 10.018 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 10.247 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 10.247 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 10.878 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 10.878 SPA_n (r) 10.878 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.921 Clock generation N/C N/C SPA_n (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain CLK40p Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin lvds_clk40in_U1/U0/U0:PAD SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Hold No Path END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p Delay (ns): 2.711 Slack (ns): Arrival (ns): 5.304 Required (ns): Clock to Out (ns): 5.304 Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n Delay (ns): 2.723 Slack (ns): Arrival (ns): 5.316 Required (ns): Clock to Out (ns): 5.316 Expanded Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p data arrival time 5.304 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (f) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 lvds_clk40in_U1/U0/U0:Y (f) + 0.000 net: lvds_clk40in_U1/U0/NET1 0.601 lvds_clk40in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 lvds_clk40in_U1/U0/U1:Y (f) + 1.978 net: CLK40_i 2.593 i_cbb/clock_generation_ipll_Core:CLKA (f) + 1.221 cell: ADLIB:PLL 3.814 i_cbb/clock_generation_ipll_Core:GLA (f) + 0.642 net: CLK40out 4.456 lvds_clk40out_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 4.685 lvds_clk40out_iob/U0/U1:DOUT (f) + 0.000 net: lvds_clk40out_iob/U0/NET1 4.685 lvds_clk40out_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 5.304 lvds_clk40out_iob/U0/U0:PAD (f) + 0.000 net: CLK40T_p 5.304 CLK40T_p (f) 5.304 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_p (f) Expanded Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n data arrival time 5.316 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (f) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 lvds_clk40in_U1/U0/U0:Y (f) + 0.000 net: lvds_clk40in_U1/U0/NET1 0.601 lvds_clk40in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 lvds_clk40in_U1/U0/U1:Y (f) + 1.978 net: CLK40_i 2.593 i_cbb/clock_generation_ipll_Core:CLKA (f) + 1.221 cell: ADLIB:PLL 3.814 i_cbb/clock_generation_ipll_Core:GLA (f) + 0.642 net: CLK40out 4.456 lvds_clk40out_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 4.685 lvds_clk40out_iob/U0/U1:DOUT (f) + 0.000 net: lvds_clk40out_iob/U0/NET1 4.685 lvds_clk40out_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 5.316 lvds_clk40out_iob/U0/U2:PAD (r) + 0.000 net: CLK40T_n 5.316 CLK40T_n (r) 5.316 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_n (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Path set Pin to Pin SET Input to Output Path 1 From: S2_IN_n(0) To: SPA_p Delay (ns): 4.464 Slack (ns): Arrival (ns): 4.464 Required (ns): Path 2 From: S2_IN_p(0) To: SPA_p Delay (ns): 4.473 Slack (ns): Arrival (ns): 4.473 Required (ns): Path 3 From: S2_IN_n(0) To: SPA_n Delay (ns): 4.476 Slack (ns): Arrival (ns): 4.476 Required (ns): Path 4 From: S2_IN_p(0) To: SPA_n Delay (ns): 4.485 Slack (ns): Arrival (ns): 4.485 Required (ns): Path 5 From: IO_C(1) To: SPA_p Delay (ns): 4.507 Slack (ns): Arrival (ns): 4.507 Required (ns): Path 6 From: IO_C(1) To: SPA_n Delay (ns): 4.519 Slack (ns): Arrival (ns): 4.519 Required (ns): Path 7 From: S1_IN_n(0) To: SPA_p Delay (ns): 4.543 Slack (ns): Arrival (ns): 4.543 Required (ns): Path 8 From: S1_IN_n(0) To: SPA_n Delay (ns): 4.555 Slack (ns): Arrival (ns): 4.555 Required (ns): Path 9 From: S1_IN_p(0) To: SPA_p Delay (ns): 4.555 Slack (ns): Arrival (ns): 4.555 Required (ns): Path 10 From: S1_IN_p(0) To: SPA_n Delay (ns): 4.567 Slack (ns): Arrival (ns): 4.567 Required (ns): Expanded Path 1 From: S2_IN_n(0) To: SPA_p data arrival time 4.464 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_n(0) (f) + 0.000 net: S2_IN_n_0_ 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/U2_N2P 0.000 adds1s2[0].lvds_S2in_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 adds1s2[0].lvds_S2in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/NET1 0.589 adds1s2[0].lvds_S2in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 adds1s2[0].lvds_S2in_U1/U0/U1:Y (f) + 0.418 net: S2_IN_i_0_ 1.021 i_cbb/ix7212z10879:A (f) + 0.182 cell: ADLIB:XOR2 1.203 i_cbb/ix7212z10879:Y (f) + 0.919 net: i_cbb/nx7212z4 2.122 i_cbb/modgen_xor_1423_ix7212z10879:A (f) + 0.141 cell: ADLIB:XOR3 2.263 i_cbb/modgen_xor_1423_ix7212z10879:Y (f) + 0.494 net: i_cbb/nx7212z3 2.757 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.974 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.616 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.845 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.845 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.464 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.464 SPA_p (f) 4.464 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_n(0) (f) N/C SPA_p (f) N/C data required time Expanded Path 2 From: S2_IN_p(0) To: SPA_p data arrival time 4.473 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_p(0) (r) + 0.000 net: S2_IN_p_0_ 0.000 adds1s2[0].lvds_S2in_U1/U0/U0:PAD (r) + 0.594 cell: ADLIB:IOPADP_IN 0.594 adds1s2[0].lvds_S2in_U1/U0/U0:Y (r) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/NET1 0.594 adds1s2[0].lvds_S2in_U1/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.609 adds1s2[0].lvds_S2in_U1/U0/U1:Y (r) + 0.445 net: S2_IN_i_0_ 1.054 i_cbb/ix7212z10879:A (r) + 0.158 cell: ADLIB:XOR2 1.212 i_cbb/ix7212z10879:Y (f) + 0.919 net: i_cbb/nx7212z4 2.131 i_cbb/modgen_xor_1423_ix7212z10879:A (f) + 0.141 cell: ADLIB:XOR3 2.272 i_cbb/modgen_xor_1423_ix7212z10879:Y (f) + 0.494 net: i_cbb/nx7212z3 2.766 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.983 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.625 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.854 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.854 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.473 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.473 SPA_p (f) 4.473 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_p(0) (r) N/C SPA_p (f) N/C data required time Expanded Path 3 From: S2_IN_n(0) To: SPA_n data arrival time 4.476 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_n(0) (f) + 0.000 net: S2_IN_n_0_ 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/U2_N2P 0.000 adds1s2[0].lvds_S2in_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 adds1s2[0].lvds_S2in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/NET1 0.589 adds1s2[0].lvds_S2in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 adds1s2[0].lvds_S2in_U1/U0/U1:Y (f) + 0.418 net: S2_IN_i_0_ 1.021 i_cbb/ix7212z10879:A (f) + 0.182 cell: ADLIB:XOR2 1.203 i_cbb/ix7212z10879:Y (f) + 0.919 net: i_cbb/nx7212z4 2.122 i_cbb/modgen_xor_1423_ix7212z10879:A (f) + 0.141 cell: ADLIB:XOR3 2.263 i_cbb/modgen_xor_1423_ix7212z10879:Y (f) + 0.494 net: i_cbb/nx7212z3 2.757 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.974 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.616 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.845 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.845 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.476 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.476 SPA_n (r) 4.476 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_n(0) (f) N/C SPA_n (r) N/C data required time Expanded Path 4 From: S2_IN_p(0) To: SPA_n data arrival time 4.485 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_p(0) (r) + 0.000 net: S2_IN_p_0_ 0.000 adds1s2[0].lvds_S2in_U1/U0/U0:PAD (r) + 0.594 cell: ADLIB:IOPADP_IN 0.594 adds1s2[0].lvds_S2in_U1/U0/U0:Y (r) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/NET1 0.594 adds1s2[0].lvds_S2in_U1/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.609 adds1s2[0].lvds_S2in_U1/U0/U1:Y (r) + 0.445 net: S2_IN_i_0_ 1.054 i_cbb/ix7212z10879:A (r) + 0.158 cell: ADLIB:XOR2 1.212 i_cbb/ix7212z10879:Y (f) + 0.919 net: i_cbb/nx7212z4 2.131 i_cbb/modgen_xor_1423_ix7212z10879:A (f) + 0.141 cell: ADLIB:XOR3 2.272 i_cbb/modgen_xor_1423_ix7212z10879:Y (f) + 0.494 net: i_cbb/nx7212z3 2.766 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.983 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.625 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.854 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.854 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.485 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.485 SPA_n (r) 4.485 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_p(0) (r) N/C SPA_n (r) N/C data required time Expanded Path 5 From: IO_C(1) To: SPA_p data arrival time 4.507 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(1) (f) + 0.000 net: IO_C_1_ 0.000 ibuf_IO_C1_ib/U0/U0:PAD (f) + 0.304 cell: ADLIB:IOPAD_IN 0.304 ibuf_IO_C1_ib/U0/U0:Y (f) + 0.000 net: ibuf_IO_C1_ib/U0/NET1 0.304 ibuf_IO_C1_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.318 ibuf_IO_C1_ib/U0/U1:Y (f) + 1.686 net: IO_C_i_1_ 2.004 i_cbb/ix7212z10877:B (f) + 0.227 cell: ADLIB:XOR2 2.231 i_cbb/ix7212z10877:Y (r) + 0.119 net: i_cbb/nx7212z2 2.350 i_cbb/modgen_xor_1423_ix7212z10877:A (r) + 0.138 cell: ADLIB:XOR3 2.488 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.388 net: i_cbb/nx7212z1 2.876 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 3.017 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.659 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.888 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.888 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.507 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.507 SPA_p (f) 4.507 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(1) (f) N/C SPA_p (f) N/C data required time Expanded Path 6 From: IO_C(1) To: SPA_n data arrival time 4.519 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(1) (f) + 0.000 net: IO_C_1_ 0.000 ibuf_IO_C1_ib/U0/U0:PAD (f) + 0.304 cell: ADLIB:IOPAD_IN 0.304 ibuf_IO_C1_ib/U0/U0:Y (f) + 0.000 net: ibuf_IO_C1_ib/U0/NET1 0.304 ibuf_IO_C1_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.318 ibuf_IO_C1_ib/U0/U1:Y (f) + 1.686 net: IO_C_i_1_ 2.004 i_cbb/ix7212z10877:B (f) + 0.227 cell: ADLIB:XOR2 2.231 i_cbb/ix7212z10877:Y (r) + 0.119 net: i_cbb/nx7212z2 2.350 i_cbb/modgen_xor_1423_ix7212z10877:A (r) + 0.138 cell: ADLIB:XOR3 2.488 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.388 net: i_cbb/nx7212z1 2.876 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 3.017 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.659 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.888 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.888 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.519 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.519 SPA_n (r) 4.519 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(1) (f) N/C SPA_n (r) N/C data required time Expanded Path 7 From: S1_IN_n(0) To: SPA_p data arrival time 4.543 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_n(0) (f) + 0.000 net: S1_IN_n_0_ 0.000 adds1s2[0].lvds_S1in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[0].lvds_S1in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[0]_lvds_S1in_U1/U0/U2_N2P 0.000 adds1s2[0].lvds_S1in_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 adds1s2[0].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[0]_lvds_S1in_U1/U0/NET1 0.589 adds1s2[0].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 adds1s2[0].lvds_S1in_U1/U0/U1:Y (f) + 1.621 net: S1_IN_i_0_ 2.224 i_cbb/modgen_xor_1423_ix7212z10877:C (f) + 0.300 cell: ADLIB:XOR3 2.524 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.388 net: i_cbb/nx7212z1 2.912 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 3.053 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.695 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.924 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.924 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.543 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.543 SPA_p (f) 4.543 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_n(0) (f) N/C SPA_p (f) N/C data required time Expanded Path 8 From: S1_IN_n(0) To: SPA_n data arrival time 4.555 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_n(0) (f) + 0.000 net: S1_IN_n_0_ 0.000 adds1s2[0].lvds_S1in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[0].lvds_S1in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[0]_lvds_S1in_U1/U0/U2_N2P 0.000 adds1s2[0].lvds_S1in_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 adds1s2[0].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[0]_lvds_S1in_U1/U0/NET1 0.589 adds1s2[0].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 adds1s2[0].lvds_S1in_U1/U0/U1:Y (f) + 1.621 net: S1_IN_i_0_ 2.224 i_cbb/modgen_xor_1423_ix7212z10877:C (f) + 0.300 cell: ADLIB:XOR3 2.524 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.388 net: i_cbb/nx7212z1 2.912 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 3.053 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.695 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.924 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.924 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.555 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.555 SPA_n (r) 4.555 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_n(0) (f) N/C SPA_n (r) N/C data required time Expanded Path 9 From: S1_IN_p(0) To: SPA_p data arrival time 4.555 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_p(0) (f) + 0.000 net: S1_IN_p_0_ 0.000 adds1s2[0].lvds_S1in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 adds1s2[0].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[0]_lvds_S1in_U1/U0/NET1 0.601 adds1s2[0].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 adds1s2[0].lvds_S1in_U1/U0/U1:Y (f) + 1.621 net: S1_IN_i_0_ 2.236 i_cbb/modgen_xor_1423_ix7212z10877:C (f) + 0.300 cell: ADLIB:XOR3 2.536 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.388 net: i_cbb/nx7212z1 2.924 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 3.065 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.707 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.936 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.936 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.555 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.555 SPA_p (f) 4.555 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_p(0) (f) N/C SPA_p (f) N/C data required time Expanded Path 10 From: S1_IN_p(0) To: SPA_n data arrival time 4.567 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_p(0) (f) + 0.000 net: S1_IN_p_0_ 0.000 adds1s2[0].lvds_S1in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 adds1s2[0].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[0]_lvds_S1in_U1/U0/NET1 0.601 adds1s2[0].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 adds1s2[0].lvds_S1in_U1/U0/U1:Y (f) + 1.621 net: S1_IN_i_0_ 2.236 i_cbb/modgen_xor_1423_ix7212z10877:C (f) + 0.300 cell: ADLIB:XOR3 2.536 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.388 net: i_cbb/nx7212z1 2.924 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 3.065 i_cbb/SPA:Y (f) + 0.642 net: SPA_i 3.707 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.936 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.936 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.567 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.567 SPA_n (r) 4.567 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_p(0) (f) N/C SPA_n (r) N/C data required time END SET Input to Output ---------------------------------------------------- Path set User Sets