Timing Report Min Delay Analysis SmartTime Version v9.1 SP3 Actel Corporation - Actel Designer Software Release v9.1 SP3 (Version 9.1.3.4) Copyright (c) 1989-2010 Date: Tue Sep 6 16:48:51 2011 Design: actel_par_A3PE1500 Family: ProASIC3E Die: A3PE1500 Package: 208 PQFP Temperature: COM Voltage: COM Speed Grade: -2 Design State: Post-Layout Data source: Silicon verified Min Operating Condition: BEST Max Operating Condition: WORST Using Enhanced Min Delay Analysis Scenario for Timing Analysis: Primary ----------------------------------------------------- SUMMARY Clock Domain: SIU_RXCLK Period (ns): 6.763 Frequency (MHz): 147.863 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 1.647 External Hold (ns): 0.326 Min Clock-To-Out (ns): N/A Max Clock-To-Out (ns): N/A Clock Domain: SIU_TXCLK Period (ns): 6.719 Frequency (MHz): 148.832 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 6.418 External Hold (ns): 1.525 Min Clock-To-Out (ns): 3.130 Max Clock-To-Out (ns): 14.389 Clock Domain: i_SIU/reg_tx_clk_2:Q Period (ns): 8.543 Frequency (MHz): 117.055 Required Period (ns): 18.182 Required Frequency (MHz): 54.999 External Setup (ns): 2.145 External Hold (ns): 0.738 Min Clock-To-Out (ns): 5.042 Max Clock-To-Out (ns): 13.371 Clock Domain: i_adc/cdiv_reg_q:Q Period (ns): 13.986 Frequency (MHz): 71.500 Required Period (ns): 100.000 Required Frequency (MHz): 10.000 External Setup (ns): 1.881 External Hold (ns): -0.136 Min Clock-To-Out (ns): 3.833 Max Clock-To-Out (ns): 10.207 Clock Domain: i_cbb/clock_generation_ipll_Core:GLA Period (ns): 19.159 Frequency (MHz): 52.195 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): 4.729 External Hold (ns): 2.756 Min Clock-To-Out (ns): 5.218 Max Clock-To-Out (ns): 19.544 Clock Domain: i_cbb/clock_generation_ipll_Core:GLB Period (ns): 0.796 Frequency (MHz): 1256.281 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 8.344 Max Clock-To-Out (ns): 14.272 Clock Domain: i_cbb/clock_generation_ipll_Core:GLC Period (ns): 4.450 Frequency (MHz): 224.719 Required Period (ns): 12.500 Required Frequency (MHz): 80.000 External Setup (ns): -6.546 External Hold (ns): 3.852 Min Clock-To-Out (ns): 9.450 Max Clock-To-Out (ns): 19.731 Clock Domain: CLK40p Period (ns): 2.860 Frequency (MHz): 349.650 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 4.824 Max Clock-To-Out (ns): 9.703 Input to Output Min Delay (ns): 4.530 Max Delay (ns): 13.313 END SUMMARY ----------------------------------------------------- Clock Domain SIU_RXCLK SET Register to Register Path 1 From: i_SIU/RXDATA_INST/reg_rxdf_d(2):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD2 Delay (ns): 0.425 Slack (ns): 0.262 Arrival (ns): 2.452 Required (ns): 2.190 Hold (ns): 0.000 Path 2 From: i_SIU/RXDATA_INST/reg_rxdf_d(0):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD0 Delay (ns): 0.425 Slack (ns): 0.262 Arrival (ns): 2.452 Required (ns): 2.190 Hold (ns): 0.000 Path 3 From: i_SIU/RXDATA_INST/reg_rxdf_d(9):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD9 Delay (ns): 0.432 Slack (ns): 0.269 Arrival (ns): 2.459 Required (ns): 2.190 Hold (ns): 0.000 Path 4 From: i_SIU/reg_srst_pipe(0):CLK To: i_SIU/reg_srst_pipe(1):D Delay (ns): 0.357 Slack (ns): 0.273 Arrival (ns): 2.316 Required (ns): 2.043 Hold (ns): 0.000 Path 5 From: i_SIU/reg_srst_pipe(2):CLK To: i_SIU/reg_srst_pipe(3):D Delay (ns): 0.357 Slack (ns): 0.285 Arrival (ns): 2.316 Required (ns): 2.031 Hold (ns): 0.000 Path 6 From: i_SIU/reg_srst_pipe(1):CLK To: i_SIU/reg_srst_pipe(2):D Delay (ns): 0.357 Slack (ns): 0.295 Arrival (ns): 2.326 Required (ns): 2.031 Hold (ns): 0.000 Path 7 From: i_SIU/RXCMD_INST/reg_scmd_present(0):CLK To: i_SIU/RXCMD_INST/reg_scmd_req:D Delay (ns): 0.440 Slack (ns): 0.361 Arrival (ns): 2.429 Required (ns): 2.068 Hold (ns): 0.000 Path 8 From: i_SIU/RXDATA_INST/reg_rxdf_d(11):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD11 Delay (ns): 0.690 Slack (ns): 0.478 Arrival (ns): 2.668 Required (ns): 2.190 Hold (ns): 0.000 Path 9 From: i_SIU/RXDATA_INST/reg_rxd_present(1):CLK To: i_SIU/RXDATA_INST/reg_b_osinfr:D Delay (ns): 0.566 Slack (ns): 0.487 Arrival (ns): 2.555 Required (ns): 2.068 Hold (ns): 0.000 Path 10 From: i_SIU/reg_q(14):CLK To: i_SIU/reg_q(14):D Delay (ns): 0.572 Slack (ns): 0.493 Arrival (ns): 2.561 Required (ns): 2.068 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/RXDATA_INST/reg_rxdf_d(2):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD2 data arrival time 2.452 data required time - 2.190 slack 0.262 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.367 net: SIU_RXCLK_cb 2.027 i_SIU/RXDATA_INST/reg_rxdf_d(2):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.233 i_SIU/RXDATA_INST/reg_rxdf_d(2):Q (r) + 0.219 net: i_SIU/s_rxdf_d_2_ 2.452 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD2 (r) 2.452 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.530 net: SIU_RXCLK_cb 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD2 2.190 data required time Expanded Path 2 From: i_SIU/RXDATA_INST/reg_rxdf_d(0):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD0 data arrival time 2.452 data required time - 2.190 slack 0.262 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.367 net: SIU_RXCLK_cb 2.027 i_SIU/RXDATA_INST/reg_rxdf_d(0):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.233 i_SIU/RXDATA_INST/reg_rxdf_d(0):Q (r) + 0.219 net: i_SIU/s_rxdf_d_0_ 2.452 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD0 (r) 2.452 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.530 net: SIU_RXCLK_cb 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD0 2.190 data required time Expanded Path 3 From: i_SIU/RXDATA_INST/reg_rxdf_d(9):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD9 data arrival time 2.459 data required time - 2.190 slack 0.269 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.367 net: SIU_RXCLK_cb 2.027 i_SIU/RXDATA_INST/reg_rxdf_d(9):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.233 i_SIU/RXDATA_INST/reg_rxdf_d(9):Q (r) + 0.226 net: i_SIU/s_rxdf_d_9_ 2.459 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD9 (r) 2.459 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.530 net: SIU_RXCLK_cb 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD9 2.190 data required time Expanded Path 4 From: i_SIU/reg_srst_pipe(0):CLK To: i_SIU/reg_srst_pipe(1):D data arrival time 2.316 data required time - 2.043 slack 0.273 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.299 net: SIU_RXCLK_cb 1.959 i_SIU/reg_srst_pipe(0):CLK (r) + 0.206 cell: ADLIB:DFN1P1 2.165 i_SIU/reg_srst_pipe(0):Q (r) + 0.151 net: i_SIU/srst_pipe_0_ 2.316 i_SIU/reg_srst_pipe(1):D (r) 2.316 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.383 net: SIU_RXCLK_cb 2.043 i_SIU/reg_srst_pipe(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 2.043 i_SIU/reg_srst_pipe(1):D 2.043 data required time Expanded Path 5 From: i_SIU/reg_srst_pipe(2):CLK To: i_SIU/reg_srst_pipe(3):D data arrival time 2.316 data required time - 2.031 slack 0.285 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.299 net: SIU_RXCLK_cb 1.959 i_SIU/reg_srst_pipe(2):CLK (r) + 0.206 cell: ADLIB:DFN1P1 2.165 i_SIU/reg_srst_pipe(2):Q (r) + 0.151 net: i_SIU/srst_pipe_2_ 2.316 i_SIU/reg_srst_pipe(3):D (r) 2.316 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.371 net: SIU_RXCLK_cb 2.031 i_SIU/reg_srst_pipe(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 2.031 i_SIU/reg_srst_pipe(3):D 2.031 data required time Expanded Path 6 From: i_SIU/reg_srst_pipe(1):CLK To: i_SIU/reg_srst_pipe(2):D data arrival time 2.326 data required time - 2.031 slack 0.295 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.309 net: SIU_RXCLK_cb 1.969 i_SIU/reg_srst_pipe(1):CLK (r) + 0.206 cell: ADLIB:DFN1P1 2.175 i_SIU/reg_srst_pipe(1):Q (r) + 0.151 net: i_SIU/srst_pipe_1_ 2.326 i_SIU/reg_srst_pipe(2):D (r) 2.326 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.371 net: SIU_RXCLK_cb 2.031 i_SIU/reg_srst_pipe(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 2.031 i_SIU/reg_srst_pipe(2):D 2.031 data required time Expanded Path 7 From: i_SIU/RXCMD_INST/reg_scmd_present(0):CLK To: i_SIU/RXCMD_INST/reg_scmd_req:D data arrival time 2.429 data required time - 2.068 slack 0.361 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.329 net: SIU_RXCLK_cb 1.989 i_SIU/RXCMD_INST/reg_scmd_present(0):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.195 i_SIU/RXCMD_INST/reg_scmd_present(0):Q (r) + 0.234 net: i_SIU/RXCMD_INST/scmd_present_0_ 2.429 i_SIU/RXCMD_INST/reg_scmd_req:D (r) 2.429 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.408 net: SIU_RXCLK_cb 2.068 i_SIU/RXCMD_INST/reg_scmd_req:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.068 i_SIU/RXCMD_INST/reg_scmd_req:D 2.068 data required time Expanded Path 8 From: i_SIU/RXDATA_INST/reg_rxdf_d(11):CLK To: i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD11 data arrival time 2.668 data required time - 2.190 slack 0.478 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.318 net: SIU_RXCLK_cb 1.978 i_SIU/RXDATA_INST/reg_rxdf_d(11):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.184 i_SIU/RXDATA_INST/reg_rxdf_d(11):Q (r) + 0.484 net: i_SIU/s_rxdf_d_11_ 2.668 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD11 (r) 2.668 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.530 net: SIU_RXCLK_cb 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WCLK (r) + 0.000 Library hold time: ADLIB:FIFO4K18 2.190 i_SIU/RXDF_INST_rxdf_core_inst_FIFOBLOCK_0_inst:WD11 2.190 data required time Expanded Path 9 From: i_SIU/RXDATA_INST/reg_rxd_present(1):CLK To: i_SIU/RXDATA_INST/reg_b_osinfr:D data arrival time 2.555 data required time - 2.068 slack 0.487 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.329 net: SIU_RXCLK_cb 1.989 i_SIU/RXDATA_INST/reg_rxd_present(1):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.195 i_SIU/RXDATA_INST/reg_rxd_present(1):Q (r) + 0.119 net: i_SIU/RXDATA_INST/rxd_present_1_ 2.314 i_SIU/RXDATA_INST/b_osinfr_2n29ss1:A (r) + 0.125 cell: ADLIB:AND3C 2.439 i_SIU/RXDATA_INST/b_osinfr_2n29ss1:Y (f) + 0.116 net: i_SIU/RXDATA_INST/b_osinfr_2n29ss1 2.555 i_SIU/RXDATA_INST/reg_b_osinfr:D (f) 2.555 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.408 net: SIU_RXCLK_cb 2.068 i_SIU/RXDATA_INST/reg_b_osinfr:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.068 i_SIU/RXDATA_INST/reg_b_osinfr:D 2.068 data required time Expanded Path 10 From: i_SIU/reg_q(14):CLK To: i_SIU/reg_q(14):D data arrival time 2.561 data required time - 2.068 slack 0.493 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.329 net: SIU_RXCLK_cb 1.989 i_SIU/reg_q(14):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.195 i_SIU/reg_q(14):Q (r) + 0.119 net: i_SIU/a_3_ 2.314 i_SIU/ix21084z21032:A (r) + 0.123 cell: ADLIB:XA1A 2.437 i_SIU/ix21084z21032:Y (r) + 0.124 net: i_SIU/nx21084z1 2.561 i_SIU/reg_q(14):D (r) 2.561 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 0.482 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 0.898 net: SIU_RXCLK_i 1.395 cbuf_SIU_RXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.660 cbuf_SIU_RXCLK:Y (r) + 0.408 net: SIU_RXCLK_cb 2.068 i_SIU/reg_q(14):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.068 i_SIU/reg_q(14):D 2.068 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SIU_RXD(2) To: addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.326 Path 2 From: SIU_RXD(3) To: addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.326 Path 3 From: SIU_RXD(0) To: addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.326 Path 4 From: SIU_RXD(1) To: addds[1].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.326 Path 5 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.315 Path 6 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.315 Path 7 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.315 Path 8 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.315 Path 9 From: SIU_RXD(10) To: addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.315 Path 10 From: SIU_RXD(15) To: addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 2.174 Slack (ns): Arrival (ns): 2.174 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.315 Expanded Path 1 From: SIU_RXD(2) To: addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(2) (f) + 0.000 net: SIU_RXD_2_ 0.000 addds[2].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[2].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[2]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 2 From: SIU_RXD(3) To: addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(3) (f) + 0.000 net: SIU_RXD_3_ 0.000 addds[3].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[3].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[3]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 3 From: SIU_RXD(0) To: addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(0) (f) + 0.000 net: SIU_RXD_0_ 0.000 addds[0].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[0].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[0]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 4 From: SIU_RXD(1) To: addds[1].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(1) (f) + 0.000 net: SIU_RXD_1_ 0.000 addds[1].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[1].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[1]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[1].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 5 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXDV (f) + 0.000 net: SIU_RXDV 0.000 ibuf_SIU_RXDV_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 ibuf_SIU_RXDV_ib/U0/U0:Y (f) + 0.000 net: ibuf_SIU_RXDV_ib/U0/NET1 2.174 ibuf_SIU_RXDV_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C ibuf_SIU_RXDV_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXDV_ib/U0/U1:YIN Expanded Path 6 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(7) (f) + 0.000 net: SIU_RXD_7_ 0.000 addds[7].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[7].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[7]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 7 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXER (f) + 0.000 net: SIU_RXER 0.000 ibuf_SIU_RXER_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 ibuf_SIU_RXER_ib/U0/U0:Y (f) + 0.000 net: ibuf_SIU_RXER_ib/U0/NET1 2.174 ibuf_SIU_RXER_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C ibuf_SIU_RXER_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXER_ib/U0/U1:YIN Expanded Path 8 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(9) (f) + 0.000 net: SIU_RXD_9_ 0.000 addds[9].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[9].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[9]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 9 From: SIU_RXD(10) To: addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(10) (f) + 0.000 net: SIU_RXD_10_ 0.000 addds[10].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[10].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[10]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[10].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 10 From: SIU_RXD(15) To: addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN data arrival time 2.174 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(15) (f) + 0.000 net: SIU_RXD_15_ 0.000 addds[15].ibuf_SIU_RXD_ib/U0/U0:PAD (f) + 2.174 cell: ADLIB:IOPAD_IN 2.174 addds[15].ibuf_SIU_RXD_ib/U0/U0:Y (f) + 0.000 net: addds[15]_ibuf_SIU_RXD_ib/U0/NET1 2.174 addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN (f) 2.174 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_IRC N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN END SET External Hold ---------------------------------------------------- SET Clock to Output No Path END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.049 Slack (ns): Arrival (ns): 4.049 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.549 Path 2 From: PUSHB To: addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.147 Slack (ns): Arrival (ns): 4.147 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.647 Path 3 From: RST_n To: addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.173 Slack (ns): Arrival (ns): 4.173 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.673 Path 4 From: RST_n To: addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.189 Slack (ns): Arrival (ns): 4.189 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.700 Path 5 From: PUSHB To: addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.271 Slack (ns): Arrival (ns): 4.271 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.771 Path 6 From: PUSHB To: addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.287 Slack (ns): Arrival (ns): 4.287 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.798 Path 7 From: RST_n To: addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.310 Slack (ns): Arrival (ns): 4.310 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.821 Path 8 From: RST_n To: addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.375 Slack (ns): Arrival (ns): 4.375 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.875 Path 9 From: RST_n To: addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.397 Slack (ns): Arrival (ns): 4.397 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.908 Path 10 From: PUSHB To: addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 4.408 Slack (ns): Arrival (ns): 4.408 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.919 Expanded Path 1 From: RST_n To: addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.049 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.477 net: not_rst_n 4.049 addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.049 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 2 From: PUSHB To: addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.147 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 1.477 net: not_rst_n 4.147 addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.147 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[0].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 3 From: RST_n To: addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.173 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.601 net: not_rst_n 4.173 addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.173 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 4 From: RST_n To: addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.189 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.617 net: not_rst_n 4.189 addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.189 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 5 From: PUSHB To: addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.271 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 1.601 net: not_rst_n 4.271 addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.271 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[1].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 6 From: PUSHB To: addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.287 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 1.617 net: not_rst_n 4.287 addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.287 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 7 From: RST_n To: addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.310 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.738 net: not_rst_n 4.310 addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.310 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 8 From: RST_n To: addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.375 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.803 net: not_rst_n 4.375 addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.375 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.416 net: SIU_RXCLK_cb N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 9 From: RST_n To: addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.397 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.825 net: not_rst_n 4.397 addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.397 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[6].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 10 From: PUSHB To: addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR data arrival time 4.408 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 1.738 net: not_rst_n 4.408 addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 4.408 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.128 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.405 net: SIU_RXCLK_cb N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) + 0.000 Library removal time: ADLIB:IOIN_IRC N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain SIU_TXCLK SET Register to Register Path 1 From: i_SIU/FRAMING_INST/reg_tx_er_r1:CLK To: i_SIU/FRAMING_INST/reg_tx_er_r2:D Delay (ns): 0.330 Slack (ns): 0.277 Arrival (ns): 2.434 Required (ns): 2.157 Hold (ns): 0.000 Path 2 From: i_SIU/CMSIU_INST/reg_v_txst_d0(29):CLK To: i_SIU/CMSIU_INST/reg_txst_data(29):D Delay (ns): 0.330 Slack (ns): 0.294 Arrival (ns): 2.470 Required (ns): 2.176 Hold (ns): 0.000 Path 3 From: i_SIU/FRAMING_INST/reg_txd_dxd(5):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(5):D Delay (ns): 0.330 Slack (ns): 0.294 Arrival (ns): 2.451 Required (ns): 2.157 Hold (ns): 0.000 Path 4 From: i_SIU/FRAMING_INST/reg_txd_dxd(4):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(4):D Delay (ns): 0.330 Slack (ns): 0.298 Arrival (ns): 2.455 Required (ns): 2.157 Hold (ns): 0.000 Path 5 From: i_SIU/FRAMING_INST/reg_txd_dxd(3):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(3):D Delay (ns): 0.330 Slack (ns): 0.298 Arrival (ns): 2.455 Required (ns): 2.157 Hold (ns): 0.000 Path 6 From: i_SIU/FRAMING_INST/reg_tx_en_r1:CLK To: i_SIU/FRAMING_INST/reg_tx_en_r2:D Delay (ns): 0.330 Slack (ns): 0.298 Arrival (ns): 2.455 Required (ns): 2.157 Hold (ns): 0.000 Path 7 From: i_SIU/FRAMING_INST/reg_tx_er_r2:CLK To: i_SIU/FRAMING_INST/reg_tx_er:D Delay (ns): 0.330 Slack (ns): 0.298 Arrival (ns): 2.455 Required (ns): 2.157 Hold (ns): 0.000 Path 8 From: i_SIU/FRAMING_INST/reg_txd_dxd(0):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(0):D Delay (ns): 0.330 Slack (ns): 0.298 Arrival (ns): 2.455 Required (ns): 2.157 Hold (ns): 0.000 Path 9 From: i_SIU/FRAMING_INST/reg_txd_dxd(11):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(11):D Delay (ns): 0.330 Slack (ns): 0.299 Arrival (ns): 2.450 Required (ns): 2.151 Hold (ns): 0.000 Path 10 From: i_SIU/INST_PARCHK_TXDF_reg_ena_d1:CLK To: i_SIU/INST_PARCHK_TXDF_reg_ena_d2:D Delay (ns): 0.330 Slack (ns): 0.299 Arrival (ns): 2.450 Required (ns): 2.151 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/FRAMING_INST/reg_tx_er_r1:CLK To: i_SIU/FRAMING_INST/reg_tx_er_r2:D data arrival time 2.434 data required time - 2.157 slack 0.277 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.477 net: SIU_TXCLK_cb 2.104 i_SIU/FRAMING_INST/reg_tx_er_r1:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.310 i_SIU/FRAMING_INST/reg_tx_er_r1:Q (r) + 0.124 net: i_SIU/FRAMING_INST/tx_er_r1 2.434 i_SIU/FRAMING_INST/reg_tx_er_r2:D (r) 2.434 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_tx_er_r2:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_tx_er_r2:D 2.157 data required time Expanded Path 2 From: i_SIU/CMSIU_INST/reg_v_txst_d0(29):CLK To: i_SIU/CMSIU_INST/reg_txst_data(29):D data arrival time 2.470 data required time - 2.176 slack 0.294 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/CMSIU_INST/reg_v_txst_d0(29):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.346 i_SIU/CMSIU_INST/reg_v_txst_d0(29):Q (r) + 0.124 net: i_SIU/CMSIU_INST/txst_data_2n8s4_29_ 2.470 i_SIU/CMSIU_INST/reg_txst_data(29):D (r) 2.470 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/CMSIU_INST/reg_txst_data(29):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.176 i_SIU/CMSIU_INST/reg_txst_data(29):D 2.176 data required time Expanded Path 3 From: i_SIU/FRAMING_INST/reg_txd_dxd(5):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(5):D data arrival time 2.451 data required time - 2.157 slack 0.294 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.494 net: SIU_TXCLK_cb 2.121 i_SIU/FRAMING_INST/reg_txd_dxd(5):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.327 i_SIU/FRAMING_INST/reg_txd_dxd(5):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_5_ 2.451 i_SIU/FRAMING_INST/reg_txd_diag(5):D (r) 2.451 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_txd_diag(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_txd_diag(5):D 2.157 data required time Expanded Path 4 From: i_SIU/FRAMING_INST/reg_txd_dxd(4):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(4):D data arrival time 2.455 data required time - 2.157 slack 0.298 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.498 net: SIU_TXCLK_cb 2.125 i_SIU/FRAMING_INST/reg_txd_dxd(4):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.331 i_SIU/FRAMING_INST/reg_txd_dxd(4):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_4_ 2.455 i_SIU/FRAMING_INST/reg_txd_diag(4):D (r) 2.455 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_txd_diag(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_txd_diag(4):D 2.157 data required time Expanded Path 5 From: i_SIU/FRAMING_INST/reg_txd_dxd(3):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(3):D data arrival time 2.455 data required time - 2.157 slack 0.298 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.498 net: SIU_TXCLK_cb 2.125 i_SIU/FRAMING_INST/reg_txd_dxd(3):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.331 i_SIU/FRAMING_INST/reg_txd_dxd(3):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_3_ 2.455 i_SIU/FRAMING_INST/reg_txd_diag(3):D (r) 2.455 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_txd_diag(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_txd_diag(3):D 2.157 data required time Expanded Path 6 From: i_SIU/FRAMING_INST/reg_tx_en_r1:CLK To: i_SIU/FRAMING_INST/reg_tx_en_r2:D data arrival time 2.455 data required time - 2.157 slack 0.298 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.498 net: SIU_TXCLK_cb 2.125 i_SIU/FRAMING_INST/reg_tx_en_r1:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.331 i_SIU/FRAMING_INST/reg_tx_en_r1:Q (r) + 0.124 net: i_SIU/FRAMING_INST/tx_en_r1 2.455 i_SIU/FRAMING_INST/reg_tx_en_r2:D (r) 2.455 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_tx_en_r2:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_tx_en_r2:D 2.157 data required time Expanded Path 7 From: i_SIU/FRAMING_INST/reg_tx_er_r2:CLK To: i_SIU/FRAMING_INST/reg_tx_er:D data arrival time 2.455 data required time - 2.157 slack 0.298 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.498 net: SIU_TXCLK_cb 2.125 i_SIU/FRAMING_INST/reg_tx_er_r2:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.331 i_SIU/FRAMING_INST/reg_tx_er_r2:Q (r) + 0.124 net: i_SIU/FRAMING_INST/tx_er_r2 2.455 i_SIU/FRAMING_INST/reg_tx_er:D (r) 2.455 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_tx_er:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_tx_er:D 2.157 data required time Expanded Path 8 From: i_SIU/FRAMING_INST/reg_txd_dxd(0):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(0):D data arrival time 2.455 data required time - 2.157 slack 0.298 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.498 net: SIU_TXCLK_cb 2.125 i_SIU/FRAMING_INST/reg_txd_dxd(0):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.331 i_SIU/FRAMING_INST/reg_txd_dxd(0):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_0_ 2.455 i_SIU/FRAMING_INST/reg_txd_diag(0):D (r) 2.455 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.530 net: SIU_TXCLK_cb 2.157 i_SIU/FRAMING_INST/reg_txd_diag(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.157 i_SIU/FRAMING_INST/reg_txd_diag(0):D 2.157 data required time Expanded Path 9 From: i_SIU/FRAMING_INST/reg_txd_dxd(11):CLK To: i_SIU/FRAMING_INST/reg_txd_diag(11):D data arrival time 2.450 data required time - 2.151 slack 0.299 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.493 net: SIU_TXCLK_cb 2.120 i_SIU/FRAMING_INST/reg_txd_dxd(11):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.326 i_SIU/FRAMING_INST/reg_txd_dxd(11):Q (r) + 0.124 net: i_SIU/FRAMING_INST/txd_dxd_11_ 2.450 i_SIU/FRAMING_INST/reg_txd_diag(11):D (r) 2.450 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.524 net: SIU_TXCLK_cb 2.151 i_SIU/FRAMING_INST/reg_txd_diag(11):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.151 i_SIU/FRAMING_INST/reg_txd_diag(11):D 2.151 data required time Expanded Path 10 From: i_SIU/INST_PARCHK_TXDF_reg_ena_d1:CLK To: i_SIU/INST_PARCHK_TXDF_reg_ena_d2:D data arrival time 2.450 data required time - 2.151 slack 0.299 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.493 net: SIU_TXCLK_cb 2.120 i_SIU/INST_PARCHK_TXDF_reg_ena_d1:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.326 i_SIU/INST_PARCHK_TXDF_reg_ena_d1:Q (r) + 0.124 net: i_SIU/INST_PARCHK_TXDF_ena_d1 2.450 i_SIU/INST_PARCHK_TXDF_reg_ena_d2:D (r) 2.450 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.524 net: SIU_TXCLK_cb 2.151 i_SIU/INST_PARCHK_TXDF_reg_ena_d2:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.151 i_SIU/INST_PARCHK_TXDF_reg_ena_d2:D 2.151 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SFP_TX_FAULT To: i_SIU/reg_s_ot_tf:D Delay (ns): 1.071 Slack (ns): Arrival (ns): 1.071 Required (ns): Hold (ns): 0.000 External Hold (ns): 1.525 Path 2 From: SIU_RECV_LOS To: i_SIU/reg_s_ot_sd:D Delay (ns): 2.130 Slack (ns): Arrival (ns): 2.130 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.489 Path 3 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(3):D Delay (ns): 2.225 Slack (ns): Arrival (ns): 2.225 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.415 Path 4 From: PUSHB To: reg_q(21):D Delay (ns): 2.179 Slack (ns): Arrival (ns): 2.179 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.407 Path 5 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(0):D Delay (ns): 2.272 Slack (ns): Arrival (ns): 2.272 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.351 Path 6 From: PUSHB To: reg_q(16):E Delay (ns): 2.289 Slack (ns): Arrival (ns): 2.289 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.288 Path 7 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(2):D Delay (ns): 2.358 Slack (ns): Arrival (ns): 2.358 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.275 Path 8 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(1):D Delay (ns): 2.358 Slack (ns): Arrival (ns): 2.358 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.275 Path 9 From: PUSHB To: reg_q(16):D Delay (ns): 2.305 Slack (ns): Arrival (ns): 2.305 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.272 Path 10 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(4):D Delay (ns): 2.363 Slack (ns): Arrival (ns): 2.363 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.260 Expanded Path 1 From: SFP_TX_FAULT To: i_SIU/reg_s_ot_tf:D data arrival time 1.071 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFP_TX_FAULT (f) + 0.000 net: SFP_TX_FAULT 0.000 ibuf_SFP_TX_FAULT_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFP_TX_FAULT_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFP_TX_FAULT_ib/U0/NET1 0.470 ibuf_SFP_TX_FAULT_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFP_TX_FAULT_ib/U0/U1:Y (f) + 0.587 net: SFP_TX_FAULT_i 1.071 i_SIU/reg_s_ot_tf:D (f) 1.071 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.555 net: SIU_TXCLK_cb N/C i_SIU/reg_s_ot_tf:CLK (r) + 0.000 Library hold time: ADLIB:DFN1 N/C i_SIU/reg_s_ot_tf:D Expanded Path 2 From: SIU_RECV_LOS To: i_SIU/reg_s_ot_sd:D data arrival time 2.130 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RECV_LOS (f) + 0.000 net: SIU_RECV_LOS 0.000 ibuf_SIU_RECV_LOS_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 ibuf_SIU_RECV_LOS_ib/U0/U0:Y (f) + 0.000 net: ibuf_SIU_RECV_LOS_ib/U0/NET1 0.286 ibuf_SIU_RECV_LOS_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.300 ibuf_SIU_RECV_LOS_ib/U0/U1:Y (f) + 1.107 net: SIU_RECV_LOS_i 1.407 i_SIU/not_ot_los:A (f) + 0.190 cell: ADLIB:INV 1.597 i_SIU/not_ot_los:Y (r) + 0.533 net: i_SIU/not_ot_los 2.130 i_SIU/reg_s_ot_sd:D (r) 2.130 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.578 net: SIU_TXCLK_cb N/C i_SIU/reg_s_ot_sd:CLK (r) + 0.000 Library hold time: ADLIB:DFN1 N/C i_SIU/reg_s_ot_sd:D Expanded Path 3 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(3):D data arrival time 2.225 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFPP_SDO (f) + 0.000 net: SFPP_SDO 0.000 ibuf_SFPP_SDO_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFPP_SDO_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFPP_SDO_ib/U0/NET1 0.470 ibuf_SFPP_SDO_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFPP_SDO_ib/U0/U1:Y (f) + 1.410 net: SFPP_SDO_i 1.894 i_SIU/INST_PMIF/ix28284z14896:B (f) + 0.215 cell: ADLIB:MX2 2.109 i_SIU/INST_PMIF/ix28284z14896:Y (f) + 0.116 net: i_SIU/INST_PMIF/nx28284z1 2.225 i_SIU/INST_PMIF/reg_pm_value_int(3):D (f) 2.225 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.599 net: SIU_TXCLK_cb N/C i_SIU/INST_PMIF/reg_pm_value_int(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/INST_PMIF/reg_pm_value_int(3):D Expanded Path 4 From: PUSHB To: reg_q(21):D data arrival time 2.179 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (f) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (f) + 0.534 cell: ADLIB:IOPAD_IN 0.534 ibuf_PUSHB_ib/U0/U0:Y (f) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.534 ibuf_PUSHB_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.548 ibuf_PUSHB_ib/U0/U1:Y (f) + 1.278 net: PUSHB_i 1.826 ix29062z2956:C (f) + 0.237 cell: ADLIB:AND3A 2.063 ix29062z2956:Y (f) + 0.116 net: nx29062z1 2.179 reg_q(21):D (f) 2.179 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.545 net: SIU_TXCLK_cb N/C reg_q(21):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(21):D Expanded Path 5 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(0):D data arrival time 2.272 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFPP_SDO (f) + 0.000 net: SFPP_SDO 0.000 ibuf_SFPP_SDO_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFPP_SDO_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFPP_SDO_ib/U0/NET1 0.470 ibuf_SFPP_SDO_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFPP_SDO_ib/U0/U1:Y (f) + 1.457 net: SFPP_SDO_i 1.941 i_SIU/INST_PMIF/ix31275z14896:B (f) + 0.215 cell: ADLIB:MX2 2.156 i_SIU/INST_PMIF/ix31275z14896:Y (f) + 0.116 net: i_SIU/INST_PMIF/nx31275z1 2.272 i_SIU/INST_PMIF/reg_pm_value_int(0):D (f) 2.272 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.582 net: SIU_TXCLK_cb N/C i_SIU/INST_PMIF/reg_pm_value_int(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/INST_PMIF/reg_pm_value_int(0):D Expanded Path 6 From: PUSHB To: reg_q(16):E data arrival time 2.289 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (f) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (f) + 0.534 cell: ADLIB:IOPAD_IN 0.534 ibuf_PUSHB_ib/U0/U0:Y (f) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.534 ibuf_PUSHB_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.548 ibuf_PUSHB_ib/U0/U1:Y (f) + 1.395 net: PUSHB_i 1.943 ix23078z24338:B (f) + 0.227 cell: ADLIB:NAND3 2.170 ix23078z24338:Y (r) + 0.119 net: nx23078z2 2.289 reg_q(16):E (r) 2.289 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.536 net: SIU_TXCLK_cb N/C reg_q(16):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(16):E Expanded Path 7 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(2):D data arrival time 2.358 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFPP_SDO (f) + 0.000 net: SFPP_SDO 0.000 ibuf_SFPP_SDO_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFPP_SDO_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFPP_SDO_ib/U0/NET1 0.470 ibuf_SFPP_SDO_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFPP_SDO_ib/U0/U1:Y (f) + 1.541 net: SFPP_SDO_i 2.025 i_SIU/INST_PMIF/ix29281z14896:B (f) + 0.215 cell: ADLIB:MX2 2.240 i_SIU/INST_PMIF/ix29281z14896:Y (f) + 0.118 net: i_SIU/INST_PMIF/nx29281z1 2.358 i_SIU/INST_PMIF/reg_pm_value_int(2):D (f) 2.358 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.592 net: SIU_TXCLK_cb N/C i_SIU/INST_PMIF/reg_pm_value_int(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/INST_PMIF/reg_pm_value_int(2):D Expanded Path 8 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(1):D data arrival time 2.358 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFPP_SDO (f) + 0.000 net: SFPP_SDO 0.000 ibuf_SFPP_SDO_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFPP_SDO_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFPP_SDO_ib/U0/NET1 0.470 ibuf_SFPP_SDO_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFPP_SDO_ib/U0/U1:Y (f) + 1.541 net: SFPP_SDO_i 2.025 i_SIU/INST_PMIF/ix30278z14896:B (f) + 0.215 cell: ADLIB:MX2 2.240 i_SIU/INST_PMIF/ix30278z14896:Y (f) + 0.118 net: i_SIU/INST_PMIF/nx30278z1 2.358 i_SIU/INST_PMIF/reg_pm_value_int(1):D (f) 2.358 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.592 net: SIU_TXCLK_cb N/C i_SIU/INST_PMIF/reg_pm_value_int(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/INST_PMIF/reg_pm_value_int(1):D Expanded Path 9 From: PUSHB To: reg_q(16):D data arrival time 2.305 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (f) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (f) + 0.534 cell: ADLIB:IOPAD_IN 0.534 ibuf_PUSHB_ib/U0/U0:Y (f) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.534 ibuf_PUSHB_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.548 ibuf_PUSHB_ib/U0/U1:Y (f) + 1.402 net: PUSHB_i 1.950 ix23078z2956:C (f) + 0.237 cell: ADLIB:AND3A 2.187 ix23078z2956:Y (f) + 0.118 net: nx23078z1 2.305 reg_q(16):D (f) 2.305 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.536 net: SIU_TXCLK_cb N/C reg_q(16):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 N/C reg_q(16):D Expanded Path 10 From: SFPP_SDO To: i_SIU/INST_PMIF/reg_pm_value_int(4):D data arrival time 2.363 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SFPP_SDO (f) + 0.000 net: SFPP_SDO 0.000 ibuf_SFPP_SDO_ib/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_IN 0.470 ibuf_SFPP_SDO_ib/U0/U0:Y (f) + 0.000 net: ibuf_SFPP_SDO_ib/U0/NET1 0.470 ibuf_SFPP_SDO_ib/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.484 ibuf_SFPP_SDO_ib/U0/U1:Y (f) + 1.548 net: SFPP_SDO_i 2.032 i_SIU/INST_PMIF/ix27287z14896:B (f) + 0.215 cell: ADLIB:MX2 2.247 i_SIU/INST_PMIF/ix27287z14896:Y (f) + 0.116 net: i_SIU/INST_PMIF/nx27287z1 2.363 i_SIU/INST_PMIF/reg_pm_value_int(4):D (f) 2.363 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.582 net: SIU_TXCLK_cb N/C i_SIU/INST_PMIF/reg_pm_value_int(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/INST_PMIF/reg_pm_value_int(4):D END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(2) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.130 Required (ns): Clock to Out (ns): 3.130 Path 2 From: addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(3) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.130 Required (ns): Clock to Out (ns): 3.130 Path 3 From: addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(6) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.130 Required (ns): Clock to Out (ns): 3.130 Path 4 From: addds[8].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(8) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.130 Required (ns): Clock to Out (ns): 3.130 Path 5 From: addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(0) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.133 Required (ns): Clock to Out (ns): 3.133 Path 6 From: addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(1) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.133 Required (ns): Clock to Out (ns): 3.133 Path 7 From: addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(4) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.133 Required (ns): Clock to Out (ns): 3.133 Path 8 From: addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(5) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.133 Required (ns): Clock to Out (ns): 3.133 Path 9 From: addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(7) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.133 Required (ns): Clock to Out (ns): 3.133 Path 10 From: addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(9) Delay (ns): 1.070 Slack (ns): Arrival (ns): 3.133 Required (ns): Clock to Out (ns): 3.133 Expanded Path 1 From: addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(2) data arrival time 3.130 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.433 net: SIU_TXCLK_cb 2.060 addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.339 addds[2].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[2]_obuf_SIU_TXD_U1/U0/NET1 2.339 addds[2].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.130 addds[2].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_2_ 3.130 SIU_TXD(2) (r) 3.130 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(2) (r) Expanded Path 2 From: addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(3) data arrival time 3.130 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.433 net: SIU_TXCLK_cb 2.060 addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.339 addds[3].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[3]_obuf_SIU_TXD_U1/U0/NET1 2.339 addds[3].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.130 addds[3].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_3_ 3.130 SIU_TXD(3) (r) 3.130 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(3) (r) Expanded Path 3 From: addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(6) data arrival time 3.130 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.433 net: SIU_TXCLK_cb 2.060 addds[6].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.339 addds[6].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[6]_obuf_SIU_TXD_U1/U0/NET1 2.339 addds[6].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.130 addds[6].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_6_ 3.130 SIU_TXD(6) (r) 3.130 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(6) (r) Expanded Path 4 From: addds[8].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(8) data arrival time 3.130 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.433 net: SIU_TXCLK_cb 2.060 addds[8].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.339 addds[8].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[8]_obuf_SIU_TXD_U1/U0/NET1 2.339 addds[8].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.130 addds[8].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_8_ 3.130 SIU_TXD(8) (r) 3.130 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(8) (r) Expanded Path 5 From: addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(0) data arrival time 3.133 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.436 net: SIU_TXCLK_cb 2.063 addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.342 addds[0].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[0]_obuf_SIU_TXD_U1/U0/NET1 2.342 addds[0].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.133 addds[0].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_0_ 3.133 SIU_TXD(0) (r) 3.133 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(0) (r) Expanded Path 6 From: addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(1) data arrival time 3.133 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.436 net: SIU_TXCLK_cb 2.063 addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.342 addds[1].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[1]_obuf_SIU_TXD_U1/U0/NET1 2.342 addds[1].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.133 addds[1].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_1_ 3.133 SIU_TXD(1) (r) 3.133 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(1) (r) Expanded Path 7 From: addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(4) data arrival time 3.133 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.436 net: SIU_TXCLK_cb 2.063 addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.342 addds[4].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[4]_obuf_SIU_TXD_U1/U0/NET1 2.342 addds[4].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.133 addds[4].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_4_ 3.133 SIU_TXD(4) (r) 3.133 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(4) (r) Expanded Path 8 From: addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(5) data arrival time 3.133 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.436 net: SIU_TXCLK_cb 2.063 addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.342 addds[5].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[5]_obuf_SIU_TXD_U1/U0/NET1 2.342 addds[5].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.133 addds[5].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_5_ 3.133 SIU_TXD(5) (r) 3.133 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(5) (r) Expanded Path 9 From: addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(7) data arrival time 3.133 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.436 net: SIU_TXCLK_cb 2.063 addds[7].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.342 addds[7].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[7]_obuf_SIU_TXD_U1/U0/NET1 2.342 addds[7].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.133 addds[7].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_7_ 3.133 SIU_TXD(7) (r) 3.133 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(7) (r) Expanded Path 10 From: addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(9) data arrival time 3.133 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.436 net: SIU_TXCLK_cb 2.063 addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.279 cell: ADLIB:IOTRI_ORC_EB 2.342 addds[9].obuf_SIU_TXD_U1/U0/U1:DOUT (r) + 0.000 net: addds[9]_obuf_SIU_TXD_U1/U0/NET1 2.342 addds[9].obuf_SIU_TXD_U1/U0/U0:D (r) + 0.791 cell: ADLIB:IOPAD_TRI 3.133 addds[9].obuf_SIU_TXD_U1/U0/U0:PAD (r) + 0.000 net: SIU_TXD_9_ 3.133 SIU_TXD(9) (r) 3.133 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(9) (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_hwidstw(25):CLR Delay (ns): 0.527 Slack (ns): 0.491 Arrival (ns): 2.667 Required (ns): 2.176 Removal (ns): 0.000 Skew (ns): -0.036 Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sfrm(7):CLR Delay (ns): 0.527 Slack (ns): 0.491 Arrival (ns): 2.667 Required (ns): 2.176 Removal (ns): 0.000 Skew (ns): -0.036 Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts1(7):CLR Delay (ns): 0.527 Slack (ns): 0.491 Arrival (ns): 2.667 Required (ns): 2.176 Removal (ns): 0.000 Skew (ns): -0.036 Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_siustw(20):CLR Delay (ns): 0.527 Slack (ns): 0.491 Arrival (ns): 2.667 Required (ns): 2.176 Removal (ns): 0.000 Skew (ns): -0.036 Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_i2c_addr(3):CLR Delay (ns): 0.527 Slack (ns): 0.491 Arrival (ns): 2.667 Required (ns): 2.176 Removal (ns): 0.000 Skew (ns): -0.036 Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(3):CLR Delay (ns): 0.527 Slack (ns): 0.525 Arrival (ns): 2.667 Required (ns): 2.142 Removal (ns): 0.000 Skew (ns): -0.002 Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts1(11):CLR Delay (ns): 0.527 Slack (ns): 0.525 Arrival (ns): 2.667 Required (ns): 2.142 Removal (ns): 0.000 Skew (ns): -0.002 Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(19):CLR Delay (ns): 0.527 Slack (ns): 0.525 Arrival (ns): 2.667 Required (ns): 2.142 Removal (ns): 0.000 Skew (ns): -0.002 Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_siustw(24):CLR Delay (ns): 0.688 Slack (ns): 0.652 Arrival (ns): 2.828 Required (ns): 2.176 Removal (ns): 0.000 Skew (ns): -0.036 Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(20):CLR Delay (ns): 0.688 Slack (ns): 0.686 Arrival (ns): 2.828 Required (ns): 2.142 Removal (ns): 0.000 Skew (ns): -0.002 Expanded Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_hwidstw(25):CLR data arrival time 2.667 data required time - 2.176 slack 0.491 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/CMSIU_INST/reg_v_hwidstw(25):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/CMSIU_INST/reg_v_hwidstw(25):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.176 i_SIU/CMSIU_INST/reg_v_hwidstw(25):CLR 2.176 data required time Expanded Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sfrm(7):CLR data arrival time 2.667 data required time - 2.176 slack 0.491 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/FRAMING_INST/reg_txd_sfrm(7):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/FRAMING_INST/reg_txd_sfrm(7):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.176 i_SIU/FRAMING_INST/reg_txd_sfrm(7):CLR 2.176 data required time Expanded Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts1(7):CLR data arrival time 2.667 data required time - 2.176 slack 0.491 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/FRAMING_INST/reg_txd_sts1(7):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/FRAMING_INST/reg_txd_sts1(7):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.176 i_SIU/FRAMING_INST/reg_txd_sts1(7):CLR 2.176 data required time Expanded Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_siustw(20):CLR data arrival time 2.667 data required time - 2.176 slack 0.491 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/CMSIU_INST/reg_v_siustw(20):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/CMSIU_INST/reg_v_siustw(20):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.176 i_SIU/CMSIU_INST/reg_v_siustw(20):CLR 2.176 data required time Expanded Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_i2c_addr(3):CLR data arrival time 2.667 data required time - 2.176 slack 0.491 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/CMSIU_INST/reg_v_i2c_addr(3):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/CMSIU_INST/reg_v_i2c_addr(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.176 i_SIU/CMSIU_INST/reg_v_i2c_addr(3):CLR 2.176 data required time Expanded Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(3):CLR data arrival time 2.667 data required time - 2.142 slack 0.525 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/CMSIU_INST/reg_txst_data(3):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.515 net: SIU_TXCLK_cb 2.142 i_SIU/CMSIU_INST/reg_txst_data(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.142 i_SIU/CMSIU_INST/reg_txst_data(3):CLR 2.142 data required time Expanded Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts1(11):CLR data arrival time 2.667 data required time - 2.142 slack 0.525 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/FRAMING_INST/reg_txd_sts1(11):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.515 net: SIU_TXCLK_cb 2.142 i_SIU/FRAMING_INST/reg_txd_sts1(11):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.142 i_SIU/FRAMING_INST/reg_txd_sts1(11):CLR 2.142 data required time Expanded Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(19):CLR data arrival time 2.667 data required time - 2.142 slack 0.525 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.321 net: i_SIU/s_arstn 2.667 i_SIU/CMSIU_INST/reg_txst_data(19):CLR (r) 2.667 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.515 net: SIU_TXCLK_cb 2.142 i_SIU/CMSIU_INST/reg_txst_data(19):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.142 i_SIU/CMSIU_INST/reg_txst_data(19):CLR 2.142 data required time Expanded Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_siustw(24):CLR data arrival time 2.828 data required time - 2.176 slack 0.652 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.482 net: i_SIU/s_arstn 2.828 i_SIU/CMSIU_INST/reg_v_siustw(24):CLR (r) 2.828 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.549 net: SIU_TXCLK_cb 2.176 i_SIU/CMSIU_INST/reg_v_siustw(24):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.176 i_SIU/CMSIU_INST/reg_v_siustw(24):CLR 2.176 data required time Expanded Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_txst_data(20):CLR data arrival time 2.828 data required time - 2.142 slack 0.686 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.513 net: SIU_TXCLK_cb 2.140 i_SIU/reg_s_arstn:CLK (r) + 0.206 cell: ADLIB:DFN1C1 2.346 i_SIU/reg_s_arstn:Q (r) + 0.482 net: i_SIU/s_arstn 2.828 i_SIU/CMSIU_INST/reg_txst_data(20):CLR (r) 2.828 data arrival time ________________________________________________________ Data required time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.482 cell: ADLIB:IOPAD_IN 0.482 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 0.482 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.497 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 0.865 net: SIU_TXCLK_i 1.362 cbuf_SIU_TXCLK:A (r) + 0.265 cell: ADLIB:CLKINT 1.627 cbuf_SIU_TXCLK:Y (r) + 0.515 net: SIU_TXCLK_cb 2.142 i_SIU/CMSIU_INST/reg_txst_data(20):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C0 2.142 i_SIU/CMSIU_INST/reg_txst_data(20):CLR 2.142 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: i_SIU/reg_s_arstn:CLR Delay (ns): 3.777 Slack (ns): Arrival (ns): 3.777 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.100 Path 2 From: PUSHB To: i_SIU/reg_s_arstn:CLR Delay (ns): 3.875 Slack (ns): Arrival (ns): 3.875 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.198 Path 3 From: RST_n To: addds[14].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.295 Slack (ns): Arrival (ns): 5.295 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.599 Path 4 From: PUSHB To: addds[14].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.393 Slack (ns): Arrival (ns): 5.393 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.697 Path 5 From: RST_n To: obuf_SIU_TXER_U1/U0/U1:CLR Delay (ns): 5.364 Slack (ns): Arrival (ns): 5.364 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.741 Path 6 From: RST_n To: obuf_SIU_TXEN_U1/U0/U1:CLR Delay (ns): 5.382 Slack (ns): Arrival (ns): 5.382 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.759 Path 7 From: PUSHB To: obuf_SIU_TXER_U1/U0/U1:CLR Delay (ns): 5.462 Slack (ns): Arrival (ns): 5.462 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.839 Path 8 From: PUSHB To: obuf_SIU_TXEN_U1/U0/U1:CLR Delay (ns): 5.480 Slack (ns): Arrival (ns): 5.480 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.857 Path 9 From: RST_n To: addds[12].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.696 Slack (ns): Arrival (ns): 5.696 Required (ns): Removal (ns): 0.000 External Removal (ns): -3.114 Path 10 From: RST_n To: addds[11].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 5.701 Slack (ns): Arrival (ns): 5.701 Required (ns): Removal (ns): 0.000 External Removal (ns): -3.119 Expanded Path 1 From: RST_n To: i_SIU/reg_s_arstn:CLR data arrival time 3.777 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.205 net: not_rst_n 3.777 i_SIU/reg_s_arstn:CLR (f) 3.777 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.636 net: SIU_TXCLK_cb N/C i_SIU/reg_s_arstn:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_SIU/reg_s_arstn:CLR Expanded Path 2 From: PUSHB To: i_SIU/reg_s_arstn:CLR data arrival time 3.875 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 1.205 net: not_rst_n 3.875 i_SIU/reg_s_arstn:CLR (f) 3.875 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.636 net: SIU_TXCLK_cb N/C i_SIU/reg_s_arstn:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_SIU/reg_s_arstn:CLR Expanded Path 3 From: RST_n To: addds[14].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.295 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 2.723 net: not_rst_n 5.295 addds[14].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.295 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.655 net: SIU_TXCLK_cb N/C addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[14].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 4 From: PUSHB To: addds[14].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.393 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 2.723 net: not_rst_n 5.393 addds[14].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.393 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.655 net: SIU_TXCLK_cb N/C addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[14].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 5 From: RST_n To: obuf_SIU_TXER_U1/U0/U1:CLR data arrival time 5.364 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 2.792 net: not_rst_n 5.364 obuf_SIU_TXER_U1/U0/U1:CLR (f) 5.364 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.582 net: SIU_TXCLK_cb N/C obuf_SIU_TXER_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C obuf_SIU_TXER_U1/U0/U1:CLR Expanded Path 6 From: RST_n To: obuf_SIU_TXEN_U1/U0/U1:CLR data arrival time 5.382 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 2.810 net: not_rst_n 5.382 obuf_SIU_TXEN_U1/U0/U1:CLR (f) 5.382 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.582 net: SIU_TXCLK_cb N/C obuf_SIU_TXEN_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C obuf_SIU_TXEN_U1/U0/U1:CLR Expanded Path 7 From: PUSHB To: obuf_SIU_TXER_U1/U0/U1:CLR data arrival time 5.462 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 2.792 net: not_rst_n 5.462 obuf_SIU_TXER_U1/U0/U1:CLR (f) 5.462 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.582 net: SIU_TXCLK_cb N/C obuf_SIU_TXER_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C obuf_SIU_TXER_U1/U0/U1:CLR Expanded Path 8 From: PUSHB To: obuf_SIU_TXEN_U1/U0/U1:CLR data arrival time 5.480 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 2.810 net: not_rst_n 5.480 obuf_SIU_TXEN_U1/U0/U1:CLR (f) 5.480 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.582 net: SIU_TXCLK_cb N/C obuf_SIU_TXEN_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C obuf_SIU_TXEN_U1/U0/U1:CLR Expanded Path 9 From: RST_n To: addds[12].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.696 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 3.124 net: not_rst_n 5.696 addds[12].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.696 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.541 net: SIU_TXCLK_cb N/C addds[12].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[12].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 10 From: RST_n To: addds[11].obuf_SIU_TXD_U1/U0/U1:CLR data arrival time 5.701 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 3.129 net: not_rst_n 5.701 addds[11].obuf_SIU_TXD_U1/U0/U1:CLR (f) 5.701 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 0.605 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.019 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.085 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.332 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.541 net: SIU_TXCLK_cb N/C addds[11].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.000 Library removal time: ADLIB:IOTRI_ORC_EB N/C addds[11].obuf_SIU_TXD_U1/U0/U1:CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_SIU/reg_tx_clk_2:Q SET Register to Register Path 1 From: i_SIU/reg_b_led_update:CLK To: i_SIU/reg_mode_sel(1):D Delay (ns): 0.572 Slack (ns): 0.548 Arrival (ns): 2.996 Required (ns): 2.448 Hold (ns): 0.000 Path 2 From: i_SIU/modgen_counter_slot_timer_reg_q(1):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(1):D Delay (ns): 0.595 Slack (ns): 0.574 Arrival (ns): 3.019 Required (ns): 2.445 Hold (ns): 0.000 Path 3 From: i_SIU/I2CIF_INST/reg_i2c_present(6):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D Delay (ns): 0.606 Slack (ns): 0.587 Arrival (ns): 3.027 Required (ns): 2.440 Hold (ns): 0.000 Path 4 From: i_SIU/I2CIF_INST/reg_b_bitct_inc:CLK To: i_SIU/I2CIF_INST/reg_bit_count(0):D Delay (ns): 0.638 Slack (ns): 0.617 Arrival (ns): 3.062 Required (ns): 2.445 Hold (ns): 0.000 Path 5 From: i_SIU/I2CIF_INST/reg_q(6):CLK To: i_SIU/I2CIF_INST/reg_q(6):D Delay (ns): 0.646 Slack (ns): 0.628 Arrival (ns): 3.060 Required (ns): 2.432 Hold (ns): 0.000 Path 6 From: i_SIU/I2CIF_INST/reg_q(5):CLK To: i_SIU/I2CIF_INST/reg_q(5):D Delay (ns): 0.646 Slack (ns): 0.628 Arrival (ns): 3.060 Required (ns): 2.432 Hold (ns): 0.000 Path 7 From: i_SIU/I2CIF_INST/reg_q(8):CLK To: i_SIU/I2CIF_INST/reg_q(8):D Delay (ns): 0.647 Slack (ns): 0.629 Arrival (ns): 3.061 Required (ns): 2.432 Hold (ns): 0.000 Path 8 From: i_SIU/modgen_counter_slot_timer_reg_q(0):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(0):D Delay (ns): 0.652 Slack (ns): 0.631 Arrival (ns): 3.076 Required (ns): 2.445 Hold (ns): 0.000 Path 9 From: i_SIU/I2CIF_INST/reg_i2c_present(14):CLK To: i_SIU/I2CIF_INST/reg_i2c_ack:D Delay (ns): 0.642 Slack (ns): 0.632 Arrival (ns): 3.056 Required (ns): 2.424 Hold (ns): 0.000 Path 10 From: i_SIU/reg_blink_timer(9):CLK To: i_SIU/reg_blink_timer(9):D Delay (ns): 0.654 Slack (ns): 0.633 Arrival (ns): 3.078 Required (ns): 2.445 Hold (ns): 0.000 Expanded Path 1 From: i_SIU/reg_b_led_update:CLK To: i_SIU/reg_mode_sel(1):D data arrival time 2.996 data required time - 2.448 slack 0.548 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.448 net: i_SIU/tx_clk_2b 2.424 i_SIU/reg_b_led_update:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.630 i_SIU/reg_b_led_update:Q (r) + 0.119 net: i_SIU/b_led_update 2.749 i_SIU/ix11369z14896:S (r) + 0.129 cell: ADLIB:MX2 2.878 i_SIU/ix11369z14896:Y (f) + 0.118 net: i_SIU/nx11369z1 2.996 i_SIU/reg_mode_sel(1):D (f) 2.996 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.472 net: i_SIU/tx_clk_2b 2.448 i_SIU/reg_mode_sel(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.448 i_SIU/reg_mode_sel(1):D 2.448 data required time Expanded Path 2 From: i_SIU/modgen_counter_slot_timer_reg_q(1):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(1):D data arrival time 3.019 data required time - 2.445 slack 0.574 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.448 net: i_SIU/tx_clk_2b 2.424 i_SIU/modgen_counter_slot_timer_reg_q(1):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.630 i_SIU/modgen_counter_slot_timer_reg_q(1):Q (r) + 0.143 net: i_SIU/slot_timer_1_ 2.773 i_SIU/ix22487z8206:C (r) + 0.122 cell: ADLIB:AX1C 2.895 i_SIU/ix22487z8206:Y (r) + 0.124 net: i_SIU/nx22487z1 3.019 i_SIU/modgen_counter_slot_timer_reg_q(1):D (r) 3.019 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.469 net: i_SIU/tx_clk_2b 2.445 i_SIU/modgen_counter_slot_timer_reg_q(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.445 i_SIU/modgen_counter_slot_timer_reg_q(1):D 2.445 data required time Expanded Path 3 From: i_SIU/I2CIF_INST/reg_i2c_present(6):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D data arrival time 3.027 data required time - 2.440 slack 0.587 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.445 net: i_SIU/tx_clk_2b 2.421 i_SIU/I2CIF_INST/reg_i2c_present(6):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.627 i_SIU/I2CIF_INST/reg_i2c_present(6):Q (r) + 0.150 net: i_SIU/I2CIF_INST/i2c_present_6_ 2.777 i_SIU/I2CIF_INST/ix26586z26293:S (r) + 0.130 cell: ADLIB:MX2A 2.907 i_SIU/I2CIF_INST/ix26586z26293:Y (f) + 0.120 net: i_SIU/I2CIF_INST/nx26586z1 3.027 i_SIU/I2CIF_INST/reg_i2c_present(6):D (f) 3.027 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.464 net: i_SIU/tx_clk_2b 2.440 i_SIU/I2CIF_INST/reg_i2c_present(6):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.440 i_SIU/I2CIF_INST/reg_i2c_present(6):D 2.440 data required time Expanded Path 4 From: i_SIU/I2CIF_INST/reg_b_bitct_inc:CLK To: i_SIU/I2CIF_INST/reg_bit_count(0):D data arrival time 3.062 data required time - 2.445 slack 0.617 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.448 net: i_SIU/tx_clk_2b 2.424 i_SIU/I2CIF_INST/reg_b_bitct_inc:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.630 i_SIU/I2CIF_INST/reg_b_bitct_inc:Q (r) + 0.124 net: i_SIU/I2CIF_INST/b_bitct_inc 2.754 i_SIU/I2CIF_INST/ix18449z21033:B (r) + 0.184 cell: ADLIB:XA1B 2.938 i_SIU/I2CIF_INST/ix18449z21033:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx18449z1 3.062 i_SIU/I2CIF_INST/reg_bit_count(0):D (r) 3.062 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.469 net: i_SIU/tx_clk_2b 2.445 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.445 i_SIU/I2CIF_INST/reg_bit_count(0):D 2.445 data required time Expanded Path 5 From: i_SIU/I2CIF_INST/reg_q(6):CLK To: i_SIU/I2CIF_INST/reg_q(6):D data arrival time 3.060 data required time - 2.432 slack 0.628 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.438 net: i_SIU/tx_clk_2b 2.414 i_SIU/I2CIF_INST/reg_q(6):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.620 i_SIU/I2CIF_INST/reg_q(6):Q (r) + 0.143 net: i_SIU/I2CIF_INST/nx59247z9 2.763 i_SIU/I2CIF_INST/ix57253z4192:C (r) + 0.173 cell: ADLIB:AXOI4 2.936 i_SIU/I2CIF_INST/ix57253z4192:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx57253z1 3.060 i_SIU/I2CIF_INST/reg_q(6):D (r) 3.060 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.456 net: i_SIU/tx_clk_2b 2.432 i_SIU/I2CIF_INST/reg_q(6):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.432 i_SIU/I2CIF_INST/reg_q(6):D 2.432 data required time Expanded Path 6 From: i_SIU/I2CIF_INST/reg_q(5):CLK To: i_SIU/I2CIF_INST/reg_q(5):D data arrival time 3.060 data required time - 2.432 slack 0.628 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.438 net: i_SIU/tx_clk_2b 2.414 i_SIU/I2CIF_INST/reg_q(5):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.620 i_SIU/I2CIF_INST/reg_q(5):Q (r) + 0.143 net: i_SIU/I2CIF_INST/nx59247z8 2.763 i_SIU/I2CIF_INST/ix56256z4192:C (r) + 0.173 cell: ADLIB:AXOI4 2.936 i_SIU/I2CIF_INST/ix56256z4192:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx56256z1 3.060 i_SIU/I2CIF_INST/reg_q(5):D (r) 3.060 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.456 net: i_SIU/tx_clk_2b 2.432 i_SIU/I2CIF_INST/reg_q(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.432 i_SIU/I2CIF_INST/reg_q(5):D 2.432 data required time Expanded Path 7 From: i_SIU/I2CIF_INST/reg_q(8):CLK To: i_SIU/I2CIF_INST/reg_q(8):D data arrival time 3.061 data required time - 2.432 slack 0.629 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.438 net: i_SIU/tx_clk_2b 2.414 i_SIU/I2CIF_INST/reg_q(8):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.620 i_SIU/I2CIF_INST/reg_q(8):Q (r) + 0.200 net: i_SIU/I2CIF_INST/scl_timer_8_ 2.820 i_SIU/I2CIF_INST/ix59247z2957:A (r) + 0.125 cell: ADLIB:AND3B 2.945 i_SIU/I2CIF_INST/ix59247z2957:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx59247z1 3.061 i_SIU/I2CIF_INST/reg_q(8):D (f) 3.061 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.456 net: i_SIU/tx_clk_2b 2.432 i_SIU/I2CIF_INST/reg_q(8):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.432 i_SIU/I2CIF_INST/reg_q(8):D 2.432 data required time Expanded Path 8 From: i_SIU/modgen_counter_slot_timer_reg_q(0):CLK To: i_SIU/modgen_counter_slot_timer_reg_q(0):D data arrival time 3.076 data required time - 2.445 slack 0.631 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.448 net: i_SIU/tx_clk_2b 2.424 i_SIU/modgen_counter_slot_timer_reg_q(0):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.630 i_SIU/modgen_counter_slot_timer_reg_q(0):Q (r) + 0.200 net: i_SIU/slot_timer_0_ 2.830 i_SIU/ix23484z10876:A (r) + 0.122 cell: ADLIB:XOR2 2.952 i_SIU/ix23484z10876:Y (r) + 0.124 net: i_SIU/nx23484z1 3.076 i_SIU/modgen_counter_slot_timer_reg_q(0):D (r) 3.076 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.469 net: i_SIU/tx_clk_2b 2.445 i_SIU/modgen_counter_slot_timer_reg_q(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.445 i_SIU/modgen_counter_slot_timer_reg_q(0):D 2.445 data required time Expanded Path 9 From: i_SIU/I2CIF_INST/reg_i2c_present(14):CLK To: i_SIU/I2CIF_INST/reg_i2c_ack:D data arrival time 3.056 data required time - 2.424 slack 0.632 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.438 net: i_SIU/tx_clk_2b 2.414 i_SIU/I2CIF_INST/reg_i2c_present(14):CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.620 i_SIU/I2CIF_INST/reg_i2c_present(14):Q (r) + 0.436 net: i_SIU/I2CIF_INST/i2c_present_14_ 3.056 i_SIU/I2CIF_INST/reg_i2c_ack:D (r) 3.056 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.448 net: i_SIU/tx_clk_2b 2.424 i_SIU/I2CIF_INST/reg_i2c_ack:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 2.424 i_SIU/I2CIF_INST/reg_i2c_ack:D 2.424 data required time Expanded Path 10 From: i_SIU/reg_blink_timer(9):CLK To: i_SIU/reg_blink_timer(9):D data arrival time 3.078 data required time - 2.445 slack 0.633 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.448 net: i_SIU/tx_clk_2b 2.424 i_SIU/reg_blink_timer(9):CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.630 i_SIU/reg_blink_timer(9):Q (r) + 0.124 net: i_SIU/blink_timer_9_ 2.754 i_SIU/ix58157z43526:A (r) + 0.206 cell: ADLIB:XO1A 2.960 i_SIU/ix58157z43526:Y (f) + 0.118 net: i_SIU/nx58157z1 3.078 i_SIU/reg_blink_timer(9):D (f) 3.078 data arrival time ________________________________________________________ Data required time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.469 net: i_SIU/tx_clk_2b 2.445 i_SIU/reg_blink_timer(9):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 2.445 i_SIU/reg_blink_timer(9):D 2.445 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Delay (ns): 2.283 Slack (ns): Arrival (ns): 2.283 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.738 Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(1):D Delay (ns): 2.283 Slack (ns): Arrival (ns): 2.283 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.737 Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Delay (ns): 2.355 Slack (ns): Arrival (ns): 2.355 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.683 Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Delay (ns): 2.422 Slack (ns): Arrival (ns): 2.422 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.606 Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(1):D Delay (ns): 2.442 Slack (ns): Arrival (ns): 2.442 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.577 Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Delay (ns): 2.777 Slack (ns): Arrival (ns): 2.777 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.252 Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Delay (ns): 2.794 Slack (ns): Arrival (ns): 2.794 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.234 Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Delay (ns): 2.796 Slack (ns): Arrival (ns): 2.796 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.232 Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Delay (ns): 2.874 Slack (ns): Arrival (ns): 2.874 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.154 Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(3):D Delay (ns): 2.929 Slack (ns): Arrival (ns): 2.929 Required (ns): Hold (ns): 0.000 External Hold (ns): 0.109 Expanded Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D data arrival time 2.283 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.466 net: SDA_ID_i 1.950 i_SIU/I2CIF_INST/ix11526z14896:A (f) + 0.215 cell: ADLIB:MX2 2.165 i_SIU/I2CIF_INST/ix11526z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx11526z1 2.283 i_SIU/I2CIF_INST/reg_i2c_rddata(3):D (f) 2.283 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.541 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Expanded Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(1):D data arrival time 2.283 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.465 net: SDA_ID_i 1.949 i_SIU/I2CIF_INST/ix9532z14896:A (f) + 0.215 cell: ADLIB:MX2 2.164 i_SIU/I2CIF_INST/ix9532z14896:Y (f) + 0.119 net: i_SIU/I2CIF_INST/nx9532z1 2.283 i_SIU/I2CIF_INST/reg_i2c_rddata(1):D (f) 2.283 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.540 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(1):D Expanded Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D data arrival time 2.355 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.538 net: SDA_ID_i 2.022 i_SIU/I2CIF_INST/ix10529z14896:A (f) + 0.215 cell: ADLIB:MX2 2.237 i_SIU/I2CIF_INST/ix10529z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx10529z1 2.355 i_SIU/I2CIF_INST/reg_i2c_rddata(2):D (f) 2.355 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.558 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Expanded Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D data arrival time 2.422 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.607 net: SDA_ID_i 2.091 i_SIU/I2CIF_INST/ix8535z14896:A (f) + 0.215 cell: ADLIB:MX2 2.306 i_SIU/I2CIF_INST/ix8535z14896:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx8535z1 2.422 i_SIU/I2CIF_INST/reg_i2c_rddata(0):D (f) 2.422 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.548 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Expanded Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(1):D data arrival time 2.442 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.339 net: SDA_ID_i 1.823 i_SIU/I2CIF_INST/ix31571z50932:B (f) + 0.128 cell: ADLIB:NAND3A 1.951 i_SIU/I2CIF_INST/ix31571z50932:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx31571z3 2.075 i_SIU/I2CIF_INST/ix31571z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.324 i_SIU/I2CIF_INST/ix31571z24337:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx31571z1 2.442 i_SIU/I2CIF_INST/reg_i2c_present(1):D (f) 2.442 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.539 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(1):D Expanded Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D data arrival time 2.777 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.960 net: SDA_ID_i 2.444 i_SIU/I2CIF_INST/ix15514z14896:A (f) + 0.215 cell: ADLIB:MX2 2.659 i_SIU/I2CIF_INST/ix15514z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx15514z1 2.777 i_SIU/I2CIF_INST/reg_i2c_rddata(7):D (f) 2.777 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.549 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Expanded Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D data arrival time 2.794 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.979 net: SDA_ID_i 2.463 i_SIU/I2CIF_INST/ix12523z14896:A (f) + 0.215 cell: ADLIB:MX2 2.678 i_SIU/I2CIF_INST/ix12523z14896:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx12523z1 2.794 i_SIU/I2CIF_INST/reg_i2c_rddata(4):D (f) 2.794 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.548 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Expanded Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D data arrival time 2.796 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.979 net: SDA_ID_i 2.463 i_SIU/I2CIF_INST/ix13520z14896:A (f) + 0.215 cell: ADLIB:MX2 2.678 i_SIU/I2CIF_INST/ix13520z14896:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx13520z1 2.796 i_SIU/I2CIF_INST/reg_i2c_rddata(5):D (f) 2.796 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.548 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Expanded Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D data arrival time 2.874 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 2.059 net: SDA_ID_i 2.543 i_SIU/I2CIF_INST/ix14517z14896:A (f) + 0.215 cell: ADLIB:MX2 2.758 i_SIU/I2CIF_INST/ix14517z14896:Y (f) + 0.116 net: i_SIU/I2CIF_INST/nx14517z1 2.874 i_SIU/I2CIF_INST/reg_i2c_rddata(6):D (f) 2.874 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.548 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Expanded Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(3):D data arrival time 2.929 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (f) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_SDA_ID/U0/U0:Y (f) + 0.000 net: bbuf_SDA_ID/U0/NET3 0.470 bbuf_SDA_ID/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_SDA_ID/U0/U1:Y (f) + 1.474 net: SDA_ID_i 1.958 i_SIU/I2CIF_INST/ix29577z26293:A (f) + 0.219 cell: ADLIB:MX2C 2.177 i_SIU/I2CIF_INST/ix29577z26293:Y (r) + 0.144 net: i_SIU/I2CIF_INST/nx29577z3 2.321 i_SIU/I2CIF_INST/ix29577z24339:A (r) + 0.141 cell: ADLIB:NAND2 2.462 i_SIU/I2CIF_INST/ix29577z24339:Y (f) + 0.118 net: i_SIU/I2CIF_INST/nx29577z2 2.580 i_SIU/I2CIF_INST/ix29577z40557:C (f) + 0.225 cell: ADLIB:AO1C 2.805 i_SIU/I2CIF_INST/ix29577z40557:Y (r) + 0.124 net: i_SIU/I2CIF_INST/nx29577z1 2.929 i_SIU/I2CIF_INST/reg_i2c_present(3):D (r) 2.929 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 2.160 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.320 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.558 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(3):D END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID Delay (ns): 2.630 Slack (ns): Arrival (ns): 5.042 Required (ns): Clock to Out (ns): 5.042 Path 2 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID Delay (ns): 3.123 Slack (ns): Arrival (ns): 5.537 Required (ns): Clock to Out (ns): 5.537 Path 3 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID Delay (ns): 3.238 Slack (ns): Arrival (ns): 5.653 Required (ns): Clock to Out (ns): 5.653 Path 4 From: i_SIU/reg_led4:CLK To: LED_SIU(4) Delay (ns): 3.643 Slack (ns): Arrival (ns): 6.057 Required (ns): Clock to Out (ns): 6.057 Path 5 From: i_SIU/reg_led3:CLK To: LED_SIU(3) Delay (ns): 3.654 Slack (ns): Arrival (ns): 6.061 Required (ns): Clock to Out (ns): 6.061 Expanded Path 1 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID data arrival time 5.042 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.436 net: i_SIU/tx_clk_2b 2.412 i_SIU/I2CIF_INST/reg_s_sda_ena:CLK (r) + 0.256 cell: ADLIB:DFN1P0 2.668 i_SIU/I2CIF_INST/reg_s_sda_ena:Q (f) + 1.154 net: SDA_ID_e 3.822 bbuf_SDA_ID/U0/U1:E (f) + 0.145 cell: ADLIB:IOBI_IB_OB_EB 3.967 bbuf_SDA_ID/U0/U1:EOUT (f) + 0.000 net: bbuf_SDA_ID/U0/NET2 3.967 bbuf_SDA_ID/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 5.042 bbuf_SDA_ID/U0/U0:PAD (r) + 0.000 net: SDA_ID 5.042 SDA_ID (r) 5.042 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (r) Expanded Path 2 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID data arrival time 5.537 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.438 net: i_SIU/tx_clk_2b 2.414 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.620 i_SIU/I2CIF_INST/reg_s_sda_out:Q (r) + 1.103 net: SDA_ID_o 3.723 bbuf_SDA_ID/U0/U1:D (r) + 0.213 cell: ADLIB:IOBI_IB_OB_EB 3.936 bbuf_SDA_ID/U0/U1:DOUT (r) + 0.000 net: bbuf_SDA_ID/U0/NET1 3.936 bbuf_SDA_ID/U0/U0:D (r) + 1.601 cell: ADLIB:IOPAD_BI 5.537 bbuf_SDA_ID/U0/U0:PAD (r) + 0.000 net: SDA_ID 5.537 SDA_ID (r) 5.537 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (r) Expanded Path 3 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID data arrival time 5.653 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.439 net: i_SIU/tx_clk_2b 2.415 i_SIU/I2CIF_INST/reg_i2c_scl:CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.621 i_SIU/I2CIF_INST/reg_i2c_scl:Q (r) + 1.218 net: SCL_ID_i 3.839 obuf_SCL_ID_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 4.052 obuf_SCL_ID_U1/U0/U1:DOUT (r) + 0.000 net: obuf_SCL_ID_U1/U0/NET1 4.052 obuf_SCL_ID_U1/U0/U0:D (r) + 1.601 cell: ADLIB:IOPAD_TRI 5.653 obuf_SCL_ID_U1/U0/U0:PAD (r) + 0.000 net: SCL_ID 5.653 SCL_ID (r) 5.653 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SCL_ID (r) Expanded Path 4 From: i_SIU/reg_led4:CLK To: LED_SIU(4) data arrival time 6.057 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.438 net: i_SIU/tx_clk_2b 2.414 i_SIU/reg_led4:CLK (r) + 0.206 cell: ADLIB:DFN1C0 2.620 i_SIU/reg_led4:Q (r) + 1.259 net: LED_SIU_i_4_ 3.879 genblk5[4].leds_siu_U1/U0/U1:D (r) + 0.231 cell: ADLIB:IOTRI_OB_EB 4.110 genblk5[4].leds_siu_U1/U0/U1:DOUT (r) + 0.000 net: genblk5[4]_leds_siu_U1/U0/NET1 4.110 genblk5[4].leds_siu_U1/U0/U0:D (r) + 1.947 cell: ADLIB:IOPAD_TRI 6.057 genblk5[4].leds_siu_U1/U0/U0:PAD (r) + 0.000 net: LED_SIU_4_ 6.057 LED_SIU(4) (r) 6.057 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(4) (r) Expanded Path 5 From: i_SIU/reg_led3:CLK To: LED_SIU(3) data arrival time 6.061 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 1.721 net: i_SIU/tx_clk_2 1.721 i_SIU/cbuf_tx_clk_2:A (r) + 0.255 cell: ADLIB:CLKINT 1.976 i_SIU/cbuf_tx_clk_2:Y (r) + 0.431 net: i_SIU/tx_clk_2b 2.407 i_SIU/reg_led3:CLK (r) + 0.206 cell: ADLIB:DFN1P0 2.613 i_SIU/reg_led3:Q (r) + 1.288 net: LED_SIU_i_3_ 3.901 genblk5[3].leds_siu_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 4.114 genblk5[3].leds_siu_U1/U0/U1:DOUT (r) + 0.000 net: genblk5[3]_leds_siu_U1/U0/NET1 4.114 genblk5[3].leds_siu_U1/U0/U0:D (r) + 1.947 cell: ADLIB:IOPAD_TRI 6.061 genblk5[3].leds_siu_U1/U0/U0:PAD (r) + 0.000 net: LED_SIU_3_ 6.061 LED_SIU(3) (r) 6.061 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(3) (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_adc/cdiv_reg_q:Q SET Register to Register Path 1 From: i_adc/ds_tsens/reg_valid:CLK To: i_adc/ds_tsens/reg_start:D Delay (ns): 0.330 Slack (ns): 0.312 Arrival (ns): 1.741 Required (ns): 1.429 Hold (ns): 0.000 Path 2 From: i_adc/ds_tsens/ix30985z54530:CLK To: i_adc/ds_tsens/ix30985z21823:D Delay (ns): 0.357 Slack (ns): 0.336 Arrival (ns): 1.780 Required (ns): 1.444 Hold (ns): 0.000 Path 3 From: i_adc/ds_tsens/bsl/ts/ix29988z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix29988z21823:D Delay (ns): 0.357 Slack (ns): 0.337 Arrival (ns): 1.775 Required (ns): 1.438 Hold (ns): 0.000 Path 4 From: i_adc/ds_tsens/bsl/ts/ix30985z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix30985z21823:D Delay (ns): 0.357 Slack (ns): 0.338 Arrival (ns): 1.775 Required (ns): 1.437 Hold (ns): 0.000 Path 5 From: i_adc/ds_tsens/ix30739z54531:CLK To: i_adc/ds_tsens/ix30739z21824:D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 1.773 Required (ns): 1.434 Hold (ns): 0.000 Path 6 From: i_adc/ds_tsens/ix32979z54530:CLK To: i_adc/ds_tsens/ix32979z21823:D Delay (ns): 0.360 Slack (ns): 0.342 Arrival (ns): 1.772 Required (ns): 1.430 Hold (ns): 0.000 Path 7 From: i_adc/ds_tsens/bsl/reg_retbyte(3):CLK To: i_adc/ds_tsens/reg_read_reg(0)(3):D Delay (ns): 0.357 Slack (ns): 0.343 Arrival (ns): 1.765 Required (ns): 1.422 Hold (ns): 0.000 Path 8 From: i_adc/ds_tsens/bsl/ts/ix32979z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix32979z21823:D Delay (ns): 0.357 Slack (ns): 0.348 Arrival (ns): 1.776 Required (ns): 1.428 Hold (ns): 0.000 Path 9 From: i_adc/ds_tsens/bsl/ts/ix31982z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix31982z21823:D Delay (ns): 0.357 Slack (ns): 0.348 Arrival (ns): 1.779 Required (ns): 1.431 Hold (ns): 0.000 Path 10 From: i_adc/ds_tsens/bsl/reg_retbyte(0):CLK To: i_adc/ds_tsens/reg_read_reg(1)(0):D Delay (ns): 0.369 Slack (ns): 0.351 Arrival (ns): 1.781 Required (ns): 1.430 Hold (ns): 0.000 Expanded Path 1 From: i_adc/ds_tsens/reg_valid:CLK To: i_adc/ds_tsens/reg_start:D data arrival time 1.741 data required time - 1.429 slack 0.312 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.439 net: i_adc/clk1MHz_b 1.411 i_adc/ds_tsens/reg_valid:CLK (r) + 0.206 cell: ADLIB:DFN1C1 1.617 i_adc/ds_tsens/reg_valid:Q (r) + 0.124 net: i_adc/ds_tsens/valid 1.741 i_adc/ds_tsens/reg_start:D (r) 1.741 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.457 net: i_adc/clk1MHz_b 1.429 i_adc/ds_tsens/reg_start:CLK (r) + 0.000 Library hold time: ADLIB:DFN1 1.429 i_adc/ds_tsens/reg_start:D 1.429 data required time Expanded Path 2 From: i_adc/ds_tsens/ix30985z54530:CLK To: i_adc/ds_tsens/ix30985z21823:D data arrival time 1.780 data required time - 1.444 slack 0.336 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.451 net: i_adc/clk1MHz_b 1.423 i_adc/ds_tsens/ix30985z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.629 i_adc/ds_tsens/ix30985z54530:Q (r) + 0.151 net: i_adc/ds_tsens/rd_data1_3_ 1.780 i_adc/ds_tsens/ix30985z21823:D (r) 1.780 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.472 net: i_adc/clk1MHz_b 1.444 i_adc/ds_tsens/ix30985z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.444 i_adc/ds_tsens/ix30985z21823:D 1.444 data required time Expanded Path 3 From: i_adc/ds_tsens/bsl/ts/ix29988z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix29988z21823:D data arrival time 1.775 data required time - 1.438 slack 0.337 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.446 net: i_adc/clk1MHz_b 1.418 i_adc/ds_tsens/bsl/ts/ix29988z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.624 i_adc/ds_tsens/bsl/ts/ix29988z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_0_ 1.775 i_adc/ds_tsens/bsl/ts/ix29988z21823:D (r) 1.775 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.466 net: i_adc/clk1MHz_b 1.438 i_adc/ds_tsens/bsl/ts/ix29988z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.438 i_adc/ds_tsens/bsl/ts/ix29988z21823:D 1.438 data required time Expanded Path 4 From: i_adc/ds_tsens/bsl/ts/ix30985z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix30985z21823:D data arrival time 1.775 data required time - 1.437 slack 0.338 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.446 net: i_adc/clk1MHz_b 1.418 i_adc/ds_tsens/bsl/ts/ix30985z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.624 i_adc/ds_tsens/bsl/ts/ix30985z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_4_ 1.775 i_adc/ds_tsens/bsl/ts/ix30985z21823:D (r) 1.775 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.465 net: i_adc/clk1MHz_b 1.437 i_adc/ds_tsens/bsl/ts/ix30985z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.437 i_adc/ds_tsens/bsl/ts/ix30985z21823:D 1.437 data required time Expanded Path 5 From: i_adc/ds_tsens/ix30739z54531:CLK To: i_adc/ds_tsens/ix30739z21824:D data arrival time 1.773 data required time - 1.434 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.444 net: i_adc/clk1MHz_b 1.416 i_adc/ds_tsens/ix30739z54531:CLK (r) + 0.206 cell: ADLIB:DFN1 1.622 i_adc/ds_tsens/ix30739z54531:Q (r) + 0.151 net: i_adc/ds_tsens/rd_data1_2_ 1.773 i_adc/ds_tsens/ix30739z21824:D (r) 1.773 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.462 net: i_adc/clk1MHz_b 1.434 i_adc/ds_tsens/ix30739z21824:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.434 i_adc/ds_tsens/ix30739z21824:D 1.434 data required time Expanded Path 6 From: i_adc/ds_tsens/ix32979z54530:CLK To: i_adc/ds_tsens/ix32979z21823:D data arrival time 1.772 data required time - 1.430 slack 0.342 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.440 net: i_adc/clk1MHz_b 1.412 i_adc/ds_tsens/ix32979z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.618 i_adc/ds_tsens/ix32979z54530:Q (r) + 0.154 net: i_adc/ds_tsens/rd_data1_1_ 1.772 i_adc/ds_tsens/ix32979z21823:D (r) 1.772 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.458 net: i_adc/clk1MHz_b 1.430 i_adc/ds_tsens/ix32979z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.430 i_adc/ds_tsens/ix32979z21823:D 1.430 data required time Expanded Path 7 From: i_adc/ds_tsens/bsl/reg_retbyte(3):CLK To: i_adc/ds_tsens/reg_read_reg(0)(3):D data arrival time 1.765 data required time - 1.422 slack 0.343 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.436 net: i_adc/clk1MHz_b 1.408 i_adc/ds_tsens/bsl/reg_retbyte(3):CLK (r) + 0.206 cell: ADLIB:DFN1C1 1.614 i_adc/ds_tsens/bsl/reg_retbyte(3):Q (r) + 0.151 net: i_adc/ds_tsens/retbyte_3_ 1.765 i_adc/ds_tsens/reg_read_reg(0)(3):D (r) 1.765 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.450 net: i_adc/clk1MHz_b 1.422 i_adc/ds_tsens/reg_read_reg(0)(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.422 i_adc/ds_tsens/reg_read_reg(0)(3):D 1.422 data required time Expanded Path 8 From: i_adc/ds_tsens/bsl/ts/ix32979z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix32979z21823:D data arrival time 1.776 data required time - 1.428 slack 0.348 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.447 net: i_adc/clk1MHz_b 1.419 i_adc/ds_tsens/bsl/ts/ix32979z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.625 i_adc/ds_tsens/bsl/ts/ix32979z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_2_ 1.776 i_adc/ds_tsens/bsl/ts/ix32979z21823:D (r) 1.776 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.456 net: i_adc/clk1MHz_b 1.428 i_adc/ds_tsens/bsl/ts/ix32979z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.428 i_adc/ds_tsens/bsl/ts/ix32979z21823:D 1.428 data required time Expanded Path 9 From: i_adc/ds_tsens/bsl/ts/ix31982z54530:CLK To: i_adc/ds_tsens/bsl/ts/ix31982z21823:D data arrival time 1.779 data required time - 1.431 slack 0.348 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.450 net: i_adc/clk1MHz_b 1.422 i_adc/ds_tsens/bsl/ts/ix31982z54530:CLK (r) + 0.206 cell: ADLIB:DFN1 1.628 i_adc/ds_tsens/bsl/ts/ix31982z54530:Q (r) + 0.151 net: i_adc/ds_tsens/bsl/ts/rd_data1_3_ 1.779 i_adc/ds_tsens/bsl/ts/ix31982z21823:D (r) 1.779 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.459 net: i_adc/clk1MHz_b 1.431 i_adc/ds_tsens/bsl/ts/ix31982z21823:CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.431 i_adc/ds_tsens/bsl/ts/ix31982z21823:D 1.431 data required time Expanded Path 10 From: i_adc/ds_tsens/bsl/reg_retbyte(0):CLK To: i_adc/ds_tsens/reg_read_reg(1)(0):D data arrival time 1.781 data required time - 1.430 slack 0.351 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.440 net: i_adc/clk1MHz_b 1.412 i_adc/ds_tsens/bsl/reg_retbyte(0):CLK (r) + 0.206 cell: ADLIB:DFN1C1 1.618 i_adc/ds_tsens/bsl/reg_retbyte(0):Q (r) + 0.163 net: i_adc/ds_tsens/retbyte_0_ 1.781 i_adc/ds_tsens/reg_read_reg(1)(0):D (r) 1.781 data arrival time ________________________________________________________ Data required time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.458 net: i_adc/clk1MHz_b 1.430 i_adc/ds_tsens/reg_read_reg(1)(0):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 1.430 i_adc/ds_tsens/reg_read_reg(1)(0):D 1.430 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D Delay (ns): 1.894 Slack (ns): Arrival (ns): 1.894 Required (ns): Hold (ns): 0.000 External Hold (ns): -0.136 Expanded Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D data arrival time 1.894 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TSENS (f) + 0.000 net: TSENS 0.000 bbuf_TSENS/U0/U0:PAD (f) + 0.470 cell: ADLIB:IOPAD_BI 0.470 bbuf_TSENS/U0/U0:Y (f) + 0.000 net: bbuf_TSENS/U0/NET3 0.470 bbuf_TSENS/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOBI_IB_OB_EB 0.484 bbuf_TSENS/U0/U1:Y (f) + 1.077 net: TSENS_i 1.561 i_adc/ds_tsens/bsl/ts/ix5225z14896:B (f) + 0.215 cell: ADLIB:MX2 1.776 i_adc/ds_tsens/bsl/ts/ix5225z14896:Y (f) + 0.118 net: i_adc/ds_tsens/bsl/ts/nx5225z1 1.894 i_adc/ds_tsens/bsl/ts/reg_retbit:D (f) 1.894 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.539 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_retbit:CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_retbit:D END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS Delay (ns): 2.426 Slack (ns): Arrival (ns): 3.833 Required (ns): Clock to Out (ns): 3.833 Path 2 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS Delay (ns): 2.491 Slack (ns): Arrival (ns): 3.914 Required (ns): Clock to Out (ns): 3.914 Expanded Path 1 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS data arrival time 3.833 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.435 net: i_adc/clk1MHz_b 1.407 i_adc/ds_tsens/bsl/ts/reg_oe:CLK (r) + 0.256 cell: ADLIB:DFN1 1.663 i_adc/ds_tsens/bsl/ts/reg_oe:Q (f) + 0.612 net: i_adc/ds_tsens/bsl/oe_i 2.275 i_adc/ds_tsens/bsl/oe:B (f) + 0.226 cell: ADLIB:NAND2B 2.501 i_adc/ds_tsens/bsl/oe:Y (f) + 0.112 net: TSENS_e 2.613 bbuf_TSENS/U0/U1:E (f) + 0.145 cell: ADLIB:IOBI_IB_OB_EB 2.758 bbuf_TSENS/U0/U1:EOUT (f) + 0.000 net: bbuf_TSENS/U0/NET2 2.758 bbuf_TSENS/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 3.833 bbuf_TSENS/U0/U0:PAD (r) + 0.000 net: TSENS 3.833 TSENS (r) 3.833 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (r) Expanded Path 2 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS data arrival time 3.914 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 0.707 net: i_adc/clk1MHz 0.707 i_adc/cbuf_1MHz:A (r) + 0.265 cell: ADLIB:CLKINT 0.972 i_adc/cbuf_1MHz:Y (r) + 0.451 net: i_adc/clk1MHz_b 1.423 i_adc/ds_tsens/bsl/reg_hold_high:CLK (r) + 0.256 cell: ADLIB:DFN1C1 1.679 i_adc/ds_tsens/bsl/reg_hold_high:Q (f) + 0.727 net: TSENS_o 2.406 i_adc/ds_tsens/bsl/oe:A (f) + 0.176 cell: ADLIB:NAND2B 2.582 i_adc/ds_tsens/bsl/oe:Y (f) + 0.112 net: TSENS_e 2.694 bbuf_TSENS/U0/U1:E (f) + 0.145 cell: ADLIB:IOBI_IB_OB_EB 2.839 bbuf_TSENS/U0/U1:EOUT (f) + 0.000 net: bbuf_TSENS/U0/NET2 2.839 bbuf_TSENS/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 3.914 bbuf_TSENS/U0/U0:PAD (r) + 0.000 net: TSENS 3.914 TSENS (r) 3.914 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: i_adc/ds_tsens/bsl/reg_retbyte(3):CLR Delay (ns): 3.535 Slack (ns): Arrival (ns): 3.535 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.776 Path 2 From: RST_n To: i_adc/ds_tsens/bsl/reg_retbyte(4):CLR Delay (ns): 3.535 Slack (ns): Arrival (ns): 3.535 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.776 Path 3 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(3):CLR Delay (ns): 3.633 Slack (ns): Arrival (ns): 3.633 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.874 Path 4 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(4):CLR Delay (ns): 3.633 Slack (ns): Arrival (ns): 3.633 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.874 Path 5 From: RST_n To: i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR Delay (ns): 3.766 Slack (ns): Arrival (ns): 3.766 Required (ns): Removal (ns): 0.000 External Removal (ns): -1.994 Path 6 From: RST_n To: i_adc/ds_tsens/bsl/reg_valid:PRE Delay (ns): 3.774 Slack (ns): Arrival (ns): 3.774 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.005 Path 7 From: RST_n To: i_adc/ds_tsens/bsl/ts/ix58961z23817:CLR Delay (ns): 3.810 Slack (ns): Arrival (ns): 3.810 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.038 Path 8 From: RST_n To: i_adc/ds_tsens/bsl/ts/reg_retbit:CLR Delay (ns): 3.802 Slack (ns): Arrival (ns): 3.802 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.044 Path 9 From: RST_n To: i_adc/ds_tsens/reg_q(16):CLR Delay (ns): 3.823 Slack (ns): Arrival (ns): 3.823 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.050 Path 10 From: PUSHB To: i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR Delay (ns): 3.864 Slack (ns): Arrival (ns): 3.864 Required (ns): Removal (ns): 0.000 External Removal (ns): -2.092 Expanded Path 1 From: RST_n To: i_adc/ds_tsens/bsl/reg_retbyte(3):CLR data arrival time 3.535 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 0.963 net: not_rst_n 3.535 i_adc/ds_tsens/bsl/reg_retbyte(3):CLR (f) 3.535 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.540 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(3):CLR Expanded Path 2 From: RST_n To: i_adc/ds_tsens/bsl/reg_retbyte(4):CLR data arrival time 3.535 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 0.963 net: not_rst_n 3.535 i_adc/ds_tsens/bsl/reg_retbyte(4):CLR (f) 3.535 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.540 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(4):CLR Expanded Path 3 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(3):CLR data arrival time 3.633 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 0.963 net: not_rst_n 3.633 i_adc/ds_tsens/bsl/reg_retbyte(3):CLR (f) 3.633 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.540 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(3):CLR Expanded Path 4 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(4):CLR data arrival time 3.633 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 0.963 net: not_rst_n 3.633 i_adc/ds_tsens/bsl/reg_retbyte(4):CLR (f) 3.633 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.540 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(4):CLR Expanded Path 5 From: RST_n To: i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR data arrival time 3.766 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.194 net: not_rst_n 3.766 i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR (f) 3.766 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.553 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_counter(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR Expanded Path 6 From: RST_n To: i_adc/ds_tsens/bsl/reg_valid:PRE data arrival time 3.774 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.202 net: not_rst_n 3.774 i_adc/ds_tsens/bsl/reg_valid:PRE (f) 3.774 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.550 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_valid:CLK (r) + 0.000 Library removal time: ADLIB:DFN1P1 N/C i_adc/ds_tsens/bsl/reg_valid:PRE Expanded Path 7 From: RST_n To: i_adc/ds_tsens/bsl/ts/ix58961z23817:CLR data arrival time 3.810 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.238 net: not_rst_n 3.810 i_adc/ds_tsens/bsl/ts/ix58961z23817:CLR (f) 3.810 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.553 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/ix58961z23817:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/ix58961z23817:CLR Expanded Path 8 From: RST_n To: i_adc/ds_tsens/bsl/ts/reg_retbit:CLR data arrival time 3.802 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.230 net: not_rst_n 3.802 i_adc/ds_tsens/bsl/ts/reg_retbit:CLR (f) 3.802 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.539 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_retbit:CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_retbit:CLR Expanded Path 9 From: RST_n To: i_adc/ds_tsens/reg_q(16):CLR data arrival time 3.823 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.917 net: RST_n_i 2.431 i_adc/adc/ix4491z24338:A (r) + 0.141 cell: ADLIB:NAND2 2.572 i_adc/adc/ix4491z24338:Y (f) + 1.251 net: not_rst_n 3.823 i_adc/ds_tsens/reg_q(16):CLR (f) 3.823 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.554 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(16):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(16):CLR Expanded Path 10 From: PUSHB To: i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR data arrival time 3.864 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.990 net: PUSHB_i 2.465 i_adc/adc/ix4491z24338:B (r) + 0.205 cell: ADLIB:NAND2 2.670 i_adc/adc/ix4491z24338:Y (f) + 1.194 net: not_rst_n 3.864 i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR (f) 3.864 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 0.887 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.332 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.553 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_counter(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_counter(4):CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLA SET Register to Register Path 1 From: i_cbb/tim_ana/reg_signals_r(15):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD7 Delay (ns): 0.398 Slack (ns): 0.289 Arrival (ns): 4.472 Required (ns): 4.183 Hold (ns): 0.000 Path 2 From: i_cbb/tim_ana/reg_signals_r(14):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD6 Delay (ns): 0.398 Slack (ns): 0.289 Arrival (ns): 4.472 Required (ns): 4.183 Hold (ns): 0.000 Path 3 From: i_cbb/tim_ana/reg_signals_r(13):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD5 Delay (ns): 0.398 Slack (ns): 0.289 Arrival (ns): 4.472 Required (ns): 4.183 Hold (ns): 0.000 Path 4 From: i_cbb/tim_ana/reg_signals_r(12):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD4 Delay (ns): 0.398 Slack (ns): 0.289 Arrival (ns): 4.472 Required (ns): 4.183 Hold (ns): 0.000 Path 5 From: i_cbb/tim_ana/reg_signals_r(11):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD3 Delay (ns): 0.399 Slack (ns): 0.290 Arrival (ns): 4.473 Required (ns): 4.183 Hold (ns): 0.000 Path 6 From: i_cbb/tim_ana/reg_signals_r(6):CLK To: i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD6 Delay (ns): 0.398 Slack (ns): 0.296 Arrival (ns): 4.455 Required (ns): 4.159 Hold (ns): 0.000 Path 7 From: i_cbb/tim_ana/reg_signals_r(1):CLK To: i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD1 Delay (ns): 0.399 Slack (ns): 0.297 Arrival (ns): 4.456 Required (ns): 4.159 Hold (ns): 0.000 Path 8 From: i_cbb/cbbr_top_1/reg_din_syn(2):CLK To: i_cbb/cbbr_top_1/reg_din_del1(2):D Delay (ns): 0.330 Slack (ns): 0.301 Arrival (ns): 4.326 Required (ns): 4.025 Hold (ns): 0.000 Path 9 From: i_cbb/sys_config0/reg_scsn_din(28):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(28):D Delay (ns): 0.334 Slack (ns): 0.302 Arrival (ns): 4.361 Required (ns): 4.059 Hold (ns): 0.000 Path 10 From: i_cbb/cbbr_top_1/reg_din_synf(2):CLK To: i_cbb/cbbr_top_1/reg_din_delf1(2):D Delay (ns): 0.330 Slack (ns): 0.303 Arrival (ns): 4.356 Required (ns): 4.053 Hold (ns): 0.000 Expanded Path 1 From: i_cbb/tim_ana/reg_signals_r(15):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD7 data arrival time 4.472 data required time - 4.183 slack 0.289 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.521 net: CLK40out 4.074 i_cbb/tim_ana/reg_signals_r(15):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.280 i_cbb/tim_ana/reg_signals_r(15):Q (r) + 0.192 net: i_cbb/tim_ana/signals_r_15_ 4.472 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD7 (r) 4.472 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.630 net: CLK40out 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD7 4.183 data required time Expanded Path 2 From: i_cbb/tim_ana/reg_signals_r(14):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD6 data arrival time 4.472 data required time - 4.183 slack 0.289 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.521 net: CLK40out 4.074 i_cbb/tim_ana/reg_signals_r(14):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.280 i_cbb/tim_ana/reg_signals_r(14):Q (r) + 0.192 net: i_cbb/tim_ana/signals_r_14_ 4.472 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD6 (r) 4.472 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.630 net: CLK40out 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD6 4.183 data required time Expanded Path 3 From: i_cbb/tim_ana/reg_signals_r(13):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD5 data arrival time 4.472 data required time - 4.183 slack 0.289 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.521 net: CLK40out 4.074 i_cbb/tim_ana/reg_signals_r(13):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.280 i_cbb/tim_ana/reg_signals_r(13):Q (r) + 0.192 net: i_cbb/tim_ana/signals_r_13_ 4.472 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD5 (r) 4.472 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.630 net: CLK40out 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD5 4.183 data required time Expanded Path 4 From: i_cbb/tim_ana/reg_signals_r(12):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD4 data arrival time 4.472 data required time - 4.183 slack 0.289 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.521 net: CLK40out 4.074 i_cbb/tim_ana/reg_signals_r(12):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.280 i_cbb/tim_ana/reg_signals_r(12):Q (r) + 0.192 net: i_cbb/tim_ana/signals_r_12_ 4.472 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD4 (r) 4.472 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.630 net: CLK40out 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD4 4.183 data required time Expanded Path 5 From: i_cbb/tim_ana/reg_signals_r(11):CLK To: i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD3 data arrival time 4.473 data required time - 4.183 slack 0.290 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.521 net: CLK40out 4.074 i_cbb/tim_ana/reg_signals_r(11):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.280 i_cbb/tim_ana/reg_signals_r(11):Q (r) + 0.193 net: i_cbb/tim_ana/signals_r_11_ 4.473 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD3 (r) 4.473 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.630 net: CLK40out 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.183 i_cbb/tim_ana/bram_inst_sram_i_1_dpram_ram:WD3 4.183 data required time Expanded Path 6 From: i_cbb/tim_ana/reg_signals_r(6):CLK To: i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD6 data arrival time 4.455 data required time - 4.159 slack 0.296 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.504 net: CLK40out 4.057 i_cbb/tim_ana/reg_signals_r(6):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.263 i_cbb/tim_ana/reg_signals_r(6):Q (r) + 0.192 net: i_cbb/tim_ana/signals_r_6_ 4.455 i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD6 (r) 4.455 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.606 net: CLK40out 4.159 i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.159 i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD6 4.159 data required time Expanded Path 7 From: i_cbb/tim_ana/reg_signals_r(1):CLK To: i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD1 data arrival time 4.456 data required time - 4.159 slack 0.297 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.504 net: CLK40out 4.057 i_cbb/tim_ana/reg_signals_r(1):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.263 i_cbb/tim_ana/reg_signals_r(1):Q (r) + 0.193 net: i_cbb/tim_ana/signals_r_1_ 4.456 i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD1 (r) 4.456 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.606 net: CLK40out 4.159 i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WCLK (r) + 0.000 Library hold time: ADLIB:RAM512X18 4.159 i_cbb/tim_ana/bram_inst_sram_i_0_dpram_ram:WD1 4.159 data required time Expanded Path 8 From: i_cbb/cbbr_top_1/reg_din_syn(2):CLK To: i_cbb/cbbr_top_1/reg_din_del1(2):D data arrival time 4.326 data required time - 4.025 slack 0.301 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.443 net: CLK40out 3.996 i_cbb/cbbr_top_1/reg_din_syn(2):CLK (r) + 0.206 cell: ADLIB:DFN1P1 4.202 i_cbb/cbbr_top_1/reg_din_syn(2):Q (r) + 0.124 net: i_cbb/cbbr_top_1/din_syn_2_ 4.326 i_cbb/cbbr_top_1/reg_din_del1(2):D (r) 4.326 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.472 net: CLK40out 4.025 i_cbb/cbbr_top_1/reg_din_del1(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 4.025 i_cbb/cbbr_top_1/reg_din_del1(2):D 4.025 data required time Expanded Path 9 From: i_cbb/sys_config0/reg_scsn_din(28):CLK To: i_cbb/scsn_inst_nw_apl/reg_read_data(28):D data arrival time 4.361 data required time - 4.059 slack 0.302 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.474 net: CLK40out 4.027 i_cbb/sys_config0/reg_scsn_din(28):CLK (r) + 0.206 cell: ADLIB:DFN1E1 4.233 i_cbb/sys_config0/reg_scsn_din(28):Q (r) + 0.128 net: i_cbb/scsn_bus_din_28_ 4.361 i_cbb/scsn_inst_nw_apl/reg_read_data(28):D (r) 4.361 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.506 net: CLK40out 4.059 i_cbb/scsn_inst_nw_apl/reg_read_data(28):CLK (r) + 0.000 Library hold time: ADLIB:DFN1E1 4.059 i_cbb/scsn_inst_nw_apl/reg_read_data(28):D 4.059 data required time Expanded Path 10 From: i_cbb/cbbr_top_1/reg_din_synf(2):CLK To: i_cbb/cbbr_top_1/reg_din_delf1(2):D data arrival time 4.356 data required time - 4.053 slack 0.303 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.473 net: CLK40out 4.026 i_cbb/cbbr_top_1/reg_din_synf(2):CLK (r) + 0.206 cell: ADLIB:DFN1P1 4.232 i_cbb/cbbr_top_1/reg_din_synf(2):Q (r) + 0.124 net: i_cbb/cbbr_top_1/din_synf_2_ 4.356 i_cbb/cbbr_top_1/reg_din_delf1(2):D (r) 4.356 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.500 net: CLK40out 4.053 i_cbb/cbbr_top_1/reg_din_delf1(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1P1 4.053 i_cbb/cbbr_top_1/reg_din_delf1(2):D 4.053 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: TLMU_n(4) To: tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.458 Slack (ns): Arrival (ns): 1.458 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.756 Path 2 From: TLMU_p(4) To: tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.470 Slack (ns): Arrival (ns): 1.470 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.744 Path 3 From: TLMU_n(3) To: tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.458 Slack (ns): Arrival (ns): 1.458 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.697 Path 4 From: TLMU_n(6) To: tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.458 Slack (ns): Arrival (ns): 1.458 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.695 Path 5 From: TLMU_n(5) To: tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.458 Slack (ns): Arrival (ns): 1.458 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.695 Path 6 From: TLMU_n(7) To: tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.458 Slack (ns): Arrival (ns): 1.458 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.695 Path 7 From: TLMU_p(3) To: tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.470 Slack (ns): Arrival (ns): 1.470 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.685 Path 8 From: TLMU_p(6) To: tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.470 Slack (ns): Arrival (ns): 1.470 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.683 Path 9 From: TLMU_p(5) To: tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.470 Slack (ns): Arrival (ns): 1.470 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.683 Path 10 From: TLMU_p(7) To: tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN Delay (ns): 1.470 Slack (ns): Arrival (ns): 1.470 Required (ns): Hold (ns): 0.000 External Hold (ns): 2.683 Expanded Path 1 From: TLMU_n(4) To: tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.458 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(4) (f) + 0.000 net: TLMU_n_4_ 0.000 tlmu_in[4].lvds_TLMUddr_ib/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[4].lvds_TLMUddr_ib/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[4]_lvds_TLMUddr_ib/U0/U2_N2P 0.000 tlmu_in[4].lvds_TLMUddr_ib/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[4].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[4]_lvds_TLMUddr_ib/U0/NET1 1.458 tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.458 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.661 net: CLK40out N/C tlmu_in[4].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 2 From: TLMU_p(4) To: tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.470 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(4) (f) + 0.000 net: TLMU_p_4_ 0.000 tlmu_in[4].lvds_TLMUddr_ib/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[4].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[4]_lvds_TLMUddr_ib/U0/NET1 1.470 tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.470 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.661 net: CLK40out N/C tlmu_in[4].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[4].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 3 From: TLMU_n(3) To: tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.458 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(3) (f) + 0.000 net: TLMU_n_3_ 0.000 tlmu_in[3].lvds_TLMUddr_ib/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[3].lvds_TLMUddr_ib/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[3]_lvds_TLMUddr_ib/U0/U2_N2P 0.000 tlmu_in[3].lvds_TLMUddr_ib/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[3].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[3]_lvds_TLMUddr_ib/U0/NET1 1.458 tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.458 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.602 net: CLK40out N/C tlmu_in[3].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 4 From: TLMU_n(6) To: tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.458 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(6) (f) + 0.000 net: TLMU_n_6_ 0.000 tlmu_in[6].lvds_TLMUddr_ib/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[6].lvds_TLMUddr_ib/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[6]_lvds_TLMUddr_ib/U0/U2_N2P 0.000 tlmu_in[6].lvds_TLMUddr_ib/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[6].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[6]_lvds_TLMUddr_ib/U0/NET1 1.458 tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.458 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.600 net: CLK40out N/C tlmu_in[6].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 5 From: TLMU_n(5) To: tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.458 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(5) (f) + 0.000 net: TLMU_n_5_ 0.000 tlmu_in[5].lvds_TLMUddr_ib/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[5].lvds_TLMUddr_ib/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[5]_lvds_TLMUddr_ib/U0/U2_N2P 0.000 tlmu_in[5].lvds_TLMUddr_ib/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[5].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[5]_lvds_TLMUddr_ib/U0/NET1 1.458 tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.458 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.600 net: CLK40out N/C tlmu_in[5].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 6 From: TLMU_n(7) To: tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.458 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(7) (f) + 0.000 net: TLMU_n_7_ 0.000 tlmu_in[7].lvds_TLMUddr_ib/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[7].lvds_TLMUddr_ib/U0/U2:N2POUT (f) + 0.000 net: tlmu_in[7]_lvds_TLMUddr_ib/U0/U2_N2P 0.000 tlmu_in[7].lvds_TLMUddr_ib/U0/U0:N2PIN (f) + 1.458 cell: ADLIB:IOPADP_IN 1.458 tlmu_in[7].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[7]_lvds_TLMUddr_ib/U0/NET1 1.458 tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.458 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.600 net: CLK40out N/C tlmu_in[7].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 7 From: TLMU_p(3) To: tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.470 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(3) (f) + 0.000 net: TLMU_p_3_ 0.000 tlmu_in[3].lvds_TLMUddr_ib/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[3].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[3]_lvds_TLMUddr_ib/U0/NET1 1.470 tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.470 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.602 net: CLK40out N/C tlmu_in[3].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[3].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 8 From: TLMU_p(6) To: tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.470 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(6) (f) + 0.000 net: TLMU_p_6_ 0.000 tlmu_in[6].lvds_TLMUddr_ib/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[6].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[6]_lvds_TLMUddr_ib/U0/NET1 1.470 tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.470 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.600 net: CLK40out N/C tlmu_in[6].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[6].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 9 From: TLMU_p(5) To: tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.470 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(5) (f) + 0.000 net: TLMU_p_5_ 0.000 tlmu_in[5].lvds_TLMUddr_ib/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[5].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[5]_lvds_TLMUddr_ib/U0/NET1 1.470 tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.470 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.600 net: CLK40out N/C tlmu_in[5].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[5].lvds_TLMUddr_ib/U0/U1:YIN Expanded Path 10 From: TLMU_p(7) To: tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN data arrival time 1.470 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(7) (f) + 0.000 net: TLMU_p_7_ 0.000 tlmu_in[7].lvds_TLMUddr_ib/U0/U0:PAD (f) + 1.470 cell: ADLIB:IOPADP_IN 1.470 tlmu_in[7].lvds_TLMUddr_ib/U0/U0:Y (f) + 0.000 net: tlmu_in[7]_lvds_TLMUddr_ib/U0/NET1 1.470 tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN (f) 1.470 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.600 net: CLK40out N/C tlmu_in[7].lvds_TLMUddr_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C tlmu_in[7].lvds_TLMUddr_ib/U0/U1:YIN END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: oddr_PIMLINK_0_ob/U0/U1:OCLK To: PIMLINK(0) Delay (ns): 1.229 Slack (ns): Arrival (ns): 5.218 Required (ns): Clock to Out (ns): 5.218 Path 2 From: i_adc/adc/adci/reg_spi_clk_i:CLK To: ADC_SCLK Delay (ns): 2.468 Slack (ns): Arrival (ns): 6.453 Required (ns): Clock to Out (ns): 6.453 Path 3 From: i_adc/adc/adci/reg_spi_cnv_i:CLK To: ADC_CSn Delay (ns): 2.502 Slack (ns): Arrival (ns): 6.497 Required (ns): Clock to Out (ns): 6.497 Path 4 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_p Delay (ns): 2.617 Slack (ns): Arrival (ns): 6.630 Required (ns): Clock to Out (ns): 6.630 Path 5 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_n Delay (ns): 2.629 Slack (ns): Arrival (ns): 6.642 Required (ns): Clock to Out (ns): 6.642 Path 6 From: i_cbb/ttcex_out_inst_reg_b_channel_out:CLK To: B_ECL Delay (ns): 2.799 Slack (ns): Arrival (ns): 6.787 Required (ns): Clock to Out (ns): 6.787 Path 7 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTp Delay (ns): 3.048 Slack (ns): Arrival (ns): 7.049 Required (ns): Clock to Out (ns): 7.049 Path 8 From: i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK To: SCSNOUTp Delay (ns): 3.048 Slack (ns): Arrival (ns): 7.049 Required (ns): Clock to Out (ns): 7.049 Path 9 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA Delay (ns): 3.037 Slack (ns): Arrival (ns): 7.051 Required (ns): Clock to Out (ns): 7.051 Path 10 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTn Delay (ns): 3.060 Slack (ns): Arrival (ns): 7.061 Required (ns): Clock to Out (ns): 7.061 Expanded Path 1 From: oddr_PIMLINK_0_ob/U0/U1:OCLK To: PIMLINK(0) data arrival time 5.218 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.436 net: CLK40out 3.989 oddr_PIMLINK_0_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 4.303 oddr_PIMLINK_0_ob/U0/U1:DOUT (r) + 0.000 net: oddr_PIMLINK_0_ob/U0/NET1 4.303 oddr_PIMLINK_0_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 5.218 oddr_PIMLINK_0_ob/U0/U0:PAD (r) + 0.000 net: PIMLINK_0_ 5.218 PIMLINK(0) (r) 5.218 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C PIMLINK(0) (r) Expanded Path 2 From: i_adc/adc/adci/reg_spi_clk_i:CLK To: ADC_SCLK data arrival time 6.453 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.432 net: CLK40out 3.985 i_adc/adc/adci/reg_spi_clk_i:CLK (r) + 0.206 cell: ADLIB:DFN1 4.191 i_adc/adc/adci/reg_spi_clk_i:Q (r) + 0.448 net: ADC_SCLK_i 4.639 obuf_ADC_SCLK_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 4.852 obuf_ADC_SCLK_U1/U0/U1:DOUT (r) + 0.000 net: obuf_ADC_SCLK_U1/U0/NET1 4.852 obuf_ADC_SCLK_U1/U0/U0:D (r) + 1.601 cell: ADLIB:IOPAD_TRI 6.453 obuf_ADC_SCLK_U1/U0/U0:PAD (r) + 0.000 net: ADC_SCLK 6.453 ADC_SCLK (r) 6.453 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C ADC_SCLK (r) Expanded Path 3 From: i_adc/adc/adci/reg_spi_cnv_i:CLK To: ADC_CSn data arrival time 6.497 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.442 net: CLK40out 3.995 i_adc/adc/adci/reg_spi_cnv_i:CLK (r) + 0.206 cell: ADLIB:DFN1 4.201 i_adc/adc/adci/reg_spi_cnv_i:Q (r) + 0.136 net: ADC_CSn_i 4.337 obuf_ADC_CSn_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 4.550 obuf_ADC_CSn_U1/U0/U1:DOUT (r) + 0.000 net: obuf_ADC_CSn_U1/U0/NET1 4.550 obuf_ADC_CSn_U1/U0/U0:D (r) + 1.947 cell: ADLIB:IOPAD_TRI 6.497 obuf_ADC_CSn_U1/U0/U0:PAD (r) + 0.000 net: ADC_CSn 6.497 ADC_CSn (r) 6.497 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C ADC_CSn (r) Expanded Path 4 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_p data arrival time 6.630 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.460 net: CLK40out 4.013 i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK (r) + 0.256 cell: ADLIB:DFN1E1 4.269 i_cbb/sys_config0/reg_cbb_ctrl_i(0):Q (f) + 1.539 net: CNRRL_i 5.808 lvds_SPB_iob/U0/U1:D (f) + 0.203 cell: ADLIB:IOTRI_OB_EB 6.011 lvds_SPB_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPB_iob/U0/NET1 6.011 lvds_SPB_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 6.630 lvds_SPB_iob/U0/U0:PAD (f) + 0.000 net: SPB_p 6.630 SPB_p (f) 6.630 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C SPB_p (f) Expanded Path 5 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: SPB_n data arrival time 6.642 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.460 net: CLK40out 4.013 i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK (r) + 0.256 cell: ADLIB:DFN1E1 4.269 i_cbb/sys_config0/reg_cbb_ctrl_i(0):Q (f) + 1.539 net: CNRRL_i 5.808 lvds_SPB_iob/U0/U1:D (f) + 0.203 cell: ADLIB:IOTRI_OB_EB 6.011 lvds_SPB_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPB_iob/U0/NET1 6.011 lvds_SPB_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 6.642 lvds_SPB_iob/U0/U2:PAD (r) + 0.000 net: SPB_n 6.642 SPB_n (r) 6.642 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C SPB_n (r) Expanded Path 6 From: i_cbb/ttcex_out_inst_reg_b_channel_out:CLK To: B_ECL data arrival time 6.787 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.435 net: CLK40out 3.988 i_cbb/ttcex_out_inst_reg_b_channel_out:CLK (r) + 0.206 cell: ADLIB:DFN1 4.194 i_cbb/ttcex_out_inst_reg_b_channel_out:Q (r) + 1.465 net: B_ECL_i 5.659 obuf_B_ECL_U1/U0/U1:D (r) + 0.213 cell: ADLIB:IOTRI_OB_EB 5.872 obuf_B_ECL_U1/U0/U1:DOUT (r) + 0.000 net: obuf_B_ECL_U1/U0/NET1 5.872 obuf_B_ECL_U1/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 6.787 obuf_B_ECL_U1/U0/U0:PAD (r) + 0.000 net: B_ECL 6.787 B_ECL (r) 6.787 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C B_ECL (r) Expanded Path 7 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTp data arrival time 7.049 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.448 net: CLK40out 4.001 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.257 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d0_out 4.375 i_adc/SCSNOUT:A (f) + 0.215 cell: ADLIB:MX2 4.590 i_adc/SCSNOUT:Y (f) + 1.611 net: SCSNOUT2_i 6.201 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 6.430 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 6.430 lvds_SCSNOUT_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 7.049 lvds_SCSNOUT_iob/U0/U0:PAD (f) + 0.000 net: SCSNOUTp 7.049 SCSNOUTp (f) 7.049 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C SCSNOUTp (f) Expanded Path 8 From: i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK To: SCSNOUTp data arrival time 7.049 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.448 net: CLK40out 4.001 i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.257 i_adc/scsn_slv_nw_dll_st1/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d1_out 4.375 i_adc/SCSNOUT:B (f) + 0.215 cell: ADLIB:MX2 4.590 i_adc/SCSNOUT:Y (f) + 1.611 net: SCSNOUT2_i 6.201 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 6.430 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 6.430 lvds_SCSNOUT_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 7.049 lvds_SCSNOUT_iob/U0/U0:PAD (f) + 0.000 net: SCSNOUTp 7.049 SCSNOUTp (f) 7.049 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C SCSNOUTp (f) Expanded Path 9 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA data arrival time 7.051 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.461 net: CLK40out 4.014 i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK (r) + 0.256 cell: ADLIB:DFN1C1 4.270 i_adc/sfp_rd_reg_SFP_SDA_e_i:Q (f) + 1.538 net: SIU_SDA_e 5.808 bbuf_SIU_SDA/U0/U1:E (f) + 0.168 cell: ADLIB:IOBI_IB_OB_EB 5.976 bbuf_SIU_SDA/U0/U1:EOUT (f) + 0.000 net: bbuf_SIU_SDA/U0/NET2 5.976 bbuf_SIU_SDA/U0/U0:E (f) + 1.075 cell: ADLIB:IOPAD_BI 7.051 bbuf_SIU_SDA/U0/U0:PAD (r) + 0.000 net: SIU_SDA 7.051 SIU_SDA (r) 7.051 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C SIU_SDA (r) Expanded Path 10 From: i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK To: SCSNOUTn data arrival time 7.061 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.448 net: CLK40out 4.001 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:CLK (r) + 0.256 cell: ADLIB:DFN1 4.257 i_adc/scsn_slv_nw_dll_st0/reg_data_out_to_pl:Q (f) + 0.118 net: i_adc/scsn_slv_nw_dll_d0_out 4.375 i_adc/SCSNOUT:A (f) + 0.215 cell: ADLIB:MX2 4.590 i_adc/SCSNOUT:Y (f) + 1.611 net: SCSNOUT2_i 6.201 lvds_SCSNOUT_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 6.430 lvds_SCSNOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 6.430 lvds_SCSNOUT_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 7.061 lvds_SCSNOUT_iob/U0/U2:PAD (r) + 0.000 net: SCSNOUTn 7.061 SCSNOUTn (r) 7.061 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C N/C SCSNOUTn (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ib0/reg_b_crc(12):CLR Delay (ns): 0.505 Slack (ns): 0.470 Arrival (ns): 4.512 Required (ns): 4.042 Removal (ns): 0.000 Skew (ns): -0.035 Path 2 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/trg_emu/reg_q(1):PRE Delay (ns): 0.505 Slack (ns): 0.470 Arrival (ns): 4.512 Required (ns): 4.042 Removal (ns): 0.000 Skew (ns): -0.035 Path 3 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(3):CLR Delay (ns): 0.496 Slack (ns): 0.474 Arrival (ns): 4.503 Required (ns): 4.029 Removal (ns): 0.000 Skew (ns): -0.022 Path 4 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/trg_gen/reg_q(0):CLR Delay (ns): 0.496 Slack (ns): 0.477 Arrival (ns): 4.503 Required (ns): 4.026 Removal (ns): 0.000 Skew (ns): -0.019 Path 5 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR Delay (ns): 0.631 Slack (ns): 0.608 Arrival (ns): 4.622 Required (ns): 4.014 Removal (ns): 0.000 Skew (ns): -0.023 Path 6 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR Delay (ns): 0.640 Slack (ns): 0.610 Arrival (ns): 4.632 Required (ns): 4.022 Removal (ns): 0.000 Skew (ns): -0.030 Path 7 From: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR Delay (ns): 0.645 Slack (ns): 0.619 Arrival (ns): 4.643 Required (ns): 4.024 Removal (ns): 0.000 Skew (ns): -0.026 Path 8 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ib0/modgen_counter_bitcounter_reg_q(4):CLR Delay (ns): 0.627 Slack (ns): 0.619 Arrival (ns): 4.634 Required (ns): 4.015 Removal (ns): 0.000 Skew (ns): -0.008 Path 9 From: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR Delay (ns): 0.640 Slack (ns): 0.620 Arrival (ns): 4.638 Required (ns): 4.018 Removal (ns): 0.000 Skew (ns): -0.020 Path 10 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR Delay (ns): 0.631 Slack (ns): 0.620 Arrival (ns): 4.642 Required (ns): 4.022 Removal (ns): 0.000 Skew (ns): -0.011 Expanded Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ib0/reg_b_crc(12):CLR data arrival time 4.512 data required time - 4.042 slack 0.470 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK40out 4.007 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.256 cell: ADLIB:DFN1P1 4.263 i_cbb/clock_generation_reg_rst_master:Q (f) + 0.249 net: i_cbb/rst_scsn 4.512 i_cbb/scsn_inst_nw_dll_ib0/reg_b_crc(12):CLR (f) 4.512 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.489 net: CLK40out 4.042 i_cbb/scsn_inst_nw_dll_ib0/reg_b_crc(12):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.042 i_cbb/scsn_inst_nw_dll_ib0/reg_b_crc(12):CLR 4.042 data required time Expanded Path 2 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/trg_emu/reg_q(1):PRE data arrival time 4.512 data required time - 4.042 slack 0.470 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK40out 4.007 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.256 cell: ADLIB:DFN1P1 4.263 i_cbb/clock_generation_reg_rst_master:Q (f) + 0.249 net: i_cbb/rst_scsn 4.512 i_cbb/trg_emu/reg_q(1):PRE (f) 4.512 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.489 net: CLK40out 4.042 i_cbb/trg_emu/reg_q(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1P1 4.042 i_cbb/trg_emu/reg_q(1):PRE 4.042 data required time Expanded Path 3 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(3):CLR data arrival time 4.503 data required time - 4.029 slack 0.474 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK40out 4.007 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.256 cell: ADLIB:DFN1P1 4.263 i_cbb/clock_generation_reg_rst_master:Q (f) + 0.240 net: i_cbb/rst_scsn 4.503 i_cbb/sys_config0/reg_syscfg_wdata_r(3):CLR (f) 4.503 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.476 net: CLK40out 4.029 i_cbb/sys_config0/reg_syscfg_wdata_r(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.029 i_cbb/sys_config0/reg_syscfg_wdata_r(3):CLR 4.029 data required time Expanded Path 4 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/trg_gen/reg_q(0):CLR data arrival time 4.503 data required time - 4.026 slack 0.477 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK40out 4.007 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.256 cell: ADLIB:DFN1P1 4.263 i_cbb/clock_generation_reg_rst_master:Q (f) + 0.240 net: i_cbb/rst_scsn 4.503 i_cbb/trg_gen/reg_q(0):CLR (f) 4.503 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.473 net: CLK40out 4.026 i_cbb/trg_gen/reg_q(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.026 i_cbb/trg_gen/reg_q(0):CLR 4.026 data required time Expanded Path 5 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR data arrival time 4.622 data required time - 4.014 slack 0.608 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.438 net: CLK40out 3.991 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.197 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_rst_n:Q (r) + 0.122 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_rst_n 4.319 i_cbb/scsn_inst_nw_nwl/sl1/ix63501z49933:B (r) + 0.187 cell: ADLIB:NAND2A 4.506 i_cbb/scsn_inst_nw_nwl/sl1/ix63501z49933:Y (f) + 0.116 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_not_rst_n_i 4.622 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR (f) 4.622 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.461 net: CLK40out 4.014 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.014 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR 4.014 data required time Expanded Path 6 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR data arrival time 4.632 data required time - 4.022 slack 0.610 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.439 net: CLK40out 3.992 i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.198 i_adc/scsn_slv_nw_nwl/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_nwl/h1_hm_rst_n 4.317 i_adc/scsn_slv_nw_nwl/ix956z24342:A (r) + 0.183 cell: ADLIB:NAND3 4.500 i_adc/scsn_slv_nw_nwl/ix956z24342:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/h1_not_rst_n_i 4.632 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR (f) 4.632 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.469 net: CLK40out 4.022 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.022 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR 4.022 data required time Expanded Path 7 From: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR data arrival time 4.643 data required time - 4.024 slack 0.619 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.445 net: CLK40out 3.998 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.204 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_dll_bt1/h1_hm_rst_n 4.323 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:A (r) + 0.183 cell: ADLIB:NAND3 4.506 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:Y (f) + 0.137 net: i_adc/scsn_slv_nw_dll_bt1/h1_not_rst_n_i 4.643 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR (f) 4.643 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.471 net: CLK40out 4.024 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.024 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR 4.024 data required time Expanded Path 8 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ib0/modgen_counter_bitcounter_reg_q(4):CLR data arrival time 4.634 data required time - 4.015 slack 0.619 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK40out 4.007 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.256 cell: ADLIB:DFN1P1 4.263 i_cbb/clock_generation_reg_rst_master:Q (f) + 0.371 net: i_cbb/rst_scsn 4.634 i_cbb/scsn_inst_nw_dll_ib0/modgen_counter_bitcounter_reg_q(4):CLR (f) 4.634 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.462 net: CLK40out 4.015 i_cbb/scsn_inst_nw_dll_ib0/modgen_counter_bitcounter_reg_q(4):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.015 i_cbb/scsn_inst_nw_dll_ib0/modgen_counter_bitcounter_reg_q(4):CLR 4.015 data required time Expanded Path 9 From: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR data arrival time 4.638 data required time - 4.018 slack 0.620 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.445 net: CLK40out 3.998 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.204 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_rst_n:Q (r) + 0.119 net: i_adc/scsn_slv_nw_dll_bt1/h1_hm_rst_n 4.323 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:A (r) + 0.183 cell: ADLIB:NAND3 4.506 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:Y (f) + 0.132 net: i_adc/scsn_slv_nw_dll_bt1/h1_not_rst_n_i 4.638 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR (f) 4.638 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.465 net: CLK40out 4.018 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.018 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR 4.018 data required time Expanded Path 10 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR data arrival time 4.642 data required time - 4.022 slack 0.620 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.458 net: CLK40out 4.011 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.217 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_rst_n:Q (r) + 0.124 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_rst_n 4.341 i_adc/scsn_slv_nw_nwl/sl1/ix63501z24337:A (r) + 0.183 cell: ADLIB:NAND3 4.524 i_adc/scsn_slv_nw_nwl/sl1/ix63501z24337:Y (f) + 0.118 net: i_adc/scsn_slv_nw_nwl/sl1/h1_not_rst_n_i 4.642 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR (f) 4.642 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation 3.553 + 0.469 net: CLK40out 4.022 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 4.022 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(0):CLR 4.022 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Removal Path 1 From: RST_n To: i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(5):CLR Delay (ns): 2.495 Slack (ns): Arrival (ns): 2.495 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.609 Path 2 From: RST_n To: i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(3):CLR Delay (ns): 2.495 Slack (ns): Arrival (ns): 2.495 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.609 Path 3 From: RST_n To: i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(6):CLR Delay (ns): 2.495 Slack (ns): Arrival (ns): 2.495 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.609 Path 4 From: PUSHB To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR Delay (ns): 2.541 Slack (ns): Arrival (ns): 2.541 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.567 Path 5 From: PUSHB To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR Delay (ns): 2.541 Slack (ns): Arrival (ns): 2.541 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.556 Path 6 From: PUSHB To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR Delay (ns): 2.636 Slack (ns): Arrival (ns): 2.636 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.474 Path 7 From: PUSHB To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR Delay (ns): 2.631 Slack (ns): Arrival (ns): 2.631 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.473 Path 8 From: PUSHB To: i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(7):CLR Delay (ns): 2.633 Slack (ns): Arrival (ns): 2.633 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.466 Path 9 From: PUSHB To: i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(0):CLR Delay (ns): 2.633 Slack (ns): Arrival (ns): 2.633 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.466 Path 10 From: PUSHB To: i_adc/scsn_slv_nw_apl/h1_reg_hm_state_out(7):CLR Delay (ns): 2.707 Slack (ns): Arrival (ns): 2.707 Required (ns): Removal (ns): 0.000 External Removal (ns): 1.417 Expanded Path 1 From: RST_n To: i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(5):CLR data arrival time 2.495 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.578 net: RST_n_i 2.092 i_adc/scsn_slv_nw_dll_st1/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.341 i_adc/scsn_slv_nw_dll_st1/ix956z24337:Y (f) + 0.154 net: i_adc/scsn_slv_nw_dll_st1/h1_not_rst_n_i 2.495 i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(5):CLR (f) 2.495 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.551 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(5):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(5):CLR Expanded Path 2 From: RST_n To: i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(3):CLR data arrival time 2.495 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.578 net: RST_n_i 2.092 i_adc/scsn_slv_nw_dll_st1/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.341 i_adc/scsn_slv_nw_dll_st1/ix956z24337:Y (f) + 0.154 net: i_adc/scsn_slv_nw_dll_st1/h1_not_rst_n_i 2.495 i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(3):CLR (f) 2.495 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.551 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(3):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(3):CLR Expanded Path 3 From: RST_n To: i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(6):CLR data arrival time 2.495 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 0.499 cell: ADLIB:IOPAD_IN 0.499 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 0.499 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.514 ibuf_RST_n_ib/U0/U1:Y (r) + 1.578 net: RST_n_i 2.092 i_adc/scsn_slv_nw_dll_st1/ix956z24337:B (r) + 0.249 cell: ADLIB:NAND3 2.341 i_adc/scsn_slv_nw_dll_st1/ix956z24337:Y (f) + 0.154 net: i_adc/scsn_slv_nw_dll_st1/h1_not_rst_n_i 2.495 i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(6):CLR (f) 2.495 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.551 net: CLK40out N/C i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_st1/h1_reg_hm_state_out(6):CLR Expanded Path 4 From: PUSHB To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR data arrival time 2.541 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.673 net: PUSHB_i 2.148 i_adc/scsn_slv_nw_nwl/ix956z24342:C (r) + 0.261 cell: ADLIB:NAND3 2.409 i_adc/scsn_slv_nw_nwl/ix956z24342:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/h1_not_rst_n_i 2.541 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR (f) 2.541 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.555 net: CLK40out N/C i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLR Expanded Path 5 From: PUSHB To: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR data arrival time 2.541 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.673 net: PUSHB_i 2.148 i_adc/scsn_slv_nw_nwl/ix956z24342:C (r) + 0.261 cell: ADLIB:NAND3 2.409 i_adc/scsn_slv_nw_nwl/ix956z24342:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/h1_not_rst_n_i 2.541 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR (f) 2.541 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.544 net: CLK40out N/C i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(6):CLR Expanded Path 6 From: PUSHB To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR data arrival time 2.636 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.763 net: PUSHB_i 2.238 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:C (r) + 0.261 cell: ADLIB:NAND3 2.499 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:Y (f) + 0.137 net: i_adc/scsn_slv_nw_dll_bt1/h1_not_rst_n_i 2.636 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR (f) 2.636 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.557 net: CLK40out N/C i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(1):CLR Expanded Path 7 From: PUSHB To: i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR data arrival time 2.631 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.763 net: PUSHB_i 2.238 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:C (r) + 0.261 cell: ADLIB:NAND3 2.499 i_adc/scsn_slv_nw_dll_bt1/ix65495z24338:Y (f) + 0.132 net: i_adc/scsn_slv_nw_dll_bt1/h1_not_rst_n_i 2.631 i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR (f) 2.631 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.551 net: CLK40out N/C i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_bt1/h1_reg_hm_state_out(2):CLR Expanded Path 8 From: PUSHB To: i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(7):CLR data arrival time 2.633 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.765 net: PUSHB_i 2.240 i_adc/scsn_slv_nw_nwl/sl0/ix63501z24337:C (r) + 0.261 cell: ADLIB:NAND3 2.501 i_adc/scsn_slv_nw_nwl/sl0/ix63501z24337:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/sl0/h1_not_rst_n_i 2.633 i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(7):CLR (f) 2.633 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.546 net: CLK40out N/C i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(7):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(7):CLR Expanded Path 9 From: PUSHB To: i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(0):CLR data arrival time 2.633 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.765 net: PUSHB_i 2.240 i_adc/scsn_slv_nw_nwl/sl0/ix63501z24337:C (r) + 0.261 cell: ADLIB:NAND3 2.501 i_adc/scsn_slv_nw_nwl/sl0/ix63501z24337:Y (f) + 0.132 net: i_adc/scsn_slv_nw_nwl/sl0/h1_not_rst_n_i 2.633 i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(0):CLR (f) 2.633 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.546 net: CLK40out N/C i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(0):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_nwl/sl0/h1_reg_hm_state_out(0):CLR Expanded Path 10 From: PUSHB To: i_adc/scsn_slv_nw_apl/h1_reg_hm_state_out(7):CLR data arrival time 2.707 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 0.460 cell: ADLIB:IOPAD_IN 0.460 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 0.460 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.015 cell: ADLIB:IOIN_IB 0.475 ibuf_PUSHB_ib/U0/U1:Y (r) + 1.794 net: PUSHB_i 2.269 i_adc/scsn_slv_nw_apl/ix63501z24337:C (r) + 0.261 cell: ADLIB:NAND3 2.530 i_adc/scsn_slv_nw_apl/ix63501z24337:Y (f) + 0.177 net: i_adc/scsn_slv_nw_apl/h1_not_rst_n_i 2.707 i_adc/scsn_slv_nw_apl/h1_reg_hm_state_out(7):CLR (f) 2.707 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 3.553 Clock generation N/C + 0.571 net: CLK40out N/C i_adc/scsn_slv_nw_apl/h1_reg_hm_state_out(7):CLK (r) + 0.000 Library removal time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_apl/h1_reg_hm_state_out(7):CLR END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLB Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin oddr_BC_ECL_ob/U0/U1:OCLK SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Hold No Path END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) Delay (ns): 1.229 Slack (ns): Arrival (ns): 8.344 Required (ns): Clock to Out (ns): 8.344 Path 2 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL Delay (ns): 1.229 Slack (ns): Arrival (ns): 8.344 Required (ns): Clock to Out (ns): 8.344 Path 3 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) Delay (ns): 1.229 Slack (ns): Arrival (ns): 8.345 Required (ns): Clock to Out (ns): 8.345 Expanded Path 1 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) data arrival time 8.344 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 6.678 Clock generation 6.678 + 0.437 net: CLK40out_90 7.115 oddr_PIMLINK_1_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 7.429 oddr_PIMLINK_1_ob/U0/U1:DOUT (r) + 0.000 net: oddr_PIMLINK_1_ob/U0/NET1 7.429 oddr_PIMLINK_1_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 8.344 oddr_PIMLINK_1_ob/U0/U0:PAD (r) + 0.000 net: PIMLINK_1_ 8.344 PIMLINK(1) (r) 8.344 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 6.678 Clock generation N/C N/C PIMLINK(1) (r) Expanded Path 2 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL data arrival time 8.344 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 6.678 Clock generation 6.678 + 0.437 net: CLK40out_90 7.115 oddr_BC_ECL_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 7.429 oddr_BC_ECL_ob/U0/U1:DOUT (r) + 0.000 net: oddr_BC_ECL_ob/U0/NET1 7.429 oddr_BC_ECL_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 8.344 oddr_BC_ECL_ob/U0/U0:PAD (r) + 0.000 net: BC_ECL 8.344 BC_ECL (r) 8.344 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 6.678 Clock generation N/C N/C BC_ECL (r) Expanded Path 3 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) data arrival time 8.345 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 6.678 Clock generation 6.678 + 0.438 net: CLK40out_90 7.116 oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.314 cell: ADLIB:IOTRI_OD_EB 7.430 oddr_PIMLINK_2_ob/U0/U1:DOUT (r) + 0.000 net: oddr_PIMLINK_2_ob/U0/NET1 7.430 oddr_PIMLINK_2_ob/U0/U0:D (r) + 0.915 cell: ADLIB:IOPAD_TRI 8.345 oddr_PIMLINK_2_ob/U0/U0:PAD (r) + 0.000 net: PIMLINK_2_ 8.345 PIMLINK(2) (r) 8.345 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 6.678 Clock generation N/C N/C PIMLINK(2) (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLC SET Register to Register Path 1 From: i_cbb/cbc_sample_reg_cb_par(3):CLK To: i_cbb/cbc_sample_reg_cb_par(5):D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 4.346 Required (ns): 4.007 Hold (ns): 0.000 Path 2 From: i_cbb/cbc_sample_reg_cb_par(2):CLK To: i_cbb/cbc_sample_reg_cb_par(4):D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 4.348 Required (ns): 4.009 Hold (ns): 0.000 Path 3 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 4.346 Required (ns): 4.007 Hold (ns): 0.000 Path 4 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D Delay (ns): 0.357 Slack (ns): 0.339 Arrival (ns): 4.348 Required (ns): 4.009 Hold (ns): 0.000 Path 5 From: i_cbb/cba_sample_reg_cb_par(3):CLK To: i_cbb/cba_sample_reg_cb_par(5):D Delay (ns): 0.357 Slack (ns): 0.340 Arrival (ns): 4.343 Required (ns): 4.003 Hold (ns): 0.000 Path 6 From: i_cbb/cba_sample_reg_cb_par(2):CLK To: i_cbb/cba_sample_reg_cb_par(4):D Delay (ns): 0.357 Slack (ns): 0.343 Arrival (ns): 4.346 Required (ns): 4.003 Hold (ns): 0.000 Path 7 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D Delay (ns): 1.014 Slack (ns): 0.997 Arrival (ns): 5.000 Required (ns): 4.003 Hold (ns): 0.000 Path 8 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D Delay (ns): 0.982 Slack (ns): 1.004 Arrival (ns): 5.007 Required (ns): 4.003 Hold (ns): 0.000 Path 9 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D Delay (ns): 1.114 Slack (ns): 1.093 Arrival (ns): 5.100 Required (ns): 4.007 Hold (ns): 0.000 Path 10 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D Delay (ns): 1.203 Slack (ns): 1.225 Arrival (ns): 5.228 Required (ns): 4.003 Hold (ns): 0.000 Expanded Path 1 From: i_cbb/cbc_sample_reg_cb_par(3):CLK To: i_cbb/cbc_sample_reg_cb_par(5):D data arrival time 4.346 data required time - 4.007 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.436 net: CLK80out 3.989 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.195 i_cbb/cbc_sample_reg_cb_par(3):Q (r) + 0.151 net: i_cbb/cbc_sample_cb_par_3_ 4.346 i_cbb/cbc_sample_reg_cb_par(5):D (r) 4.346 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK80out 4.007 i_cbb/cbc_sample_reg_cb_par(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.007 i_cbb/cbc_sample_reg_cb_par(5):D 4.007 data required time Expanded Path 2 From: i_cbb/cbc_sample_reg_cb_par(2):CLK To: i_cbb/cbc_sample_reg_cb_par(4):D data arrival time 4.348 data required time - 4.009 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.438 net: CLK80out 3.991 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.197 i_cbb/cbc_sample_reg_cb_par(2):Q (r) + 0.151 net: i_cbb/cbc_sample_cb_par_2_ 4.348 i_cbb/cbc_sample_reg_cb_par(4):D (r) 4.348 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.456 net: CLK80out 4.009 i_cbb/cbc_sample_reg_cb_par(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.009 i_cbb/cbc_sample_reg_cb_par(4):D 4.009 data required time Expanded Path 3 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D data arrival time 4.346 data required time - 4.007 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.436 net: CLK80out 3.989 i_cbb/cba_sample_reg_cb_par(0):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.195 i_cbb/cba_sample_reg_cb_par(0):Q (r) + 0.151 net: i_cbb/cba_sample_cb_par_0_ 4.346 i_cbb/cba_sample_reg_cb_par(2):D (r) 4.346 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK80out 4.007 i_cbb/cba_sample_reg_cb_par(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.007 i_cbb/cba_sample_reg_cb_par(2):D 4.007 data required time Expanded Path 4 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D data arrival time 4.348 data required time - 4.009 slack 0.339 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.438 net: CLK80out 3.991 i_cbb/cbc_sample_reg_cb_par(0):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.197 i_cbb/cbc_sample_reg_cb_par(0):Q (r) + 0.151 net: i_cbb/cbc_sample_cb_par_0_ 4.348 i_cbb/cbc_sample_reg_cb_par(2):D (r) 4.348 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.456 net: CLK80out 4.009 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.009 i_cbb/cbc_sample_reg_cb_par(2):D 4.009 data required time Expanded Path 5 From: i_cbb/cba_sample_reg_cb_par(3):CLK To: i_cbb/cba_sample_reg_cb_par(5):D data arrival time 4.343 data required time - 4.003 slack 0.340 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.433 net: CLK80out 3.986 i_cbb/cba_sample_reg_cb_par(3):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.192 i_cbb/cba_sample_reg_cb_par(3):Q (r) + 0.151 net: i_cbb/cba_sample_cb_par_3_ 4.343 i_cbb/cba_sample_reg_cb_par(5):D (r) 4.343 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.450 net: CLK80out 4.003 i_cbb/cba_sample_reg_cb_par(5):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.003 i_cbb/cba_sample_reg_cb_par(5):D 4.003 data required time Expanded Path 6 From: i_cbb/cba_sample_reg_cb_par(2):CLK To: i_cbb/cba_sample_reg_cb_par(4):D data arrival time 4.346 data required time - 4.003 slack 0.343 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.436 net: CLK80out 3.989 i_cbb/cba_sample_reg_cb_par(2):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.195 i_cbb/cba_sample_reg_cb_par(2):Q (r) + 0.151 net: i_cbb/cba_sample_cb_par_2_ 4.346 i_cbb/cba_sample_reg_cb_par(4):D (r) 4.346 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.450 net: CLK80out 4.003 i_cbb/cba_sample_reg_cb_par(4):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.003 i_cbb/cba_sample_reg_cb_par(4):D 4.003 data required time Expanded Path 7 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D data arrival time 5.000 data required time - 4.003 slack 0.997 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.433 net: CLK80out 3.986 i_cbb/cba_sample_reg_cb_par(1):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.192 i_cbb/cba_sample_reg_cb_par(1):Q (r) + 0.808 net: i_cbb/cba_sample_cb_par_1_ 5.000 i_cbb/cba_sample_reg_cb_par(3):D (r) 5.000 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.450 net: CLK80out 4.003 i_cbb/cba_sample_reg_cb_par(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.003 i_cbb/cba_sample_reg_cb_par(3):D 4.003 data required time Expanded Path 8 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D data arrival time 5.007 data required time - 4.003 slack 1.004 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.472 net: CLK80out 4.025 iddr_CB_C_ib/U0/U1:ICLK (r) + 0.127 cell: ADLIB:IOIN_ID 4.152 iddr_CB_C_ib/U0/U1:YF (f) + 0.855 net: CB_C_i_1_ 5.007 i_cbb/cbc_sample_reg_cb_par(1):D (f) 5.007 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.450 net: CLK80out 4.003 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.003 i_cbb/cbc_sample_reg_cb_par(1):D 4.003 data required time Expanded Path 9 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D data arrival time 5.100 data required time - 4.007 slack 1.093 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.433 net: CLK80out 3.986 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) + 0.206 cell: ADLIB:DFN1C1 4.192 i_cbb/cbc_sample_reg_cb_par(1):Q (r) + 0.908 net: i_cbb/cbc_sample_cb_par_1_ 5.100 i_cbb/cbc_sample_reg_cb_par(3):D (r) 5.100 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.454 net: CLK80out 4.007 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.007 i_cbb/cbc_sample_reg_cb_par(3):D 4.007 data required time Expanded Path 10 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D data arrival time 5.228 data required time - 4.003 slack 1.225 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.472 net: CLK80out 4.025 iddr_CB_A_ib/U0/U1:ICLK (r) + 0.127 cell: ADLIB:IOIN_ID 4.152 iddr_CB_A_ib/U0/U1:YF (f) + 1.076 net: CB_A_i_1_ 5.228 i_cbb/cba_sample_reg_cb_par(1):D (f) 5.228 data arrival time ________________________________________________________ Data required time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.450 net: CLK80out 4.003 i_cbb/cba_sample_reg_cb_par(1):CLK (r) + 0.000 Library hold time: ADLIB:DFN1C1 4.003 i_cbb/cba_sample_reg_cb_par(1):D 4.003 data required time END SET Register to Register ---------------------------------------------------- SET External Hold Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN Delay (ns): 0.286 Slack (ns): Arrival (ns): 0.286 Required (ns): Hold (ns): 0.000 External Hold (ns): 3.852 Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN Delay (ns): 0.286 Slack (ns): Arrival (ns): 0.286 Required (ns): Hold (ns): 0.000 External Hold (ns): 3.852 Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN Delay (ns): 0.286 Slack (ns): Arrival (ns): 0.286 Required (ns): Hold (ns): 0.000 External Hold (ns): 3.852 Expanded Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN data arrival time 0.286 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_C (f) + 0.000 net: CB_C 0.000 iddr_CB_C_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 iddr_CB_C_ib/U0/U0:Y (f) + 0.000 net: iddr_CB_C_ib/U0/NET1 0.286 iddr_CB_C_ib/U0/U1:YIN (f) 0.286 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation N/C + 0.585 net: CLK80out N/C iddr_CB_C_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C iddr_CB_C_ib/U0/U1:YIN Expanded Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN data arrival time 0.286 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 BUSY (f) + 0.000 net: BUSY 0.000 iddr_busy_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 iddr_busy_ib/U0/U0:Y (f) + 0.000 net: iddr_busy_ib/U0/NET1 0.286 iddr_busy_ib/U0/U1:YIN (f) 0.286 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation N/C + 0.585 net: CLK80out N/C iddr_busy_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C iddr_busy_ib/U0/U1:YIN Expanded Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN data arrival time 0.286 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_A (f) + 0.000 net: CB_A 0.000 iddr_CB_A_ib/U0/U0:PAD (f) + 0.286 cell: ADLIB:IOPAD_IN 0.286 iddr_CB_A_ib/U0/U0:Y (f) + 0.000 net: iddr_CB_A_ib/U0/NET1 0.286 iddr_CB_A_ib/U0/U1:YIN (f) 0.286 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation N/C + 0.585 net: CLK80out N/C iddr_CB_A_ib/U0/U1:ICLK (r) + 0.000 Library hold time: ADLIB:IOIN_ID N/C iddr_CB_A_ib/U0/U1:YIN END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n Delay (ns): 5.425 Slack (ns): Arrival (ns): 9.450 Required (ns): Clock to Out (ns): 9.450 Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p Delay (ns): 5.437 Slack (ns): Arrival (ns): 9.462 Required (ns): Clock to Out (ns): 9.462 Expanded Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n data arrival time 9.450 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.472 net: CLK80out 4.025 iddr_busy_ib/U0/U1:ICLK (r) + 0.127 cell: ADLIB:IOIN_ID 4.152 iddr_busy_ib/U0/U1:YF (f) + 2.148 net: BUSY_i_1_ 6.300 i_cbb/ix7212z10880:B (f) + 0.227 cell: ADLIB:XOR2 6.527 i_cbb/ix7212z10880:Y (r) + 1.002 net: i_cbb/nx7212z5 7.529 i_cbb/SPA:C (r) + 0.242 cell: ADLIB:XOR3 7.771 i_cbb/SPA:Y (r) + 0.856 net: SPA_i 8.627 lvds_SPA_iob/U0/U1:D (r) + 0.231 cell: ADLIB:IOTRI_OB_EB 8.858 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 8.858 lvds_SPA_iob/U0/U2:DB (r) + 0.592 cell: ADLIB:IOPADN_OUT 9.450 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 9.450 SPA_n (f) 9.450 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation N/C N/C SPA_n (f) Expanded Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p data arrival time 9.462 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation 3.553 + 0.472 net: CLK80out 4.025 iddr_busy_ib/U0/U1:ICLK (r) + 0.127 cell: ADLIB:IOIN_ID 4.152 iddr_busy_ib/U0/U1:YF (f) + 2.148 net: BUSY_i_1_ 6.300 i_cbb/ix7212z10880:B (f) + 0.227 cell: ADLIB:XOR2 6.527 i_cbb/ix7212z10880:Y (r) + 1.002 net: i_cbb/nx7212z5 7.529 i_cbb/SPA:C (r) + 0.242 cell: ADLIB:XOR3 7.771 i_cbb/SPA:Y (r) + 0.856 net: SPA_i 8.627 lvds_SPA_iob/U0/U1:D (r) + 0.231 cell: ADLIB:IOTRI_OB_EB 8.858 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 8.858 lvds_SPA_iob/U0/U0:D (r) + 0.604 cell: ADLIB:IOPADP_TRI 9.462 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 9.462 SPA_p (r) 9.462 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 3.553 Clock generation N/C N/C SPA_p (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain CLK40p Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin lvds_clk40in_U1/U0/U0:PAD SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Hold No Path END SET External Hold ---------------------------------------------------- SET Clock to Output Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p Delay (ns): 2.561 Slack (ns): Arrival (ns): 4.824 Required (ns): Clock to Out (ns): 4.824 Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n Delay (ns): 2.573 Slack (ns): Arrival (ns): 4.836 Required (ns): Clock to Out (ns): 4.836 Expanded Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p data arrival time 4.824 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (f) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 lvds_clk40in_U1/U0/U0:Y (f) + 0.000 net: lvds_clk40in_U1/U0/NET1 0.601 lvds_clk40in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 lvds_clk40in_U1/U0/U1:Y (f) + 1.648 net: CLK40_i 2.263 i_cbb/clock_generation_ipll_Core:CLKA (f) + 1.221 cell: ADLIB:PLL 3.484 i_cbb/clock_generation_ipll_Core:GLA (f) + 0.492 net: CLK40out 3.976 lvds_clk40out_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 4.205 lvds_clk40out_iob/U0/U1:DOUT (f) + 0.000 net: lvds_clk40out_iob/U0/NET1 4.205 lvds_clk40out_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.824 lvds_clk40out_iob/U0/U0:PAD (f) + 0.000 net: CLK40T_p 4.824 CLK40T_p (f) 4.824 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_p (f) Expanded Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n data arrival time 4.836 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (f) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 lvds_clk40in_U1/U0/U0:Y (f) + 0.000 net: lvds_clk40in_U1/U0/NET1 0.601 lvds_clk40in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 lvds_clk40in_U1/U0/U1:Y (f) + 1.648 net: CLK40_i 2.263 i_cbb/clock_generation_ipll_Core:CLKA (f) + 1.221 cell: ADLIB:PLL 3.484 i_cbb/clock_generation_ipll_Core:GLA (f) + 0.492 net: CLK40out 3.976 lvds_clk40out_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 4.205 lvds_clk40out_iob/U0/U1:DOUT (f) + 0.000 net: lvds_clk40out_iob/U0/NET1 4.205 lvds_clk40out_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.836 lvds_clk40out_iob/U0/U2:PAD (r) + 0.000 net: CLK40T_n 4.836 CLK40T_n (r) 4.836 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_n (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Removal No Path END SET External Removal ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Path set Pin to Pin SET Input to Output Path 1 From: S1_IN_n(1) To: SPA_p Delay (ns): 4.530 Slack (ns): Arrival (ns): 4.530 Required (ns): Path 2 From: S1_IN_n(1) To: SPA_n Delay (ns): 4.542 Slack (ns): Arrival (ns): 4.542 Required (ns): Path 3 From: S1_IN_p(1) To: SPA_p Delay (ns): 4.542 Slack (ns): Arrival (ns): 4.542 Required (ns): Path 4 From: SPC_n To: SPA_p Delay (ns): 4.549 Slack (ns): Arrival (ns): 4.549 Required (ns): Path 5 From: S1_IN_p(1) To: SPA_n Delay (ns): 4.554 Slack (ns): Arrival (ns): 4.554 Required (ns): Path 6 From: SPC_p To: SPA_p Delay (ns): 4.561 Slack (ns): Arrival (ns): 4.561 Required (ns): Path 7 From: SPC_n To: SPA_n Delay (ns): 4.561 Slack (ns): Arrival (ns): 4.561 Required (ns): Path 8 From: IF17x_SCSN_IN_n To: SCSNFEBOUTp Delay (ns): 4.569 Slack (ns): Arrival (ns): 4.569 Required (ns): Path 9 From: SPC_p To: SPA_n Delay (ns): 4.573 Slack (ns): Arrival (ns): 4.573 Required (ns): Path 10 From: IF17x_SCSN_IN_n To: SCSNFEBOUTn Delay (ns): 4.581 Slack (ns): Arrival (ns): 4.581 Required (ns): Expanded Path 1 From: S1_IN_n(1) To: SPA_p data arrival time 4.530 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_n(1) (f) + 0.000 net: S1_IN_n_1_ 0.000 adds1s2[1].lvds_S1in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[1].lvds_S1in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[1]_lvds_S1in_U1/U0/U2_N2P 0.000 adds1s2[1].lvds_S1in_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 adds1s2[1].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S1in_U1/U0/NET1 0.589 adds1s2[1].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 adds1s2[1].lvds_S1in_U1/U0/U1:Y (f) + 0.532 net: S1_IN_i_1_ 1.135 i_cbb/modgen_xor_1422_ix7212z10877:B (f) + 0.225 cell: ADLIB:XOR3 1.360 i_cbb/modgen_xor_1422_ix7212z10877:Y (f) + 1.379 net: i_cbb/nx7212z1 2.739 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 2.880 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.682 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.911 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.911 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.530 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.530 SPA_p (f) 4.530 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_n(1) (f) N/C SPA_p (f) N/C data required time Expanded Path 2 From: S1_IN_n(1) To: SPA_n data arrival time 4.542 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_n(1) (f) + 0.000 net: S1_IN_n_1_ 0.000 adds1s2[1].lvds_S1in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[1].lvds_S1in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[1]_lvds_S1in_U1/U0/U2_N2P 0.000 adds1s2[1].lvds_S1in_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 adds1s2[1].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S1in_U1/U0/NET1 0.589 adds1s2[1].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 adds1s2[1].lvds_S1in_U1/U0/U1:Y (f) + 0.532 net: S1_IN_i_1_ 1.135 i_cbb/modgen_xor_1422_ix7212z10877:B (f) + 0.225 cell: ADLIB:XOR3 1.360 i_cbb/modgen_xor_1422_ix7212z10877:Y (f) + 1.379 net: i_cbb/nx7212z1 2.739 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 2.880 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.682 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.911 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.911 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.542 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.542 SPA_n (r) 4.542 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_n(1) (f) N/C SPA_n (r) N/C data required time Expanded Path 3 From: S1_IN_p(1) To: SPA_p data arrival time 4.542 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_p(1) (f) + 0.000 net: S1_IN_p_1_ 0.000 adds1s2[1].lvds_S1in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 adds1s2[1].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S1in_U1/U0/NET1 0.601 adds1s2[1].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 adds1s2[1].lvds_S1in_U1/U0/U1:Y (f) + 0.532 net: S1_IN_i_1_ 1.147 i_cbb/modgen_xor_1422_ix7212z10877:B (f) + 0.225 cell: ADLIB:XOR3 1.372 i_cbb/modgen_xor_1422_ix7212z10877:Y (f) + 1.379 net: i_cbb/nx7212z1 2.751 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 2.892 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.694 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.923 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.923 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.542 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.542 SPA_p (f) 4.542 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_p(1) (f) N/C SPA_p (f) N/C data required time Expanded Path 4 From: SPC_n To: SPA_p data arrival time 4.549 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SPC_n (f) + 0.000 net: SPC_n 0.000 lvds_SPC_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_SPC_U1/U0/U2:N2POUT (f) + 0.000 net: lvds_SPC_U1/U0/U2_N2P 0.000 lvds_SPC_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 lvds_SPC_U1/U0/U0:Y (f) + 0.000 net: lvds_SPC_U1/U0/NET1 0.589 lvds_SPC_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 lvds_SPC_U1/U0/U1:Y (f) + 0.921 net: SPC_i 1.524 i_cbb/modgen_xor_1422_ix7212z10879:B (f) + 0.225 cell: ADLIB:XOR3 1.749 i_cbb/modgen_xor_1422_ix7212z10879:Y (f) + 0.933 net: i_cbb/nx7212z3 2.682 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.899 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.701 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.930 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.930 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.549 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.549 SPA_p (f) 4.549 data arrival time ________________________________________________________ Data required time calculation N/C SPC_n (f) N/C SPA_p (f) N/C data required time Expanded Path 5 From: S1_IN_p(1) To: SPA_n data arrival time 4.554 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 S1_IN_p(1) (f) + 0.000 net: S1_IN_p_1_ 0.000 adds1s2[1].lvds_S1in_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 adds1s2[1].lvds_S1in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S1in_U1/U0/NET1 0.601 adds1s2[1].lvds_S1in_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 adds1s2[1].lvds_S1in_U1/U0/U1:Y (f) + 0.532 net: S1_IN_i_1_ 1.147 i_cbb/modgen_xor_1422_ix7212z10877:B (f) + 0.225 cell: ADLIB:XOR3 1.372 i_cbb/modgen_xor_1422_ix7212z10877:Y (f) + 1.379 net: i_cbb/nx7212z1 2.751 i_cbb/SPA:A (f) + 0.141 cell: ADLIB:XOR3 2.892 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.694 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.923 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.923 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.554 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.554 SPA_n (r) 4.554 data arrival time ________________________________________________________ Data required time calculation N/C S1_IN_p(1) (f) N/C SPA_n (r) N/C data required time Expanded Path 6 From: SPC_p To: SPA_p data arrival time 4.561 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SPC_p (f) + 0.000 net: SPC_p 0.000 lvds_SPC_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 lvds_SPC_U1/U0/U0:Y (f) + 0.000 net: lvds_SPC_U1/U0/NET1 0.601 lvds_SPC_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 lvds_SPC_U1/U0/U1:Y (f) + 0.921 net: SPC_i 1.536 i_cbb/modgen_xor_1422_ix7212z10879:B (f) + 0.225 cell: ADLIB:XOR3 1.761 i_cbb/modgen_xor_1422_ix7212z10879:Y (f) + 0.933 net: i_cbb/nx7212z3 2.694 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.911 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.713 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.942 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.942 lvds_SPA_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.561 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 4.561 SPA_p (f) 4.561 data arrival time ________________________________________________________ Data required time calculation N/C SPC_p (f) N/C SPA_p (f) N/C data required time Expanded Path 7 From: SPC_n To: SPA_n data arrival time 4.561 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SPC_n (f) + 0.000 net: SPC_n 0.000 lvds_SPC_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_SPC_U1/U0/U2:N2POUT (f) + 0.000 net: lvds_SPC_U1/U0/U2_N2P 0.000 lvds_SPC_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 lvds_SPC_U1/U0/U0:Y (f) + 0.000 net: lvds_SPC_U1/U0/NET1 0.589 lvds_SPC_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 lvds_SPC_U1/U0/U1:Y (f) + 0.921 net: SPC_i 1.524 i_cbb/modgen_xor_1422_ix7212z10879:B (f) + 0.225 cell: ADLIB:XOR3 1.749 i_cbb/modgen_xor_1422_ix7212z10879:Y (f) + 0.933 net: i_cbb/nx7212z3 2.682 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.899 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.701 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.930 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.930 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.561 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.561 SPA_n (r) 4.561 data arrival time ________________________________________________________ Data required time calculation N/C SPC_n (f) N/C SPA_n (r) N/C data required time Expanded Path 8 From: IF17x_SCSN_IN_n To: SCSNFEBOUTp data arrival time 4.569 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 IF17x_SCSN_IN_n (f) + 0.000 net: IF17x_SCSN_IN_n 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:N2POUT (f) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/U2_N2P 0.000 lvds_IF17x_SCSN_IN_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 lvds_IF17x_SCSN_IN_U1/U0/U0:Y (f) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/NET1 0.589 lvds_IF17x_SCSN_IN_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 lvds_IF17x_SCSN_IN_U1/U0/U1:Y (f) + 3.144 net: SCSNFEBOUT_i 3.747 lvds_SCSNFEBOUT_iob/U0/U1:D (f) + 0.203 cell: ADLIB:IOTRI_OB_EB 3.950 lvds_SCSNFEBOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNFEBOUT_iob/U0/NET1 3.950 lvds_SCSNFEBOUT_iob/U0/U0:D (f) + 0.619 cell: ADLIB:IOPADP_TRI 4.569 lvds_SCSNFEBOUT_iob/U0/U0:PAD (f) + 0.000 net: SCSNFEBOUTp 4.569 SCSNFEBOUTp (f) 4.569 data arrival time ________________________________________________________ Data required time calculation N/C IF17x_SCSN_IN_n (f) N/C SCSNFEBOUTp (f) N/C data required time Expanded Path 9 From: SPC_p To: SPA_n data arrival time 4.573 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 SPC_p (f) + 0.000 net: SPC_p 0.000 lvds_SPC_U1/U0/U0:PAD (f) + 0.601 cell: ADLIB:IOPADP_IN 0.601 lvds_SPC_U1/U0/U0:Y (f) + 0.000 net: lvds_SPC_U1/U0/NET1 0.601 lvds_SPC_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.615 lvds_SPC_U1/U0/U1:Y (f) + 0.921 net: SPC_i 1.536 i_cbb/modgen_xor_1422_ix7212z10879:B (f) + 0.225 cell: ADLIB:XOR3 1.761 i_cbb/modgen_xor_1422_ix7212z10879:Y (f) + 0.933 net: i_cbb/nx7212z3 2.694 i_cbb/SPA:B (f) + 0.217 cell: ADLIB:XOR3 2.911 i_cbb/SPA:Y (f) + 0.802 net: SPA_i 3.713 lvds_SPA_iob/U0/U1:D (f) + 0.229 cell: ADLIB:IOTRI_OB_EB 3.942 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 3.942 lvds_SPA_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.573 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 4.573 SPA_n (r) 4.573 data arrival time ________________________________________________________ Data required time calculation N/C SPC_p (f) N/C SPA_n (r) N/C data required time Expanded Path 10 From: IF17x_SCSN_IN_n To: SCSNFEBOUTn data arrival time 4.581 data required time - N/C slack N/C ________________________________________________________ Data arrival time calculation 0.000 IF17x_SCSN_IN_n (f) + 0.000 net: IF17x_SCSN_IN_n 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:N2POUT (f) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/U2_N2P 0.000 lvds_IF17x_SCSN_IN_U1/U0/U0:N2PIN (f) + 0.589 cell: ADLIB:IOPADP_IN 0.589 lvds_IF17x_SCSN_IN_U1/U0/U0:Y (f) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/NET1 0.589 lvds_IF17x_SCSN_IN_U1/U0/U1:YIN (f) + 0.014 cell: ADLIB:IOIN_IB 0.603 lvds_IF17x_SCSN_IN_U1/U0/U1:Y (f) + 3.144 net: SCSNFEBOUT_i 3.747 lvds_SCSNFEBOUT_iob/U0/U1:D (f) + 0.203 cell: ADLIB:IOTRI_OB_EB 3.950 lvds_SCSNFEBOUT_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SCSNFEBOUT_iob/U0/NET1 3.950 lvds_SCSNFEBOUT_iob/U0/U2:DB (f) + 0.631 cell: ADLIB:IOPADN_OUT 4.581 lvds_SCSNFEBOUT_iob/U0/U2:PAD (r) + 0.000 net: SCSNFEBOUTn 4.581 SCSNFEBOUTn (r) 4.581 data arrival time ________________________________________________________ Data required time calculation N/C IF17x_SCSN_IN_n (f) N/C SCSNFEBOUTn (r) N/C data required time END SET Input to Output ---------------------------------------------------- Path set User Sets