Timing Report Max Delay Analysis SmartTime Version v9.1 SP3 Actel Corporation - Actel Designer Software Release v9.1 SP3 (Version 9.1.3.4) Copyright (c) 1989-2010 Date: Thu Aug 11 22:20:30 2011 Design: actel_par_A3PE3000 Family: ProASIC3E Die: A3PE3000 Package: 208 PQFP Temperature: COM Voltage: COM Speed Grade: -2 Design State: Post-Layout Data source: Silicon verified Min Operating Condition: BEST Max Operating Condition: WORST Using Enhanced Min Delay Analysis Scenario for Timing Analysis: Primary ----------------------------------------------------- SUMMARY Clock Domain: SIU_RXCLK Period (ns): 6.264 Frequency (MHz): 159.642 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 0.612 External Hold (ns): 0.964 Min Clock-To-Out (ns): N/A Max Clock-To-Out (ns): N/A Clock Domain: SIU_TXCLK Period (ns): 7.517 Frequency (MHz): 133.032 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 8.999 External Hold (ns): 1.489 Min Clock-To-Out (ns): 3.536 Max Clock-To-Out (ns): 16.454 Clock Domain: i_SIU/reg_tx_clk_2:Q Period (ns): 8.289 Frequency (MHz): 120.642 Required Period (ns): 18.182 Required Frequency (MHz): 54.999 External Setup (ns): 7.079 External Hold (ns): -0.468 Min Clock-To-Out (ns): 5.921 Max Clock-To-Out (ns): 15.872 Clock Domain: i_adc/cdiv_reg_q:Q Period (ns): 12.222 Frequency (MHz): 81.820 Required Period (ns): 100.000 Required Frequency (MHz): 10.000 External Setup (ns): 3.387 External Hold (ns): -0.792 Min Clock-To-Out (ns): 5.294 Max Clock-To-Out (ns): 14.369 Clock Domain: i_cbb/clock_generation_ipll_Core:GLA Period (ns): 19.421 Frequency (MHz): 51.491 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): 8.303 External Hold (ns): 2.990 Min Clock-To-Out (ns): 5.765 Max Clock-To-Out (ns): 23.945 Clock Domain: i_cbb/clock_generation_ipll_Core:GLB Period (ns): 0.926 Frequency (MHz): 1079.914 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): 3.924 External Hold (ns): 0.674 Min Clock-To-Out (ns): 8.893 Max Clock-To-Out (ns): 15.347 Clock Domain: i_cbb/clock_generation_ipll_Core:GLC Period (ns): 6.657 Frequency (MHz): 150.218 Required Period (ns): 12.500 Required Frequency (MHz): 80.000 External Setup (ns): -7.554 External Hold (ns): 4.443 Min Clock-To-Out (ns): 10.866 Max Clock-To-Out (ns): 22.751 Clock Domain: CLK40p Period (ns): 2.860 Frequency (MHz): 349.650 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 5.304 Max Clock-To-Out (ns): 10.724 Input to Output Min Delay (ns): 4.464 Max Delay (ns): 14.068 END SUMMARY ----------------------------------------------------- Clock Domain SIU_RXCLK SET Register to Register Path 1 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(14):D Delay (ns): 5.862 Slack (ns): 2.827 Arrival (ns): 11.004 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 6.264 Path 2 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(15):D Delay (ns): 5.698 Slack (ns): 2.991 Arrival (ns): 10.840 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 6.100 Path 3 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(14):D Delay (ns): 5.630 Slack (ns): 3.033 Arrival (ns): 10.798 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 6.058 Path 4 From: i_SIU/reg_q(0):CLK To: i_SIU/reg_q(14):D Delay (ns): 5.591 Slack (ns): 3.098 Arrival (ns): 10.733 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 5.993 Path 5 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(9):D Delay (ns): 5.604 Slack (ns): 3.102 Arrival (ns): 10.746 Required (ns): 13.848 Setup (ns): 0.402 Minimum Period (ns): 5.989 Path 6 From: i_SIU/reg_q(4):CLK To: i_SIU/reg_q(14):D Delay (ns): 5.497 Slack (ns): 3.175 Arrival (ns): 10.656 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 5.916 Path 7 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(15):D Delay (ns): 5.466 Slack (ns): 3.197 Arrival (ns): 10.634 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 5.894 Path 8 From: i_SIU/reg_q(6):CLK To: i_SIU/reg_q(14):D Delay (ns): 5.470 Slack (ns): 3.202 Arrival (ns): 10.629 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 5.889 Path 9 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(10):D Delay (ns): 5.498 Slack (ns): 3.208 Arrival (ns): 10.640 Required (ns): 13.848 Setup (ns): 0.402 Minimum Period (ns): 5.883 Path 10 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(16):D Delay (ns): 5.479 Slack (ns): 3.210 Arrival (ns): 10.621 Required (ns): 13.831 Setup (ns): 0.402 Minimum Period (ns): 5.881 Expanded Path 1 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(14):D data required time 13.831 data arrival time - 11.004 slack 2.827 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 5.142 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.692 i_SIU/reg_q(16):Q (f) + 0.337 net: i_SIU/RXIN_INST_v_por_timer_16_ 6.029 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 6.590 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.933 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.430 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.751 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 8.143 i_SIU/NOT_a(0):Y (f) + 1.241 net: i_SIU/NOT_a_0_ 9.384 i_SIU/NOT_ix21084z49935:A (f) + 0.401 cell: ADLIB:NAND2B 9.785 i_SIU/NOT_ix21084z49935:Y (f) + 0.241 net: i_SIU/nx21084z2 10.026 i_SIU/ix21084z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.763 i_SIU/ix21084z21032:Y (f) + 0.241 net: i_SIU/nx21084z1 11.004 i_SIU/reg_q(14):D (f) 11.004 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(14):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(14):D 13.831 data required time Expanded Path 2 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(15):D data required time 13.831 data arrival time - 10.840 slack 2.991 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 5.142 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.692 i_SIU/reg_q(16):Q (f) + 0.337 net: i_SIU/RXIN_INST_v_por_timer_16_ 6.029 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 6.590 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.933 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.430 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.751 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 8.143 i_SIU/NOT_a(0):Y (f) + 0.984 net: i_SIU/NOT_a_0_ 9.127 i_SIU/NOT_ix22081z50932:A (f) + 0.496 cell: ADLIB:NAND3B 9.623 i_SIU/NOT_ix22081z50932:Y (f) + 0.241 net: i_SIU/nx22081z2 9.864 i_SIU/ix22081z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.601 i_SIU/ix22081z21032:Y (f) + 0.239 net: i_SIU/nx22081z1 10.840 i_SIU/reg_q(15):D (f) 10.840 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(15):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(15):D 13.831 data required time Expanded Path 3 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(14):D data required time 13.831 data arrival time - 10.798 slack 3.033 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb 5.168 i_SIU/reg_q(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.602 i_SIU/reg_q(1):Q (r) + 0.316 net: i_SIU/nx32078z4 5.918 i_SIU/NOT_ix32078z50931:C (r) + 0.466 cell: ADLIB:NAND3A 6.384 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.727 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.224 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.545 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.937 i_SIU/NOT_a(0):Y (f) + 1.241 net: i_SIU/NOT_a_0_ 9.178 i_SIU/NOT_ix21084z49935:A (f) + 0.401 cell: ADLIB:NAND2B 9.579 i_SIU/NOT_ix21084z49935:Y (f) + 0.241 net: i_SIU/nx21084z2 9.820 i_SIU/ix21084z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.557 i_SIU/ix21084z21032:Y (f) + 0.241 net: i_SIU/nx21084z1 10.798 i_SIU/reg_q(14):D (f) 10.798 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(14):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(14):D 13.831 data required time Expanded Path 4 From: i_SIU/reg_q(0):CLK To: i_SIU/reg_q(14):D data required time 13.831 data arrival time - 10.733 slack 3.098 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 5.142 i_SIU/reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.576 i_SIU/reg_q(0):Q (r) + 0.351 net: i_SIU/nx32078z3 5.927 i_SIU/NOT_ix32078z50931:B (r) + 0.392 cell: ADLIB:NAND3A 6.319 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.662 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.159 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.480 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.872 i_SIU/NOT_a(0):Y (f) + 1.241 net: i_SIU/NOT_a_0_ 9.113 i_SIU/NOT_ix21084z49935:A (f) + 0.401 cell: ADLIB:NAND2B 9.514 i_SIU/NOT_ix21084z49935:Y (f) + 0.241 net: i_SIU/nx21084z2 9.755 i_SIU/ix21084z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.492 i_SIU/ix21084z21032:Y (f) + 0.241 net: i_SIU/nx21084z1 10.733 i_SIU/reg_q(14):D (f) 10.733 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(14):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(14):D 13.831 data required time Expanded Path 5 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(9):D data required time 13.848 data arrival time - 10.746 slack 3.102 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 5.142 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.692 i_SIU/reg_q(16):Q (f) + 0.337 net: i_SIU/RXIN_INST_v_por_timer_16_ 6.029 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 6.590 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.933 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.430 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.751 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 8.143 i_SIU/NOT_a(0):Y (f) + 0.901 net: i_SIU/NOT_a_0_ 9.044 i_SIU/NOT_ix60244z49934:A (f) + 0.485 cell: ADLIB:NAND2A 9.529 i_SIU/NOT_ix60244z49934:Y (f) + 0.241 net: i_SIU/nx60244z2 9.770 i_SIU/ix60244z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.507 i_SIU/ix60244z21032:Y (f) + 0.239 net: i_SIU/nx60244z1 10.746 i_SIU/reg_q(9):D (f) 10.746 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.700 net: SIU_RXCLK_cb 14.250 i_SIU/reg_q(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.848 i_SIU/reg_q(9):D 13.848 data required time Expanded Path 6 From: i_SIU/reg_q(4):CLK To: i_SIU/reg_q(14):D data required time 13.831 data arrival time - 10.656 slack 3.175 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.700 net: SIU_RXCLK_cb 5.159 i_SIU/reg_q(4):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.709 i_SIU/reg_q(4):Q (f) + 0.389 net: i_SIU/nx56256z3 6.098 i_SIU/NOT_ix32078z24340:B (f) + 0.469 cell: ADLIB:NAND2 6.567 i_SIU/NOT_ix32078z24340:Y (r) + 0.901 net: i_SIU/nx32078z6 7.468 i_SIU/NOT_a(0):B (r) + 0.479 cell: ADLIB:NAND3C 7.947 i_SIU/NOT_a(0):Y (r) + 1.325 net: i_SIU/NOT_a_0_ 9.272 i_SIU/NOT_ix21084z49935:A (r) + 0.348 cell: ADLIB:NAND2B 9.620 i_SIU/NOT_ix21084z49935:Y (r) + 0.249 net: i_SIU/nx21084z2 9.869 i_SIU/ix21084z21032:B (r) + 0.546 cell: ADLIB:XA1A 10.415 i_SIU/ix21084z21032:Y (f) + 0.241 net: i_SIU/nx21084z1 10.656 i_SIU/reg_q(14):D (f) 10.656 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(14):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(14):D 13.831 data required time Expanded Path 7 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(15):D data required time 13.831 data arrival time - 10.634 slack 3.197 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb 5.168 i_SIU/reg_q(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.602 i_SIU/reg_q(1):Q (r) + 0.316 net: i_SIU/nx32078z4 5.918 i_SIU/NOT_ix32078z50931:C (r) + 0.466 cell: ADLIB:NAND3A 6.384 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.727 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.224 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.545 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.937 i_SIU/NOT_a(0):Y (f) + 0.984 net: i_SIU/NOT_a_0_ 8.921 i_SIU/NOT_ix22081z50932:A (f) + 0.496 cell: ADLIB:NAND3B 9.417 i_SIU/NOT_ix22081z50932:Y (f) + 0.241 net: i_SIU/nx22081z2 9.658 i_SIU/ix22081z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.395 i_SIU/ix22081z21032:Y (f) + 0.239 net: i_SIU/nx22081z1 10.634 i_SIU/reg_q(15):D (f) 10.634 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(15):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(15):D 13.831 data required time Expanded Path 8 From: i_SIU/reg_q(6):CLK To: i_SIU/reg_q(14):D data required time 13.831 data arrival time - 10.629 slack 3.202 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.700 net: SIU_RXCLK_cb 5.159 i_SIU/reg_q(6):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.709 i_SIU/reg_q(6):Q (f) + 0.330 net: i_SIU/nx58250z3 6.039 i_SIU/ix32078z24341:B (f) + 0.469 cell: ADLIB:NAND2 6.508 i_SIU/ix32078z24341:Y (r) + 0.902 net: i_SIU/nx32078z8 7.410 i_SIU/NOT_a(0):C (r) + 0.510 cell: ADLIB:NAND3C 7.920 i_SIU/NOT_a(0):Y (r) + 1.325 net: i_SIU/NOT_a_0_ 9.245 i_SIU/NOT_ix21084z49935:A (r) + 0.348 cell: ADLIB:NAND2B 9.593 i_SIU/NOT_ix21084z49935:Y (r) + 0.249 net: i_SIU/nx21084z2 9.842 i_SIU/ix21084z21032:B (r) + 0.546 cell: ADLIB:XA1A 10.388 i_SIU/ix21084z21032:Y (f) + 0.241 net: i_SIU/nx21084z1 10.629 i_SIU/reg_q(14):D (f) 10.629 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(14):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(14):D 13.831 data required time Expanded Path 9 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(10):D data required time 13.848 data arrival time - 10.640 slack 3.208 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 5.142 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.692 i_SIU/reg_q(16):Q (f) + 0.337 net: i_SIU/RXIN_INST_v_por_timer_16_ 6.029 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 6.590 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.933 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.430 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.751 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 8.143 i_SIU/NOT_a(0):Y (f) + 0.783 net: i_SIU/NOT_a_0_ 8.926 i_SIU/NOT_ix17096z50931:A (f) + 0.497 cell: ADLIB:NAND3A 9.423 i_SIU/NOT_ix17096z50931:Y (f) + 0.241 net: i_SIU/nx17096z2 9.664 i_SIU/ix17096z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.401 i_SIU/ix17096z21032:Y (f) + 0.239 net: i_SIU/nx17096z1 10.640 i_SIU/reg_q(10):D (f) 10.640 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.700 net: SIU_RXCLK_cb 14.250 i_SIU/reg_q(10):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.848 i_SIU/reg_q(10):D 13.848 data required time Expanded Path 10 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(16):D data required time 13.831 data arrival time - 10.621 slack 3.210 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 3.901 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 4.459 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 5.142 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.692 i_SIU/reg_q(16):Q (f) + 0.337 net: i_SIU/RXIN_INST_v_por_timer_16_ 6.029 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 6.590 i_SIU/NOT_ix32078z50931:Y (f) + 0.343 net: i_SIU/nx32078z2 6.933 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.430 i_SIU/NOT_ix32078z50930:Y (f) + 0.321 net: i_SIU/nx32078z1 7.751 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 8.143 i_SIU/NOT_a(0):Y (f) + 0.869 net: i_SIU/NOT_a_0_ 9.012 i_SIU/NOT_ix23078z50933:A (f) + 0.392 cell: ADLIB:NAND3C 9.404 i_SIU/NOT_ix23078z50933:Y (f) + 0.241 net: i_SIU/nx23078z2 9.645 i_SIU/ix23078z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.382 i_SIU/ix23078z21032:Y (f) + 0.239 net: i_SIU/nx23078z1 10.621 i_SIU/reg_q(16):D (f) 10.621 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i 12.992 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.550 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 14.233 i_SIU/reg_q(16):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.831 i_SIU/reg_q(16):D 13.831 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: SIU_RXD(11) To: addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.612 Path 2 From: SIU_RXD(8) To: addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.612 Path 3 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 4 From: SIU_RXD(2) To: addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 5 From: SIU_RXD(3) To: addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 6 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 7 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 8 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 9 From: SIU_RXD(10) To: addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Path 10 From: SIU_RXD(6) To: addds[6].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 0.605 Expanded Path 1 From: SIU_RXD(11) To: addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(11) (r) + 0.000 net: SIU_RXD_11_ 0.000 addds[11].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[11].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[11]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.702 net: SIU_RXCLK_cb N/C addds[11].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 2 From: SIU_RXD(8) To: addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(8) (r) + 0.000 net: SIU_RXD_8_ 0.000 addds[8].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[8].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[8]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.702 net: SIU_RXCLK_cb N/C addds[8].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 3 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXDV (r) + 0.000 net: SIU_RXDV 0.000 ibuf_SIU_RXDV_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 ibuf_SIU_RXDV_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXDV_ib/U0/NET1 5.547 ibuf_SIU_RXDV_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C ibuf_SIU_RXDV_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXDV_ib/U0/U1:YIN Expanded Path 4 From: SIU_RXD(2) To: addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(2) (r) + 0.000 net: SIU_RXD_2_ 0.000 addds[2].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[2].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[2]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[2].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 5 From: SIU_RXD(3) To: addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(3) (r) + 0.000 net: SIU_RXD_3_ 0.000 addds[3].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[3].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[3]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[3].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 6 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(7) (r) + 0.000 net: SIU_RXD_7_ 0.000 addds[7].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[7].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[7]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 7 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXER (r) + 0.000 net: SIU_RXER 0.000 ibuf_SIU_RXER_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 ibuf_SIU_RXER_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXER_ib/U0/NET1 5.547 ibuf_SIU_RXER_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C ibuf_SIU_RXER_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXER_ib/U0/U1:YIN Expanded Path 8 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(9) (r) + 0.000 net: SIU_RXD_9_ 0.000 addds[9].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[9].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[9]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 9 From: SIU_RXD(10) To: addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(10) (r) + 0.000 net: SIU_RXD_10_ 0.000 addds[10].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[10].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[10]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[10].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[10].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 10 From: SIU_RXD(6) To: addds[6].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(6) (r) + 0.000 net: SIU_RXD_6_ 0.000 addds[6].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[6].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[6]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[6].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[6].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[6].ibuf_SIU_RXD_ib/U0/U1:YIN END SET External Setup ---------------------------------------------------- SET Clock to Output No Path END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: i_SIU/reg_b_rx_cext:CLR Delay (ns): 14.342 Slack (ns): Arrival (ns): 14.342 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.464 Path 2 From: PUSHB To: addds[7].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 14.315 Slack (ns): Arrival (ns): 14.315 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.369 Path 3 From: PUSHB To: addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 14.127 Slack (ns): Arrival (ns): 14.127 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.180 Path 4 From: PUSHB To: addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 14.127 Slack (ns): Arrival (ns): 14.127 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.180 Path 5 From: PUSHB To: ibuf_SIU_RXER_ib/U0/U1:CLR Delay (ns): 13.939 Slack (ns): Arrival (ns): 13.939 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.993 Path 6 From: PUSHB To: addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 13.918 Slack (ns): Arrival (ns): 13.918 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.972 Path 7 From: PUSHB To: addds[14].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 13.875 Slack (ns): Arrival (ns): 13.875 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.928 Path 8 From: PUSHB To: addds[15].ibuf_SIU_RXD_ib/U0/U1:CLR Delay (ns): 13.725 Slack (ns): Arrival (ns): 13.725 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.778 Path 9 From: PUSHB To: ibuf_SIU_RXDV_ib/U0/U1:CLR Delay (ns): 13.685 Slack (ns): Arrival (ns): 13.685 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.739 Path 10 From: PUSHB To: i_SIU/reg_s_sreset:PRE Delay (ns): 13.350 Slack (ns): Arrival (ns): 13.350 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.450 Expanded Path 1 From: PUSHB To: i_SIU/reg_b_rx_cext:CLR data required time N/C data arrival time - 14.342 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.918 net: not_rst_n 14.342 i_SIU/reg_b_rx_cext:CLR (f) 14.342 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.641 net: SIU_RXCLK_cb N/C i_SIU/reg_b_rx_cext:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_rx_cext:CLR Expanded Path 2 From: PUSHB To: addds[7].ibuf_SIU_RXD_ib/U0/U1:CLR data required time N/C data arrival time - 14.315 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.891 net: not_rst_n 14.315 addds[7].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 14.315 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 3 From: PUSHB To: addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR data required time N/C data arrival time - 14.127 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.703 net: not_rst_n 14.127 addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 14.127 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.710 net: SIU_RXCLK_cb N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 4 From: PUSHB To: addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR data required time N/C data arrival time - 14.127 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.703 net: not_rst_n 14.127 addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 14.127 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.710 net: SIU_RXCLK_cb N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 5 From: PUSHB To: ibuf_SIU_RXER_ib/U0/U1:CLR data required time N/C data arrival time - 13.939 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.515 net: not_rst_n 13.939 ibuf_SIU_RXER_ib/U0/U1:CLR (f) 13.939 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C ibuf_SIU_RXER_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXER_ib/U0/U1:CLR Expanded Path 6 From: PUSHB To: addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR data required time N/C data arrival time - 13.918 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.494 net: not_rst_n 13.918 addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 13.918 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C addds[6].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C addds[6].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 7 From: PUSHB To: addds[14].ibuf_SIU_RXD_ib/U0/U1:CLR data required time N/C data arrival time - 13.875 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.451 net: not_rst_n 13.875 addds[14].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 13.875 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.710 net: SIU_RXCLK_cb N/C addds[14].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C addds[14].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 8 From: PUSHB To: addds[15].ibuf_SIU_RXD_ib/U0/U1:CLR data required time N/C data arrival time - 13.725 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.301 net: not_rst_n 13.725 addds[15].ibuf_SIU_RXD_ib/U0/U1:CLR (f) 13.725 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.710 net: SIU_RXCLK_cb N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:CLR Expanded Path 9 From: PUSHB To: ibuf_SIU_RXDV_ib/U0/U1:CLR data required time N/C data arrival time - 13.685 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.261 net: not_rst_n 13.685 ibuf_SIU_RXDV_ib/U0/U1:CLR (f) 13.685 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.709 net: SIU_RXCLK_cb N/C ibuf_SIU_RXDV_ib/U0/U1:ICLK (r) - 0.222 Library recovery time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXDV_ib/U0/U1:CLR Expanded Path 10 From: PUSHB To: i_SIU/reg_s_sreset:PRE data required time N/C data arrival time - 13.350 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 4.926 net: not_rst_n 13.350 i_SIU/reg_s_sreset:PRE (f) 13.350 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 2.740 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.663 net: SIU_RXCLK_cb N/C i_SIU/reg_s_sreset:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1P1 N/C i_SIU/reg_s_sreset:PRE END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain SIU_TXCLK SET Register to Register Path 1 From: i_SIU/CMSIU_INST/reg_q(4):CLK To: i_SIU/CMSIU_INST/reg_q(18):D Delay (ns): 6.651 Slack (ns): 2.037 Arrival (ns): 11.777 Required (ns): 13.814 Setup (ns): 0.402 Minimum Period (ns): 7.054 Path 2 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_txd_sts2(11):D Delay (ns): 6.392 Slack (ns): 2.106 Arrival (ns): 11.641 Required (ns): 13.747 Setup (ns): 0.428 Minimum Period (ns): 6.985 Path 3 From: i_SIU/CMSIU_INST/reg_q(5):CLK To: i_SIU/CMSIU_INST/reg_q(18):D Delay (ns): 6.498 Slack (ns): 2.190 Arrival (ns): 11.624 Required (ns): 13.814 Setup (ns): 0.402 Minimum Period (ns): 6.901 Path 4 From: i_SIU/CMSIU_INST/reg_q(4):CLK To: i_SIU/CMSIU_INST/reg_q(20):D Delay (ns): 6.477 Slack (ns): 2.212 Arrival (ns): 11.603 Required (ns): 13.815 Setup (ns): 0.402 Minimum Period (ns): 6.879 Path 5 From: i_SIU/CMSIU_INST/reg_q(4):CLK To: i_SIU/CMSIU_INST/reg_q(16):D Delay (ns): 6.435 Slack (ns): 2.257 Arrival (ns): 11.561 Required (ns): 13.818 Setup (ns): 0.402 Minimum Period (ns): 6.834 Path 6 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_s_crc_in(6):D Delay (ns): 6.308 Slack (ns): 2.272 Arrival (ns): 11.557 Required (ns): 13.829 Setup (ns): 0.402 Minimum Period (ns): 6.819 Path 7 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/TXDF_INST_reg_txdf_empty:D Delay (ns): 6.231 Slack (ns): 2.305 Arrival (ns): 11.480 Required (ns): 13.785 Setup (ns): 0.428 Minimum Period (ns): 6.786 Path 8 From: reg_q(10):CLK To: reg_q(24):E Delay (ns): 6.397 Slack (ns): 2.357 Arrival (ns): 11.463 Required (ns): 13.820 Setup (ns): 0.325 Minimum Period (ns): 6.734 Path 9 From: i_SIU/CMSIU_INST/reg_q(5):CLK To: i_SIU/CMSIU_INST/reg_q(20):D Delay (ns): 6.324 Slack (ns): 2.365 Arrival (ns): 11.450 Required (ns): 13.815 Setup (ns): 0.402 Minimum Period (ns): 6.726 Path 10 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_txd_sts2(3):D Delay (ns): 6.186 Slack (ns): 2.368 Arrival (ns): 11.435 Required (ns): 13.803 Setup (ns): 0.428 Minimum Period (ns): 6.723 Expanded Path 1 From: i_SIU/CMSIU_INST/reg_q(4):CLK To: i_SIU/CMSIU_INST/reg_q(18):D data required time 13.814 data arrival time - 11.777 slack 2.037 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 5.126 i_SIU/CMSIU_INST/reg_q(4):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.676 i_SIU/CMSIU_INST/reg_q(4):Q (f) + 0.397 net: i_SIU/CMSIU_INST/nx56256z3 6.073 i_SIU/CMSIU_INST/NOT_ix22081z24344:B (f) + 0.469 cell: ADLIB:NAND2 6.542 i_SIU/CMSIU_INST/NOT_ix22081z24344:Y (r) + 0.711 net: i_SIU/CMSIU_INST/nx22081z9 7.253 i_SIU/CMSIU_INST/ix22081z50935:A (r) + 0.509 cell: ADLIB:NAND3A 7.762 i_SIU/CMSIU_INST/ix22081z50935:Y (r) + 1.191 net: i_SIU/CMSIU_INST/nx22081z8 8.953 i_SIU/CMSIU_INST/NOT_ix22081z50934:B (r) + 0.453 cell: ADLIB:NAND3C 9.406 i_SIU/CMSIU_INST/NOT_ix22081z50934:Y (r) + 0.856 net: i_SIU/CMSIU_INST/nx22081z3 10.262 i_SIU/CMSIU_INST/NOT_ix25072z50933:C (r) + 0.479 cell: ADLIB:NAND3C 10.741 i_SIU/CMSIU_INST/NOT_ix25072z50933:Y (r) + 0.249 net: i_SIU/CMSIU_INST/nx25072z2 10.990 i_SIU/CMSIU_INST/ix25072z21032:B (r) + 0.546 cell: ADLIB:XA1A 11.536 i_SIU/CMSIU_INST/ix25072z21032:Y (f) + 0.241 net: i_SIU/CMSIU_INST/nx25072z1 11.777 i_SIU/CMSIU_INST/reg_q(18):D (f) 11.777 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.208 net: SIU_TXCLK_cb 14.216 i_SIU/CMSIU_INST/reg_q(18):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.814 i_SIU/CMSIU_INST/reg_q(18):D 13.814 data required time Expanded Path 2 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_txd_sts2(11):D data required time 13.747 data arrival time - 11.641 slack 2.106 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.332 net: SIU_TXCLK_cb 5.249 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) + 2.165 cell: ADLIB:FIFO4K18 7.414 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RD9 (r) + 1.486 net: i_SIU/s_txdf_q_27_ 8.900 i_SIU/FRAMING_INST/ix46636z49935:A (r) + 0.441 cell: ADLIB:NAND2A 9.341 i_SIU/FRAMING_INST/ix46636z49935:Y (r) + 0.249 net: i_SIU/FRAMING_INST/nx46636z3 9.590 i_SIU/FRAMING_INST/ix46636z14897:B (r) + 0.506 cell: ADLIB:MX2 10.096 i_SIU/FRAMING_INST/ix46636z14897:Y (r) + 0.910 net: i_SIU/FRAMING_INST/nx46636z2 11.006 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(11):B (r) + 0.386 cell: ADLIB:AND2 11.392 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(11):Y (r) + 0.249 net: i_SIU/FRAMING_INST/txd_sts2_2n22ss1_11_ 11.641 i_SIU/FRAMING_INST/reg_txd_sts2(11):D (r) 11.641 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.167 net: SIU_TXCLK_cb 14.175 i_SIU/FRAMING_INST/reg_txd_sts2(11):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 13.747 i_SIU/FRAMING_INST/reg_txd_sts2(11):D 13.747 data required time Expanded Path 3 From: i_SIU/CMSIU_INST/reg_q(5):CLK To: i_SIU/CMSIU_INST/reg_q(18):D data required time 13.814 data arrival time - 11.624 slack 2.190 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 5.126 i_SIU/CMSIU_INST/reg_q(5):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.676 i_SIU/CMSIU_INST/reg_q(5):Q (f) + 0.329 net: i_SIU/CMSIU_INST/nx22081z10 6.005 i_SIU/CMSIU_INST/NOT_ix22081z24344:A (f) + 0.384 cell: ADLIB:NAND2 6.389 i_SIU/CMSIU_INST/NOT_ix22081z24344:Y (r) + 0.711 net: i_SIU/CMSIU_INST/nx22081z9 7.100 i_SIU/CMSIU_INST/ix22081z50935:A (r) + 0.509 cell: ADLIB:NAND3A 7.609 i_SIU/CMSIU_INST/ix22081z50935:Y (r) + 1.191 net: i_SIU/CMSIU_INST/nx22081z8 8.800 i_SIU/CMSIU_INST/NOT_ix22081z50934:B (r) + 0.453 cell: ADLIB:NAND3C 9.253 i_SIU/CMSIU_INST/NOT_ix22081z50934:Y (r) + 0.856 net: i_SIU/CMSIU_INST/nx22081z3 10.109 i_SIU/CMSIU_INST/NOT_ix25072z50933:C (r) + 0.479 cell: ADLIB:NAND3C 10.588 i_SIU/CMSIU_INST/NOT_ix25072z50933:Y (r) + 0.249 net: i_SIU/CMSIU_INST/nx25072z2 10.837 i_SIU/CMSIU_INST/ix25072z21032:B (r) + 0.546 cell: ADLIB:XA1A 11.383 i_SIU/CMSIU_INST/ix25072z21032:Y (f) + 0.241 net: i_SIU/CMSIU_INST/nx25072z1 11.624 i_SIU/CMSIU_INST/reg_q(18):D (f) 11.624 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.208 net: SIU_TXCLK_cb 14.216 i_SIU/CMSIU_INST/reg_q(18):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.814 i_SIU/CMSIU_INST/reg_q(18):D 13.814 data required time Expanded Path 4 From: i_SIU/CMSIU_INST/reg_q(4):CLK To: i_SIU/CMSIU_INST/reg_q(20):D data required time 13.815 data arrival time - 11.603 slack 2.212 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 5.126 i_SIU/CMSIU_INST/reg_q(4):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.676 i_SIU/CMSIU_INST/reg_q(4):Q (f) + 0.397 net: i_SIU/CMSIU_INST/nx56256z3 6.073 i_SIU/CMSIU_INST/NOT_ix22081z24344:B (f) + 0.469 cell: ADLIB:NAND2 6.542 i_SIU/CMSIU_INST/NOT_ix22081z24344:Y (r) + 0.711 net: i_SIU/CMSIU_INST/nx22081z9 7.253 i_SIU/CMSIU_INST/ix22081z50935:A (r) + 0.509 cell: ADLIB:NAND3A 7.762 i_SIU/CMSIU_INST/ix22081z50935:Y (r) + 1.191 net: i_SIU/CMSIU_INST/nx22081z8 8.953 i_SIU/CMSIU_INST/NOT_ix22081z50934:B (r) + 0.453 cell: ADLIB:NAND3C 9.406 i_SIU/CMSIU_INST/NOT_ix22081z50934:Y (r) + 0.682 net: i_SIU/CMSIU_INST/nx22081z3 10.088 i_SIU/CMSIU_INST/NOT_ix28065z50933:C (r) + 0.479 cell: ADLIB:NAND3C 10.567 i_SIU/CMSIU_INST/NOT_ix28065z50933:Y (r) + 0.249 net: i_SIU/CMSIU_INST/nx28065z2 10.816 i_SIU/CMSIU_INST/ix28065z21032:B (r) + 0.546 cell: ADLIB:XA1A 11.362 i_SIU/CMSIU_INST/ix28065z21032:Y (f) + 0.241 net: i_SIU/CMSIU_INST/nx28065z1 11.603 i_SIU/CMSIU_INST/reg_q(20):D (f) 11.603 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 14.217 i_SIU/CMSIU_INST/reg_q(20):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.815 i_SIU/CMSIU_INST/reg_q(20):D 13.815 data required time Expanded Path 5 From: i_SIU/CMSIU_INST/reg_q(4):CLK To: i_SIU/CMSIU_INST/reg_q(16):D data required time 13.818 data arrival time - 11.561 slack 2.257 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 5.126 i_SIU/CMSIU_INST/reg_q(4):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.676 i_SIU/CMSIU_INST/reg_q(4):Q (f) + 0.397 net: i_SIU/CMSIU_INST/nx56256z3 6.073 i_SIU/CMSIU_INST/NOT_ix22081z24344:B (f) + 0.469 cell: ADLIB:NAND2 6.542 i_SIU/CMSIU_INST/NOT_ix22081z24344:Y (r) + 0.711 net: i_SIU/CMSIU_INST/nx22081z9 7.253 i_SIU/CMSIU_INST/ix22081z50935:A (r) + 0.509 cell: ADLIB:NAND3A 7.762 i_SIU/CMSIU_INST/ix22081z50935:Y (r) + 1.191 net: i_SIU/CMSIU_INST/nx22081z8 8.953 i_SIU/CMSIU_INST/NOT_ix22081z50934:B (r) + 0.453 cell: ADLIB:NAND3C 9.406 i_SIU/CMSIU_INST/NOT_ix22081z50934:Y (r) + 0.642 net: i_SIU/CMSIU_INST/nx22081z3 10.048 i_SIU/CMSIU_INST/NOT_ix23078z50931:A (r) + 0.479 cell: ADLIB:NAND3A 10.527 i_SIU/CMSIU_INST/NOT_ix23078z50931:Y (r) + 0.249 net: i_SIU/CMSIU_INST/nx23078z2 10.776 i_SIU/CMSIU_INST/ix23078z21032:B (r) + 0.546 cell: ADLIB:XA1A 11.322 i_SIU/CMSIU_INST/ix23078z21032:Y (f) + 0.239 net: i_SIU/CMSIU_INST/nx23078z1 11.561 i_SIU/CMSIU_INST/reg_q(16):D (f) 11.561 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.212 net: SIU_TXCLK_cb 14.220 i_SIU/CMSIU_INST/reg_q(16):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.818 i_SIU/CMSIU_INST/reg_q(16):D 13.818 data required time Expanded Path 6 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_s_crc_in(6):D data required time 13.829 data arrival time - 11.557 slack 2.272 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.332 net: SIU_TXCLK_cb 5.249 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) + 2.165 cell: ADLIB:FIFO4K18 7.414 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RD4 (r) + 1.574 net: i_SIU/s_txdf_q_22_ 8.988 i_SIU/FRAMING_INST/txdf_q16_2n22ss1(6):B (r) + 0.506 cell: ADLIB:MX2 9.494 i_SIU/FRAMING_INST/txdf_q16_2n22ss1(6):Y (r) + 1.377 net: i_SIU/FRAMING_INST/txdf_q16_2n22ss1_6_ 10.871 i_SIU/FRAMING_INST/ix23196z14896:B (r) + 0.437 cell: ADLIB:MX2 11.308 i_SIU/FRAMING_INST/ix23196z14896:Y (r) + 0.249 net: i_SIU/FRAMING_INST/nx23196z1 11.557 i_SIU/FRAMING_INST/reg_s_crc_in(6):D (r) 11.557 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.223 net: SIU_TXCLK_cb 14.231 i_SIU/FRAMING_INST/reg_s_crc_in(6):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.829 i_SIU/FRAMING_INST/reg_s_crc_in(6):D 13.829 data required time Expanded Path 7 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/TXDF_INST_reg_txdf_empty:D data required time 13.785 data arrival time - 11.480 slack 2.305 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.332 net: SIU_TXCLK_cb 5.249 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) + 1.717 cell: ADLIB:FIFO4K18 6.966 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:EMPTY (r) + 1.100 net: i_SIU/TXDF_INST_TXDF_CORE_INST_EMPTY_1 8.066 i_SIU/TXDF_INST_txdf_e_i:A (r) + 0.348 cell: ADLIB:NAND2B 8.414 i_SIU/TXDF_INST_txdf_e_i:Y (r) + 0.881 net: i_SIU/TXDF_INST_txdf_e_i 9.295 i_SIU/ix14207z40557:B (r) + 0.414 cell: ADLIB:AO1B 9.709 i_SIU/ix14207z40557:Y (r) + 0.314 net: i_SIU/nx14207z2 10.023 i_SIU/NOT_TXDF_INST_ix44315z40560:C (r) + 0.572 cell: ADLIB:AO1E 10.595 i_SIU/NOT_TXDF_INST_ix44315z40560:Y (f) + 0.246 net: i_SIU/nx44315z2 10.841 i_SIU/ix44315z14896:S (f) + 0.388 cell: ADLIB:MX2 11.229 i_SIU/ix44315z14896:Y (f) + 0.251 net: i_SIU/nx44315z1 11.480 i_SIU/TXDF_INST_reg_txdf_empty:D (f) 11.480 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.205 net: SIU_TXCLK_cb 14.213 i_SIU/TXDF_INST_reg_txdf_empty:CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 13.785 i_SIU/TXDF_INST_reg_txdf_empty:D 13.785 data required time Expanded Path 8 From: reg_q(10):CLK To: reg_q(24):E data required time 13.820 data arrival time - 11.463 slack 2.357 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.149 net: SIU_TXCLK_cb 5.066 reg_q(10):CLK (r) + 0.550 cell: ADLIB:DFN1E1 5.616 reg_q(10):Q (f) + 0.801 net: nx18093z4 6.417 ix18093z24339:C (f) + 0.509 cell: ADLIB:NAND3 6.926 ix18093z24339:Y (r) + 0.524 net: nx18093z3 7.450 ix24075z50935:C (r) + 0.479 cell: ADLIB:NAND3C 7.929 ix24075z50935:Y (r) + 0.947 net: nx24075z4 8.876 NOT_ix24075z50934:A (r) + 0.347 cell: ADLIB:NAND3C 9.223 NOT_ix24075z50934:Y (r) + 1.621 net: nx24075z3 10.844 ix32053z40560:A (r) + 0.375 cell: ADLIB:AO1E 11.219 ix32053z40560:Y (f) + 0.244 net: nx32053z2 11.463 reg_q(24):E (f) 11.463 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.137 net: SIU_TXCLK_cb 14.145 reg_q(24):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 13.820 reg_q(24):E 13.820 data required time Expanded Path 9 From: i_SIU/CMSIU_INST/reg_q(5):CLK To: i_SIU/CMSIU_INST/reg_q(20):D data required time 13.815 data arrival time - 11.450 slack 2.365 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 5.126 i_SIU/CMSIU_INST/reg_q(5):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.676 i_SIU/CMSIU_INST/reg_q(5):Q (f) + 0.329 net: i_SIU/CMSIU_INST/nx22081z10 6.005 i_SIU/CMSIU_INST/NOT_ix22081z24344:A (f) + 0.384 cell: ADLIB:NAND2 6.389 i_SIU/CMSIU_INST/NOT_ix22081z24344:Y (r) + 0.711 net: i_SIU/CMSIU_INST/nx22081z9 7.100 i_SIU/CMSIU_INST/ix22081z50935:A (r) + 0.509 cell: ADLIB:NAND3A 7.609 i_SIU/CMSIU_INST/ix22081z50935:Y (r) + 1.191 net: i_SIU/CMSIU_INST/nx22081z8 8.800 i_SIU/CMSIU_INST/NOT_ix22081z50934:B (r) + 0.453 cell: ADLIB:NAND3C 9.253 i_SIU/CMSIU_INST/NOT_ix22081z50934:Y (r) + 0.682 net: i_SIU/CMSIU_INST/nx22081z3 9.935 i_SIU/CMSIU_INST/NOT_ix28065z50933:C (r) + 0.479 cell: ADLIB:NAND3C 10.414 i_SIU/CMSIU_INST/NOT_ix28065z50933:Y (r) + 0.249 net: i_SIU/CMSIU_INST/nx28065z2 10.663 i_SIU/CMSIU_INST/ix28065z21032:B (r) + 0.546 cell: ADLIB:XA1A 11.209 i_SIU/CMSIU_INST/ix28065z21032:Y (f) + 0.241 net: i_SIU/CMSIU_INST/nx28065z1 11.450 i_SIU/CMSIU_INST/reg_q(20):D (f) 11.450 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.209 net: SIU_TXCLK_cb 14.217 i_SIU/CMSIU_INST/reg_q(20):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.815 i_SIU/CMSIU_INST/reg_q(20):D 13.815 data required time Expanded Path 10 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_txd_sts2(3):D data required time 13.803 data arrival time - 11.435 slack 2.368 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.332 net: SIU_TXCLK_cb 5.249 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) + 2.165 cell: ADLIB:FIFO4K18 7.414 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RD1 (r) + 1.280 net: i_SIU/s_txdf_q_19_ 8.694 i_SIU/FRAMING_INST/ix2953z49934:A (r) + 0.441 cell: ADLIB:NAND2A 9.135 i_SIU/FRAMING_INST/ix2953z49934:Y (r) + 0.249 net: i_SIU/FRAMING_INST/nx2953z2 9.384 i_SIU/FRAMING_INST/ix2953z14896:B (r) + 0.506 cell: ADLIB:MX2 9.890 i_SIU/FRAMING_INST/ix2953z14896:Y (r) + 0.910 net: i_SIU/FRAMING_INST/nx2953z1 10.800 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(3):B (r) + 0.386 cell: ADLIB:AND2 11.186 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(3):Y (r) + 0.249 net: i_SIU/FRAMING_INST/txd_sts2_2n22ss1_3_ 11.435 i_SIU/FRAMING_INST/reg_txd_sts2(3):D (r) 11.435 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.223 net: SIU_TXCLK_cb 14.231 i_SIU/FRAMING_INST/reg_txd_sts2(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 13.803 i_SIU/FRAMING_INST/reg_txd_sts2(3):D 13.803 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: PUSHB To: reg_q(23):E Delay (ns): 13.731 Slack (ns): Arrival (ns): 13.731 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.999 Path 2 From: PUSHB To: reg_q(24):E Delay (ns): 13.649 Slack (ns): Arrival (ns): 13.649 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.920 Path 3 From: PUSHB To: reg_q(20):E Delay (ns): 13.635 Slack (ns): Arrival (ns): 13.635 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.890 Path 4 From: PUSHB To: reg_q(18):E Delay (ns): 13.446 Slack (ns): Arrival (ns): 13.446 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.714 Path 5 From: PUSHB To: reg_q(21):E Delay (ns): 13.446 Slack (ns): Arrival (ns): 13.446 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.701 Path 6 From: PUSHB To: reg_q(25):E Delay (ns): 13.239 Slack (ns): Arrival (ns): 13.239 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.510 Path 7 From: PUSHB To: reg_q(22):E Delay (ns): 13.205 Slack (ns): Arrival (ns): 13.205 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.460 Path 8 From: PUSHB To: reg_q(19):E Delay (ns): 12.912 Slack (ns): Arrival (ns): 12.912 Required (ns): Setup (ns): 0.325 External Setup (ns): 8.180 Path 9 From: PUSHB To: reg_q(17):E Delay (ns): 12.647 Slack (ns): Arrival (ns): 12.647 Required (ns): Setup (ns): 0.325 External Setup (ns): 7.902 Path 10 From: PUSHB To: reg_q(26):E Delay (ns): 11.805 Slack (ns): Arrival (ns): 11.805 Required (ns): Setup (ns): 0.325 External Setup (ns): 7.073 Expanded Path 1 From: PUSHB To: reg_q(23):E data required time N/C data arrival time - 13.731 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.885 net: nx21420z1 12.929 ix31056z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.501 ix31056z40560:Y (f) + 0.230 net: nx31056z2 13.731 reg_q(23):E (f) 13.731 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.140 net: SIU_TXCLK_cb N/C reg_q(23):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(23):E Expanded Path 2 From: PUSHB To: reg_q(24):E data required time N/C data arrival time - 13.649 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.789 net: nx21420z1 12.833 ix32053z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.405 ix32053z40560:Y (f) + 0.244 net: nx32053z2 13.649 reg_q(24):E (f) 13.649 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.137 net: SIU_TXCLK_cb N/C reg_q(24):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(24):E Expanded Path 3 From: PUSHB To: reg_q(20):E data required time N/C data arrival time - 13.635 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.789 net: nx21420z1 12.833 ix28065z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.405 ix28065z40560:Y (f) + 0.230 net: nx28065z2 13.635 reg_q(20):E (f) 13.635 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.153 net: SIU_TXCLK_cb N/C reg_q(20):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(20):E Expanded Path 4 From: PUSHB To: reg_q(18):E data required time N/C data arrival time - 13.446 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.600 net: nx21420z1 12.644 ix25072z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.216 ix25072z40560:Y (f) + 0.230 net: nx25072z2 13.446 reg_q(18):E (f) 13.446 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.140 net: SIU_TXCLK_cb N/C reg_q(18):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(18):E Expanded Path 5 From: PUSHB To: reg_q(21):E data required time N/C data arrival time - 13.446 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.600 net: nx21420z1 12.644 ix29062z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.216 ix29062z40560:Y (f) + 0.230 net: nx29062z2 13.446 reg_q(21):E (f) 13.446 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.153 net: SIU_TXCLK_cb N/C reg_q(21):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(21):E Expanded Path 6 From: PUSHB To: reg_q(25):E data required time N/C data arrival time - 13.239 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.380 net: nx21420z1 12.424 ix33050z40560:C (r) + 0.572 cell: ADLIB:AO1E 12.996 ix33050z40560:Y (f) + 0.243 net: nx33050z2 13.239 reg_q(25):E (f) 13.239 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.137 net: SIU_TXCLK_cb N/C reg_q(25):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(25):E Expanded Path 7 From: PUSHB To: reg_q(22):E data required time N/C data arrival time - 13.205 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.359 net: nx21420z1 12.403 ix30059z40560:C (r) + 0.572 cell: ADLIB:AO1E 12.975 ix30059z40560:Y (f) + 0.230 net: nx30059z2 13.205 reg_q(22):E (f) 13.205 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.153 net: SIU_TXCLK_cb N/C reg_q(22):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(22):E Expanded Path 8 From: PUSHB To: reg_q(19):E data required time N/C data arrival time - 12.912 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 4.066 net: nx21420z1 12.110 ix26069z40560:C (r) + 0.572 cell: ADLIB:AO1E 12.682 ix26069z40560:Y (f) + 0.230 net: nx26069z2 12.912 reg_q(19):E (f) 12.912 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.140 net: SIU_TXCLK_cb N/C reg_q(19):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(19):E Expanded Path 9 From: PUSHB To: reg_q(17):E data required time N/C data arrival time - 12.647 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 3.801 net: nx21420z1 11.845 ix24075z40558:C (r) + 0.572 cell: ADLIB:AO1C 12.417 ix24075z40558:Y (f) + 0.230 net: nx24075z2 12.647 reg_q(17):E (f) 12.647 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.153 net: SIU_TXCLK_cb N/C reg_q(17):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(17):E Expanded Path 10 From: PUSHB To: reg_q(26):E data required time N/C data arrival time - 11.805 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.493 net: PUSHB_i 7.603 NOT_ix21420z48514:B (r) + 0.441 cell: ADLIB:AND2 8.044 NOT_ix21420z48514:Y (r) + 2.959 net: nx21420z1 11.003 ix34047z40560:C (r) + 0.572 cell: ADLIB:AO1E 11.575 ix34047z40560:Y (f) + 0.230 net: nx34047z2 11.805 reg_q(26):E (f) 11.805 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.140 net: SIU_TXCLK_cb N/C reg_q(26):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(26):E END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SFP_TX_DIS Delay (ns): 11.291 Slack (ns): Arrival (ns): 16.454 Required (ns): Clock to Out (ns): 16.454 Path 2 From: i_SIU/INST_PMIF/reg_pm_clk:CLK To: SFPP_SCLK Delay (ns): 11.314 Slack (ns): Arrival (ns): 16.404 Required (ns): Clock to Out (ns): 16.404 Path 3 From: reg_q(26):CLK To: LED_SIU(1) Delay (ns): 11.156 Slack (ns): Arrival (ns): 16.213 Required (ns): Clock to Out (ns): 16.213 Path 4 From: reg_q(25):CLK To: LED_SIU(2) Delay (ns): 11.097 Slack (ns): Arrival (ns): 16.151 Required (ns): Clock to Out (ns): 16.151 Path 5 From: i_SIU/INST_PMIF/reg_pm_ncs:CLK To: SFPP_SCSn Delay (ns): 10.591 Slack (ns): Arrival (ns): 15.681 Required (ns): Clock to Out (ns): 15.681 Path 6 From: i_SIU/LMSIU_INST/reg_sd_prbsen:CLK To: SIU_PRBSEN Delay (ns): 9.282 Slack (ns): Arrival (ns): 14.445 Required (ns): Clock to Out (ns): 14.445 Path 7 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SIU_ENABLE Delay (ns): 9.279 Slack (ns): Arrival (ns): 14.442 Required (ns): Clock to Out (ns): 14.442 Path 8 From: addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(13) Delay (ns): 3.007 Slack (ns): Arrival (ns): 8.243 Required (ns): Clock to Out (ns): 8.243 Path 9 From: addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(14) Delay (ns): 3.007 Slack (ns): Arrival (ns): 8.243 Required (ns): Clock to Out (ns): 8.243 Path 10 From: addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(15) Delay (ns): 3.007 Slack (ns): Arrival (ns): 8.243 Required (ns): Clock to Out (ns): 8.243 Expanded Path 1 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SFP_TX_DIS data required time N/C data arrival time - 16.454 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.246 net: SIU_TXCLK_cb 5.163 i_SIU/LMSIU_INST/reg_ot_lon:CLK (r) + 0.434 cell: ADLIB:DFN1P0 5.597 i_SIU/LMSIU_INST/reg_ot_lon:Q (r) + 3.201 net: SIU_ENABLE_i 8.798 i_SIU/ot_td:A (r) + 0.348 cell: ADLIB:INV 9.146 i_SIU/ot_td:Y (f) + 2.317 net: SFP_TX_DIS_i 11.463 obuf_SFP_TX_DIS_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 11.955 obuf_SFP_TX_DIS_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SFP_TX_DIS_U1/U0/NET1 11.955 obuf_SFP_TX_DIS_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 16.454 obuf_SFP_TX_DIS_U1/U0/U0:PAD (f) + 0.000 net: SFP_TX_DIS 16.454 SFP_TX_DIS (f) 16.454 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SFP_TX_DIS (f) Expanded Path 2 From: i_SIU/INST_PMIF/reg_pm_clk:CLK To: SFPP_SCLK data required time N/C data arrival time - 16.404 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.173 net: SIU_TXCLK_cb 5.090 i_SIU/INST_PMIF/reg_pm_clk:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.640 i_SIU/INST_PMIF/reg_pm_clk:Q (f) + 5.830 net: SFPP_SCLK_i 11.470 obuf_SFPP_SCLK_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 11.905 obuf_SFPP_SCLK_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SFPP_SCLK_U1/U0/NET1 11.905 obuf_SFPP_SCLK_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 16.404 obuf_SFPP_SCLK_U1/U0/U0:PAD (f) + 0.000 net: SFPP_SCLK 16.404 SFPP_SCLK (f) 16.404 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SFPP_SCLK (f) Expanded Path 3 From: reg_q(26):CLK To: LED_SIU(1) data required time N/C data arrival time - 16.213 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.140 net: SIU_TXCLK_cb 5.057 reg_q(26):CLK (r) + 0.550 cell: ADLIB:DFN1E1 5.607 reg_q(26):Q (f) + 5.113 net: led_cnt_26_ 10.720 genblk4[1].leds_cnt_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 11.155 genblk4[1].leds_cnt_U1/U0/U1:DOUT (f) + 0.000 net: genblk4[1]_leds_cnt_U1/U0/NET1 11.155 genblk4[1].leds_cnt_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 16.213 genblk4[1].leds_cnt_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_1_ 16.213 LED_SIU(1) (f) 16.213 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C LED_SIU(1) (f) Expanded Path 4 From: reg_q(25):CLK To: LED_SIU(2) data required time N/C data arrival time - 16.151 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.137 net: SIU_TXCLK_cb 5.054 reg_q(25):CLK (r) + 0.550 cell: ADLIB:DFN1E1 5.604 reg_q(25):Q (f) + 5.054 net: led_cnt_25_ 10.658 genblk4[2].leds_cnt_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 11.093 genblk4[2].leds_cnt_U1/U0/U1:DOUT (f) + 0.000 net: genblk4[2]_leds_cnt_U1/U0/NET1 11.093 genblk4[2].leds_cnt_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 16.151 genblk4[2].leds_cnt_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_2_ 16.151 LED_SIU(2) (f) 16.151 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C LED_SIU(2) (f) Expanded Path 5 From: i_SIU/INST_PMIF/reg_pm_ncs:CLK To: SFPP_SCSn data required time N/C data arrival time - 15.681 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.173 net: SIU_TXCLK_cb 5.090 i_SIU/INST_PMIF/reg_pm_ncs:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.640 i_SIU/INST_PMIF/reg_pm_ncs:Q (f) + 5.107 net: SFPP_SCSn_i 10.747 obuf_SFPP_SCSn_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 11.182 obuf_SFPP_SCSn_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SFPP_SCSn_U1/U0/NET1 11.182 obuf_SFPP_SCSn_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 15.681 obuf_SFPP_SCSn_U1/U0/U0:PAD (f) + 0.000 net: SFPP_SCSn 15.681 SFPP_SCSn (f) 15.681 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SFPP_SCSn (f) Expanded Path 6 From: i_SIU/LMSIU_INST/reg_sd_prbsen:CLK To: SIU_PRBSEN data required time N/C data arrival time - 14.445 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.246 net: SIU_TXCLK_cb 5.163 i_SIU/LMSIU_INST/reg_sd_prbsen:CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.713 i_SIU/LMSIU_INST/reg_sd_prbsen:Q (f) + 3.182 net: SIU_PRBSEN_i 8.895 obuf_SIU_PRBSEN_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 9.387 obuf_SIU_PRBSEN_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SIU_PRBSEN_U1/U0/NET1 9.387 obuf_SIU_PRBSEN_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 14.445 obuf_SIU_PRBSEN_U1/U0/U0:PAD (f) + 0.000 net: SIU_PRBSEN 14.445 SIU_PRBSEN (f) 14.445 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_PRBSEN (f) Expanded Path 7 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SIU_ENABLE data required time N/C data arrival time - 14.442 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.246 net: SIU_TXCLK_cb 5.163 i_SIU/LMSIU_INST/reg_ot_lon:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.713 i_SIU/LMSIU_INST/reg_ot_lon:Q (f) + 3.236 net: SIU_ENABLE_i 8.949 obuf_SIU_ENABLE_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 9.384 obuf_SIU_ENABLE_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SIU_ENABLE_U1/U0/NET1 9.384 obuf_SIU_ENABLE_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 14.442 obuf_SIU_ENABLE_U1/U0/U0:PAD (f) + 0.000 net: SIU_ENABLE 14.442 SIU_ENABLE (f) 14.442 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_ENABLE (f) Expanded Path 8 From: addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(13) data required time N/C data arrival time - 8.243 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.319 net: SIU_TXCLK_cb 5.236 addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.572 cell: ADLIB:IOTRI_ORC_EB 5.808 addds[13].obuf_SIU_TXD_U1/U0/U1:DOUT (f) + 0.000 net: addds[13]_obuf_SIU_TXD_U1/U0/NET1 5.808 addds[13].obuf_SIU_TXD_U1/U0/U0:D (f) + 2.435 cell: ADLIB:IOPAD_TRI 8.243 addds[13].obuf_SIU_TXD_U1/U0/U0:PAD (f) + 0.000 net: SIU_TXD_13_ 8.243 SIU_TXD(13) (f) 8.243 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(13) (f) Expanded Path 9 From: addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(14) data required time N/C data arrival time - 8.243 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.319 net: SIU_TXCLK_cb 5.236 addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.572 cell: ADLIB:IOTRI_ORC_EB 5.808 addds[14].obuf_SIU_TXD_U1/U0/U1:DOUT (f) + 0.000 net: addds[14]_obuf_SIU_TXD_U1/U0/NET1 5.808 addds[14].obuf_SIU_TXD_U1/U0/U0:D (f) + 2.435 cell: ADLIB:IOPAD_TRI 8.243 addds[14].obuf_SIU_TXD_U1/U0/U0:PAD (f) + 0.000 net: SIU_TXD_14_ 8.243 SIU_TXD(14) (f) 8.243 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(14) (f) Expanded Path 10 From: addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(15) data required time N/C data arrival time - 8.243 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.319 net: SIU_TXCLK_cb 5.236 addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.572 cell: ADLIB:IOTRI_ORC_EB 5.808 addds[15].obuf_SIU_TXD_U1/U0/U1:DOUT (f) + 0.000 net: addds[15]_obuf_SIU_TXD_U1/U0/NET1 5.808 addds[15].obuf_SIU_TXD_U1/U0/U0:D (f) + 2.435 cell: ADLIB:IOPAD_TRI 8.243 addds[15].obuf_SIU_TXD_U1/U0/U0:PAD (f) + 0.000 net: SIU_TXD_15_ 8.243 SIU_TXD(15) (f) 8.243 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(15) (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(0):CLR Delay (ns): 7.171 Slack (ns): 1.574 Arrival (ns): 12.385 Required (ns): 13.959 Recovery (ns): 0.222 Minimum Period (ns): 7.517 Skew (ns): 0.124 Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(12):CLR Delay (ns): 7.001 Slack (ns): 1.744 Arrival (ns): 12.215 Required (ns): 13.959 Recovery (ns): 0.222 Minimum Period (ns): 7.347 Skew (ns): 0.124 Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1):CLR Delay (ns): 7.001 Slack (ns): 1.744 Arrival (ns): 12.215 Required (ns): 13.959 Recovery (ns): 0.222 Minimum Period (ns): 7.347 Skew (ns): 0.124 Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_i2c_addr(4):CLR Delay (ns): 6.974 Slack (ns): 1.765 Arrival (ns): 12.188 Required (ns): 13.953 Recovery (ns): 0.222 Minimum Period (ns): 7.326 Skew (ns): 0.130 Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sfrm(3):CLR Delay (ns): 7.029 Slack (ns): 1.835 Arrival (ns): 12.243 Required (ns): 14.078 Recovery (ns): 0.222 Minimum Period (ns): 7.256 Skew (ns): 0.005 Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/reg_tx_clk_2:CLR Delay (ns): 6.845 Slack (ns): 1.864 Arrival (ns): 12.059 Required (ns): 13.923 Recovery (ns): 0.222 Minimum Period (ns): 7.227 Skew (ns): 0.160 Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_pmvstw(13):CLR Delay (ns): 6.798 Slack (ns): 1.945 Arrival (ns): 12.012 Required (ns): 13.957 Recovery (ns): 0.222 Minimum Period (ns): 7.146 Skew (ns): 0.126 Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_q(1):CLR Delay (ns): 6.715 Slack (ns): 2.024 Arrival (ns): 11.929 Required (ns): 13.953 Recovery (ns): 0.222 Minimum Period (ns): 7.067 Skew (ns): 0.130 Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_txst_d1(8):CLR Delay (ns): 6.778 Slack (ns): 2.034 Arrival (ns): 11.992 Required (ns): 14.026 Recovery (ns): 0.222 Minimum Period (ns): 7.057 Skew (ns): 0.057 Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(6):CLR Delay (ns): 6.707 Slack (ns): 2.038 Arrival (ns): 11.921 Required (ns): 13.959 Recovery (ns): 0.222 Minimum Period (ns): 7.053 Skew (ns): 0.124 Expanded Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(0):CLR data required time 13.959 data arrival time - 12.385 slack 1.574 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.737 net: i_SIU/s_arstn 12.385 i_SIU/INST_PMIF/reg_pm_value_int(0):CLR (r) 12.385 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.173 net: SIU_TXCLK_cb 14.181 i_SIU/INST_PMIF/reg_pm_value_int(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.959 i_SIU/INST_PMIF/reg_pm_value_int(0):CLR 13.959 data required time Expanded Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(12):CLR data required time 13.959 data arrival time - 12.215 slack 1.744 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.567 net: i_SIU/s_arstn 12.215 i_SIU/INST_PMIF/reg_pm_value_int(12):CLR (r) 12.215 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.173 net: SIU_TXCLK_cb 14.181 i_SIU/INST_PMIF/reg_pm_value_int(12):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.959 i_SIU/INST_PMIF/reg_pm_value_int(12):CLR 13.959 data required time Expanded Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1):CLR data required time 13.959 data arrival time - 12.215 slack 1.744 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.567 net: i_SIU/s_arstn 12.215 i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1):CLR (r) 12.215 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.173 net: SIU_TXCLK_cb 14.181 i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.959 i_SIU/INST_PMIF/modgen_counter_bit_cnt_reg_q(1):CLR 13.959 data required time Expanded Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_i2c_addr(4):CLR data required time 13.953 data arrival time - 12.188 slack 1.765 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.540 net: i_SIU/s_arstn 12.188 i_SIU/CMSIU_INST/reg_v_i2c_addr(4):CLR (r) 12.188 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.167 net: SIU_TXCLK_cb 14.175 i_SIU/CMSIU_INST/reg_v_i2c_addr(4):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.953 i_SIU/CMSIU_INST/reg_v_i2c_addr(4):CLR 13.953 data required time Expanded Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sfrm(3):CLR data required time 14.078 data arrival time - 12.243 slack 1.835 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.595 net: i_SIU/s_arstn 12.243 i_SIU/FRAMING_INST/reg_txd_sfrm(3):CLR (r) 12.243 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.292 net: SIU_TXCLK_cb 14.300 i_SIU/FRAMING_INST/reg_txd_sfrm(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 14.078 i_SIU/FRAMING_INST/reg_txd_sfrm(3):CLR 14.078 data required time Expanded Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/reg_tx_clk_2:CLR data required time 13.923 data arrival time - 12.059 slack 1.864 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.411 net: i_SIU/s_arstn 12.059 i_SIU/reg_tx_clk_2:CLR (r) 12.059 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.137 net: SIU_TXCLK_cb 14.145 i_SIU/reg_tx_clk_2:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.923 i_SIU/reg_tx_clk_2:CLR 13.923 data required time Expanded Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_pmvstw(13):CLR data required time 13.957 data arrival time - 12.012 slack 1.945 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.364 net: i_SIU/s_arstn 12.012 i_SIU/CMSIU_INST/reg_v_pmvstw(13):CLR (r) 12.012 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.171 net: SIU_TXCLK_cb 14.179 i_SIU/CMSIU_INST/reg_v_pmvstw(13):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.957 i_SIU/CMSIU_INST/reg_v_pmvstw(13):CLR 13.957 data required time Expanded Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_q(1):CLR data required time 13.953 data arrival time - 11.929 slack 2.024 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.281 net: i_SIU/s_arstn 11.929 i_SIU/FRAMING_INST/reg_q(1):CLR (r) 11.929 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.167 net: SIU_TXCLK_cb 14.175 i_SIU/FRAMING_INST/reg_q(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.953 i_SIU/FRAMING_INST/reg_q(1):CLR 13.953 data required time Expanded Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/CMSIU_INST/reg_v_txst_d1(8):CLR data required time 14.026 data arrival time - 11.992 slack 2.034 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.344 net: i_SIU/s_arstn 11.992 i_SIU/CMSIU_INST/reg_v_txst_d1(8):CLR (r) 11.992 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.240 net: SIU_TXCLK_cb 14.248 i_SIU/CMSIU_INST/reg_v_txst_d1(8):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 14.026 i_SIU/CMSIU_INST/reg_v_txst_d1(8):CLR 14.026 data required time Expanded Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(6):CLR data required time 13.959 data arrival time - 11.921 slack 2.038 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 3.359 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.917 cbuf_SIU_TXCLK:Y (r) + 1.297 net: SIU_TXCLK_cb 5.214 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 5.648 i_SIU/reg_s_arstn:Q (r) + 6.273 net: i_SIU/s_arstn 11.921 i_SIU/INST_PMIF/reg_pm_value_int(6):CLR (r) 11.921 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i 12.450 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 13.008 cbuf_SIU_TXCLK:Y (r) + 1.173 net: SIU_TXCLK_cb 14.181 i_SIU/INST_PMIF/reg_pm_value_int(6):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.959 i_SIU/INST_PMIF/reg_pm_value_int(6):CLR 13.959 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: addds[2].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 17.823 Slack (ns): Arrival (ns): 17.823 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 12.986 Path 2 From: PUSHB To: addds[0].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 17.823 Slack (ns): Arrival (ns): 17.823 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 12.982 Path 3 From: PUSHB To: addds[1].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 16.929 Slack (ns): Arrival (ns): 16.929 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 12.088 Path 4 From: PUSHB To: addds[13].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 17.084 Slack (ns): Arrival (ns): 17.084 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 12.070 Path 5 From: PUSHB To: addds[15].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 17.084 Slack (ns): Arrival (ns): 17.084 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 12.070 Path 6 From: PUSHB To: addds[3].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 16.607 Slack (ns): Arrival (ns): 16.607 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.769 Path 7 From: PUSHB To: addds[4].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 16.521 Slack (ns): Arrival (ns): 16.521 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.680 Path 8 From: PUSHB To: addds[9].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 16.460 Slack (ns): Arrival (ns): 16.460 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.624 Path 9 From: PUSHB To: addds[10].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 16.460 Slack (ns): Arrival (ns): 16.460 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.623 Path 10 From: PUSHB To: addds[5].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 16.235 Slack (ns): Arrival (ns): 16.235 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.394 Expanded Path 1 From: PUSHB To: addds[2].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 17.823 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 9.399 net: not_rst_n 17.823 addds[2].obuf_SIU_TXD_U1/U0/U1:CLR (f) 17.823 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.142 net: SIU_TXCLK_cb N/C addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[2].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 2 From: PUSHB To: addds[0].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 17.823 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 9.399 net: not_rst_n 17.823 addds[0].obuf_SIU_TXD_U1/U0/U1:CLR (f) 17.823 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.146 net: SIU_TXCLK_cb N/C addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[0].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 3 From: PUSHB To: addds[1].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 16.929 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.505 net: not_rst_n 16.929 addds[1].obuf_SIU_TXD_U1/U0/U1:CLR (f) 16.929 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.146 net: SIU_TXCLK_cb N/C addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[1].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 4 From: PUSHB To: addds[13].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 17.084 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.660 net: not_rst_n 17.084 addds[13].obuf_SIU_TXD_U1/U0/U1:CLR (f) 17.084 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.319 net: SIU_TXCLK_cb N/C addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[13].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 5 From: PUSHB To: addds[15].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 17.084 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.660 net: not_rst_n 17.084 addds[15].obuf_SIU_TXD_U1/U0/U1:CLR (f) 17.084 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.319 net: SIU_TXCLK_cb N/C addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[15].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 6 From: PUSHB To: addds[3].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 16.607 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.183 net: not_rst_n 16.607 addds[3].obuf_SIU_TXD_U1/U0/U1:CLR (f) 16.607 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.143 net: SIU_TXCLK_cb N/C addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[3].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 7 From: PUSHB To: addds[4].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 16.521 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.097 net: not_rst_n 16.521 addds[4].obuf_SIU_TXD_U1/U0/U1:CLR (f) 16.521 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.146 net: SIU_TXCLK_cb N/C addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[4].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 8 From: PUSHB To: addds[9].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 16.460 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.036 net: not_rst_n 16.460 addds[9].obuf_SIU_TXD_U1/U0/U1:CLR (f) 16.460 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.141 net: SIU_TXCLK_cb N/C addds[9].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[9].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 9 From: PUSHB To: addds[10].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 16.460 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.036 net: not_rst_n 16.460 addds[10].obuf_SIU_TXD_U1/U0/U1:CLR (f) 16.460 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.142 net: SIU_TXCLK_cb N/C addds[10].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[10].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 10 From: PUSHB To: addds[5].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 16.235 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 7.811 net: not_rst_n 16.235 addds[5].obuf_SIU_TXD_U1/U0/U1:CLR (f) 16.235 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 2.198 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 1.146 net: SIU_TXCLK_cb N/C addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[5].obuf_SIU_TXD_U1/U0/U1:CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_SIU/reg_tx_clk_2:Q SET Register to Register Path 1 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D Delay (ns): 7.835 Slack (ns): 9.893 Arrival (ns): 12.976 Required (ns): 22.869 Setup (ns): 0.428 Minimum Period (ns): 8.289 Path 2 From: i_SIU/I2CIF_INST/reg_bit_count(1):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D Delay (ns): 6.987 Slack (ns): 10.741 Arrival (ns): 12.128 Required (ns): 22.869 Setup (ns): 0.428 Minimum Period (ns): 7.441 Path 3 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(11):D Delay (ns): 6.911 Slack (ns): 10.833 Arrival (ns): 12.052 Required (ns): 22.885 Setup (ns): 0.428 Minimum Period (ns): 7.349 Path 4 From: i_SIU/I2CIF_INST/reg_q(8):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(11):D Delay (ns): 6.909 Slack (ns): 10.849 Arrival (ns): 12.036 Required (ns): 22.885 Setup (ns): 0.428 Minimum Period (ns): 7.333 Path 5 From: i_SIU/I2CIF_INST/reg_bit_count(2):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D Delay (ns): 6.836 Slack (ns): 10.892 Arrival (ns): 11.977 Required (ns): 22.869 Setup (ns): 0.428 Minimum Period (ns): 7.290 Path 6 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D Delay (ns): 6.825 Slack (ns): 10.929 Arrival (ns): 11.966 Required (ns): 22.895 Setup (ns): 0.428 Minimum Period (ns): 7.253 Path 7 From: i_SIU/I2CIF_INST/reg_q(8):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D Delay (ns): 6.823 Slack (ns): 10.945 Arrival (ns): 11.950 Required (ns): 22.895 Setup (ns): 0.428 Minimum Period (ns): 7.237 Path 8 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(2):D Delay (ns): 6.706 Slack (ns): 11.039 Arrival (ns): 11.847 Required (ns): 22.886 Setup (ns): 0.428 Minimum Period (ns): 7.143 Path 9 From: i_SIU/I2CIF_INST/reg_bit_count(1):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(11):D Delay (ns): 6.681 Slack (ns): 11.063 Arrival (ns): 11.822 Required (ns): 22.885 Setup (ns): 0.428 Minimum Period (ns): 7.119 Path 10 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(10):D Delay (ns): 6.669 Slack (ns): 11.101 Arrival (ns): 11.810 Required (ns): 22.911 Setup (ns): 0.402 Minimum Period (ns): 7.081 Expanded Path 1 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D data required time 22.869 data arrival time - 12.976 slack 9.893 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.575 i_SIU/I2CIF_INST/reg_bit_count(0):Q (r) + 2.868 net: i_SIU/I2CIF_INST/bit_count_0_ 8.443 i_SIU/I2CIF_INST/ix7293z14903:S (r) + 0.278 cell: ADLIB:MX2 8.721 i_SIU/I2CIF_INST/ix7293z14903:Y (f) + 0.810 net: i_SIU/I2CIF_INST/nx7293z8 9.531 i_SIU/I2CIF_INST/ix7293z50936:C (f) + 0.453 cell: ADLIB:NAND3A 9.984 i_SIU/I2CIF_INST/ix7293z50936:Y (r) + 0.238 net: i_SIU/I2CIF_INST/nx7293z7 10.222 i_SIU/I2CIF_INST/ix7293z24342:A (r) + 0.365 cell: ADLIB:NAND3 10.587 i_SIU/I2CIF_INST/ix7293z24342:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z6 10.828 i_SIU/I2CIF_INST/ix7293z50934:A (f) + 0.497 cell: ADLIB:NAND3A 11.325 i_SIU/I2CIF_INST/ix7293z50934:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z5 11.566 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:B (f) + 0.466 cell: ADLIB:NAND3B 12.032 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:Y (f) + 0.241 net: i_SIU/I2CIF_INST/s_sda_out_3n41ss1 12.273 i_SIU/I2CIF_INST/ix33626z14896:A (f) + 0.462 cell: ADLIB:MX2 12.735 i_SIU/I2CIF_INST/ix33626z14896:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx33626z1 12.976 i_SIU/I2CIF_INST/reg_s_sda_out:D (f) 12.976 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 23.297 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.869 i_SIU/I2CIF_INST/reg_s_sda_out:D 22.869 data required time Expanded Path 2 From: i_SIU/I2CIF_INST/reg_bit_count(1):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D data required time 22.869 data arrival time - 12.128 slack 10.741 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(1):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(1):Q (f) + 0.430 net: i_SIU/I2CIF_INST/bit_count_1_ 6.121 i_SIU/I2CIF_INST/ix9993z24342:B (f) + 0.469 cell: ADLIB:NAND2 6.590 i_SIU/I2CIF_INST/ix9993z24342:Y (r) + 1.856 net: i_SIU/I2CIF_INST/nx9993z4 8.446 i_SIU/I2CIF_INST/ix7293z50938:A (r) + 0.509 cell: ADLIB:NAND3A 8.955 i_SIU/I2CIF_INST/ix7293z50938:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx7293z9 9.204 i_SIU/I2CIF_INST/ix7293z24342:B (r) + 0.535 cell: ADLIB:NAND3 9.739 i_SIU/I2CIF_INST/ix7293z24342:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z6 9.980 i_SIU/I2CIF_INST/ix7293z50934:A (f) + 0.497 cell: ADLIB:NAND3A 10.477 i_SIU/I2CIF_INST/ix7293z50934:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z5 10.718 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:B (f) + 0.466 cell: ADLIB:NAND3B 11.184 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:Y (f) + 0.241 net: i_SIU/I2CIF_INST/s_sda_out_3n41ss1 11.425 i_SIU/I2CIF_INST/ix33626z14896:A (f) + 0.462 cell: ADLIB:MX2 11.887 i_SIU/I2CIF_INST/ix33626z14896:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx33626z1 12.128 i_SIU/I2CIF_INST/reg_s_sda_out:D (f) 12.128 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 23.297 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.869 i_SIU/I2CIF_INST/reg_s_sda_out:D 22.869 data required time Expanded Path 3 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(11):D data required time 22.885 data arrival time - 12.052 slack 10.833 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(0):Q (f) + 0.832 net: i_SIU/I2CIF_INST/bit_count_0_ 6.523 i_SIU/I2CIF_INST/NOT_ix15514z24339:A (f) + 0.347 cell: ADLIB:NAND3 6.870 i_SIU/I2CIF_INST/NOT_ix15514z24339:Y (r) + 1.224 net: i_SIU/I2CIF_INST/nx15514z3 8.094 i_SIU/I2CIF_INST/ix30574z50935:C (r) + 0.479 cell: ADLIB:NAND3C 8.573 i_SIU/I2CIF_INST/ix30574z50935:Y (r) + 0.303 net: i_SIU/I2CIF_INST/nx30574z4 8.876 i_SIU/I2CIF_INST/ix9993z40561:B (r) + 0.414 cell: ADLIB:AO1B 9.290 i_SIU/I2CIF_INST/ix9993z40561:Y (r) + 1.382 net: i_SIU/I2CIF_INST/nx9993z2 10.672 i_SIU/I2CIF_INST/ix10990z50932:B (r) + 0.365 cell: ADLIB:NAND3A 11.037 i_SIU/I2CIF_INST/ix10990z50932:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx10990z3 11.276 i_SIU/I2CIF_INST/ix10990z40556:C (f) + 0.527 cell: ADLIB:AO1B 11.803 i_SIU/I2CIF_INST/ix10990z40556:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx10990z1 12.052 i_SIU/I2CIF_INST/reg_i2c_present(11):D (r) 12.052 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.168 net: i_SIU/tx_clk_2b 23.313 i_SIU/I2CIF_INST/reg_i2c_present(11):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.885 i_SIU/I2CIF_INST/reg_i2c_present(11):D 22.885 data required time Expanded Path 4 From: i_SIU/I2CIF_INST/reg_q(8):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(11):D data required time 22.885 data arrival time - 12.036 slack 10.849 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.164 net: i_SIU/tx_clk_2b 5.127 i_SIU/I2CIF_INST/reg_q(8):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.677 i_SIU/I2CIF_INST/reg_q(8):Q (f) + 1.293 net: i_SIU/I2CIF_INST/scl_timer_8_ 6.970 i_SIU/I2CIF_INST/ix24592z2957:C (f) + 0.479 cell: ADLIB:AND3A 7.449 i_SIU/I2CIF_INST/ix24592z2957:Y (f) + 1.353 net: i_SIU/I2CIF_INST/nx24592z2 8.802 i_SIU/I2CIF_INST/ix9993z40561:C (f) + 0.472 cell: ADLIB:AO1B 9.274 i_SIU/I2CIF_INST/ix9993z40561:Y (r) + 1.382 net: i_SIU/I2CIF_INST/nx9993z2 10.656 i_SIU/I2CIF_INST/ix10990z50932:B (r) + 0.365 cell: ADLIB:NAND3A 11.021 i_SIU/I2CIF_INST/ix10990z50932:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx10990z3 11.260 i_SIU/I2CIF_INST/ix10990z40556:C (f) + 0.527 cell: ADLIB:AO1B 11.787 i_SIU/I2CIF_INST/ix10990z40556:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx10990z1 12.036 i_SIU/I2CIF_INST/reg_i2c_present(11):D (r) 12.036 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.168 net: i_SIU/tx_clk_2b 23.313 i_SIU/I2CIF_INST/reg_i2c_present(11):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.885 i_SIU/I2CIF_INST/reg_i2c_present(11):D 22.885 data required time Expanded Path 5 From: i_SIU/I2CIF_INST/reg_bit_count(2):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D data required time 22.869 data arrival time - 11.977 slack 10.892 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(2):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(2):Q (f) + 0.364 net: i_SIU/I2CIF_INST/bit_count_2_ 6.055 i_SIU/I2CIF_INST/ix9993z24342:A (f) + 0.384 cell: ADLIB:NAND2 6.439 i_SIU/I2CIF_INST/ix9993z24342:Y (r) + 1.856 net: i_SIU/I2CIF_INST/nx9993z4 8.295 i_SIU/I2CIF_INST/ix7293z50938:A (r) + 0.509 cell: ADLIB:NAND3A 8.804 i_SIU/I2CIF_INST/ix7293z50938:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx7293z9 9.053 i_SIU/I2CIF_INST/ix7293z24342:B (r) + 0.535 cell: ADLIB:NAND3 9.588 i_SIU/I2CIF_INST/ix7293z24342:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z6 9.829 i_SIU/I2CIF_INST/ix7293z50934:A (f) + 0.497 cell: ADLIB:NAND3A 10.326 i_SIU/I2CIF_INST/ix7293z50934:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z5 10.567 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:B (f) + 0.466 cell: ADLIB:NAND3B 11.033 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:Y (f) + 0.241 net: i_SIU/I2CIF_INST/s_sda_out_3n41ss1 11.274 i_SIU/I2CIF_INST/ix33626z14896:A (f) + 0.462 cell: ADLIB:MX2 11.736 i_SIU/I2CIF_INST/ix33626z14896:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx33626z1 11.977 i_SIU/I2CIF_INST/reg_s_sda_out:D (f) 11.977 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 23.297 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.869 i_SIU/I2CIF_INST/reg_s_sda_out:D 22.869 data required time Expanded Path 6 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D data required time 22.895 data arrival time - 11.966 slack 10.929 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(0):Q (f) + 0.832 net: i_SIU/I2CIF_INST/bit_count_0_ 6.523 i_SIU/I2CIF_INST/NOT_ix15514z24339:A (f) + 0.347 cell: ADLIB:NAND3 6.870 i_SIU/I2CIF_INST/NOT_ix15514z24339:Y (r) + 1.224 net: i_SIU/I2CIF_INST/nx15514z3 8.094 i_SIU/I2CIF_INST/ix30574z50935:C (r) + 0.479 cell: ADLIB:NAND3C 8.573 i_SIU/I2CIF_INST/ix30574z50935:Y (r) + 0.303 net: i_SIU/I2CIF_INST/nx30574z4 8.876 i_SIU/I2CIF_INST/ix9993z40561:B (r) + 0.414 cell: ADLIB:AO1B 9.290 i_SIU/I2CIF_INST/ix9993z40561:Y (r) + 1.936 net: i_SIU/I2CIF_INST/nx9993z2 11.226 i_SIU/I2CIF_INST/ix26586z26293:B (r) + 0.491 cell: ADLIB:MX2A 11.717 i_SIU/I2CIF_INST/ix26586z26293:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx26586z1 11.966 i_SIU/I2CIF_INST/reg_i2c_present(6):D (r) 11.966 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 23.323 i_SIU/I2CIF_INST/reg_i2c_present(6):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.895 i_SIU/I2CIF_INST/reg_i2c_present(6):D 22.895 data required time Expanded Path 7 From: i_SIU/I2CIF_INST/reg_q(8):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(6):D data required time 22.895 data arrival time - 11.950 slack 10.945 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.164 net: i_SIU/tx_clk_2b 5.127 i_SIU/I2CIF_INST/reg_q(8):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.677 i_SIU/I2CIF_INST/reg_q(8):Q (f) + 1.293 net: i_SIU/I2CIF_INST/scl_timer_8_ 6.970 i_SIU/I2CIF_INST/ix24592z2957:C (f) + 0.479 cell: ADLIB:AND3A 7.449 i_SIU/I2CIF_INST/ix24592z2957:Y (f) + 1.353 net: i_SIU/I2CIF_INST/nx24592z2 8.802 i_SIU/I2CIF_INST/ix9993z40561:C (f) + 0.472 cell: ADLIB:AO1B 9.274 i_SIU/I2CIF_INST/ix9993z40561:Y (r) + 1.936 net: i_SIU/I2CIF_INST/nx9993z2 11.210 i_SIU/I2CIF_INST/ix26586z26293:B (r) + 0.491 cell: ADLIB:MX2A 11.701 i_SIU/I2CIF_INST/ix26586z26293:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx26586z1 11.950 i_SIU/I2CIF_INST/reg_i2c_present(6):D (r) 11.950 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 23.323 i_SIU/I2CIF_INST/reg_i2c_present(6):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.895 i_SIU/I2CIF_INST/reg_i2c_present(6):D 22.895 data required time Expanded Path 8 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(2):D data required time 22.886 data arrival time - 11.847 slack 11.039 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(0):Q (f) + 0.832 net: i_SIU/I2CIF_INST/bit_count_0_ 6.523 i_SIU/I2CIF_INST/NOT_ix15514z24339:A (f) + 0.347 cell: ADLIB:NAND3 6.870 i_SIU/I2CIF_INST/NOT_ix15514z24339:Y (r) + 1.224 net: i_SIU/I2CIF_INST/nx15514z3 8.094 i_SIU/I2CIF_INST/ix30574z50935:C (r) + 0.479 cell: ADLIB:NAND3C 8.573 i_SIU/I2CIF_INST/ix30574z50935:Y (r) + 0.303 net: i_SIU/I2CIF_INST/nx30574z4 8.876 i_SIU/I2CIF_INST/ix30574z24339:C (r) + 0.561 cell: ADLIB:NAND3 9.437 i_SIU/I2CIF_INST/ix30574z24339:Y (f) + 0.972 net: i_SIU/I2CIF_INST/nx30574z3 10.409 i_SIU/I2CIF_INST/ix30574z40558:C (f) + 0.526 cell: ADLIB:AO1C 10.935 i_SIU/I2CIF_INST/ix30574z40558:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx30574z2 11.184 i_SIU/I2CIF_INST/ix30574z40556:B (r) + 0.414 cell: ADLIB:AO1B 11.598 i_SIU/I2CIF_INST/ix30574z40556:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx30574z1 11.847 i_SIU/I2CIF_INST/reg_i2c_present(2):D (r) 11.847 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.169 net: i_SIU/tx_clk_2b 23.314 i_SIU/I2CIF_INST/reg_i2c_present(2):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.886 i_SIU/I2CIF_INST/reg_i2c_present(2):D 22.886 data required time Expanded Path 9 From: i_SIU/I2CIF_INST/reg_bit_count(1):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(11):D data required time 22.885 data arrival time - 11.822 slack 11.063 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(1):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(1):Q (f) + 0.430 net: i_SIU/I2CIF_INST/bit_count_1_ 6.121 i_SIU/I2CIF_INST/ix9993z24342:B (f) + 0.469 cell: ADLIB:NAND2 6.590 i_SIU/I2CIF_INST/ix9993z24342:Y (r) + 1.384 net: i_SIU/I2CIF_INST/nx9993z4 7.974 i_SIU/I2CIF_INST/ix9993z50933:A (r) + 0.509 cell: ADLIB:NAND3A 8.483 i_SIU/I2CIF_INST/ix9993z50933:Y (r) + 0.289 net: i_SIU/I2CIF_INST/nx9993z3 8.772 i_SIU/I2CIF_INST/ix9993z40561:A (r) + 0.288 cell: ADLIB:AO1B 9.060 i_SIU/I2CIF_INST/ix9993z40561:Y (r) + 1.382 net: i_SIU/I2CIF_INST/nx9993z2 10.442 i_SIU/I2CIF_INST/ix10990z50932:B (r) + 0.365 cell: ADLIB:NAND3A 10.807 i_SIU/I2CIF_INST/ix10990z50932:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx10990z3 11.046 i_SIU/I2CIF_INST/ix10990z40556:C (f) + 0.527 cell: ADLIB:AO1B 11.573 i_SIU/I2CIF_INST/ix10990z40556:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx10990z1 11.822 i_SIU/I2CIF_INST/reg_i2c_present(11):D (r) 11.822 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.168 net: i_SIU/tx_clk_2b 23.313 i_SIU/I2CIF_INST/reg_i2c_present(11):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.885 i_SIU/I2CIF_INST/reg_i2c_present(11):D 22.885 data required time Expanded Path 10 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_i2c_present(10):D data required time 22.911 data arrival time - 11.810 slack 11.101 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b 5.141 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.691 i_SIU/I2CIF_INST/reg_bit_count(0):Q (f) + 0.832 net: i_SIU/I2CIF_INST/bit_count_0_ 6.523 i_SIU/I2CIF_INST/NOT_ix15514z24339:A (f) + 0.347 cell: ADLIB:NAND3 6.870 i_SIU/I2CIF_INST/NOT_ix15514z24339:Y (r) + 1.224 net: i_SIU/I2CIF_INST/nx15514z3 8.094 i_SIU/I2CIF_INST/ix30574z50935:C (r) + 0.479 cell: ADLIB:NAND3C 8.573 i_SIU/I2CIF_INST/ix30574z50935:Y (r) + 0.303 net: i_SIU/I2CIF_INST/nx30574z4 8.876 i_SIU/I2CIF_INST/ix9993z40561:B (r) + 0.414 cell: ADLIB:AO1B 9.290 i_SIU/I2CIF_INST/ix9993z40561:Y (r) + 1.904 net: i_SIU/I2CIF_INST/nx9993z2 11.194 i_SIU/I2CIF_INST/ix11987z40557:A (r) + 0.375 cell: ADLIB:AO1C 11.569 i_SIU/I2CIF_INST/ix11987z40557:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx11987z1 11.810 i_SIU/I2CIF_INST/reg_i2c_present(10):D (f) 11.810 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 21.609 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.145 i_SIU/cbuf_tx_clk_2:Y (r) + 1.168 net: i_SIU/tx_clk_2b 23.313 i_SIU/I2CIF_INST/reg_i2c_present(10):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 22.911 i_SIU/I2CIF_INST/reg_i2c_present(10):D 22.911 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(3):D Delay (ns): 11.818 Slack (ns): Arrival (ns): 11.818 Required (ns): Setup (ns): 0.402 External Setup (ns): 7.079 Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(5):D Delay (ns): 11.128 Slack (ns): Arrival (ns): 11.128 Required (ns): Setup (ns): 0.402 External Setup (ns): 6.397 Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Delay (ns): 9.966 Slack (ns): Arrival (ns): 9.966 Required (ns): Setup (ns): 0.402 External Setup (ns): 5.233 Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Delay (ns): 9.806 Slack (ns): Arrival (ns): 9.806 Required (ns): Setup (ns): 0.402 External Setup (ns): 5.073 Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Delay (ns): 9.797 Slack (ns): Arrival (ns): 9.797 Required (ns): Setup (ns): 0.402 External Setup (ns): 5.064 Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(1):D Delay (ns): 9.707 Slack (ns): Arrival (ns): 9.707 Required (ns): Setup (ns): 0.402 External Setup (ns): 4.994 Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Delay (ns): 9.710 Slack (ns): Arrival (ns): 9.710 Required (ns): Setup (ns): 0.402 External Setup (ns): 4.971 Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Delay (ns): 9.654 Slack (ns): Arrival (ns): 9.654 Required (ns): Setup (ns): 0.402 External Setup (ns): 4.941 Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Delay (ns): 9.411 Slack (ns): Arrival (ns): 9.411 Required (ns): Setup (ns): 0.402 External Setup (ns): 4.682 Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Delay (ns): 8.109 Slack (ns): Arrival (ns): 8.109 Required (ns): Setup (ns): 0.402 External Setup (ns): 3.376 Expanded Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(3):D data required time N/C data arrival time - 11.818 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.730 net: SDA_ID_i 8.931 i_SIU/I2CIF_INST/ix29577z26293:A (r) + 0.497 cell: ADLIB:MX2C 9.428 i_SIU/I2CIF_INST/ix29577z26293:Y (f) + 1.125 net: i_SIU/I2CIF_INST/nx29577z3 10.553 i_SIU/I2CIF_INST/ix29577z24339:A (f) + 0.288 cell: ADLIB:NAND2 10.841 i_SIU/I2CIF_INST/ix29577z24339:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx29577z2 11.090 i_SIU/I2CIF_INST/ix29577z40557:C (r) + 0.489 cell: ADLIB:AO1C 11.579 i_SIU/I2CIF_INST/ix29577z40557:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx29577z1 11.818 i_SIU/I2CIF_INST/reg_i2c_present(3):D (f) 11.818 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(3):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(3):D Expanded Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(5):D data required time N/C data arrival time - 11.128 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.730 net: SDA_ID_i 8.931 i_SIU/I2CIF_INST/ix29577z26293:A (r) + 0.497 cell: ADLIB:MX2C 9.428 i_SIU/I2CIF_INST/ix29577z26293:Y (f) + 0.244 net: i_SIU/I2CIF_INST/nx29577z3 9.672 i_SIU/I2CIF_INST/ix27583z24339:B (f) + 0.471 cell: ADLIB:NAND2 10.143 i_SIU/I2CIF_INST/ix27583z24339:Y (r) + 0.252 net: i_SIU/I2CIF_INST/nx27583z2 10.395 i_SIU/I2CIF_INST/ix27583z40557:C (r) + 0.489 cell: ADLIB:AO1C 10.884 i_SIU/I2CIF_INST/ix27583z40557:Y (f) + 0.244 net: i_SIU/I2CIF_INST/nx27583z1 11.128 i_SIU/I2CIF_INST/reg_i2c_present(5):D (f) 11.128 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.170 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(5):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(5):D Expanded Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D data required time N/C data arrival time - 9.966 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 8.019 net: SDA_ID_i 9.220 i_SIU/I2CIF_INST/ix13520z14896:A (r) + 0.497 cell: ADLIB:MX2 9.717 i_SIU/I2CIF_INST/ix13520z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx13520z1 9.966 i_SIU/I2CIF_INST/reg_i2c_rddata(5):D (r) 9.966 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.172 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Expanded Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D data required time N/C data arrival time - 9.806 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.859 net: SDA_ID_i 9.060 i_SIU/I2CIF_INST/ix15514z14896:A (r) + 0.497 cell: ADLIB:MX2 9.557 i_SIU/I2CIF_INST/ix15514z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx15514z1 9.806 i_SIU/I2CIF_INST/reg_i2c_rddata(7):D (r) 9.806 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.172 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Expanded Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D data required time N/C data arrival time - 9.797 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.850 net: SDA_ID_i 9.051 i_SIU/I2CIF_INST/ix12523z14896:A (r) + 0.497 cell: ADLIB:MX2 9.548 i_SIU/I2CIF_INST/ix12523z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx12523z1 9.797 i_SIU/I2CIF_INST/reg_i2c_rddata(4):D (r) 9.797 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.172 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Expanded Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(1):D data required time N/C data arrival time - 9.707 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.760 net: SDA_ID_i 8.961 i_SIU/I2CIF_INST/ix9532z14896:A (r) + 0.497 cell: ADLIB:MX2 9.458 i_SIU/I2CIF_INST/ix9532z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx9532z1 9.707 i_SIU/I2CIF_INST/reg_i2c_rddata(1):D (r) 9.707 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(1):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(1):D Expanded Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D data required time N/C data arrival time - 9.710 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.763 net: SDA_ID_i 8.964 i_SIU/I2CIF_INST/ix8535z14896:A (r) + 0.497 cell: ADLIB:MX2 9.461 i_SIU/I2CIF_INST/ix8535z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx8535z1 9.710 i_SIU/I2CIF_INST/reg_i2c_rddata(0):D (r) 9.710 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.178 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Expanded Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D data required time N/C data arrival time - 9.654 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.707 net: SDA_ID_i 8.908 i_SIU/I2CIF_INST/ix11526z14896:A (r) + 0.497 cell: ADLIB:MX2 9.405 i_SIU/I2CIF_INST/ix11526z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx11526z1 9.654 i_SIU/I2CIF_INST/reg_i2c_rddata(3):D (r) 9.654 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Expanded Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D data required time N/C data arrival time - 9.411 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 7.464 net: SDA_ID_i 8.665 i_SIU/I2CIF_INST/ix14517z14896:A (r) + 0.497 cell: ADLIB:MX2 9.162 i_SIU/I2CIF_INST/ix14517z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx14517z1 9.411 i_SIU/I2CIF_INST/reg_i2c_rddata(6):D (r) 9.411 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.168 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Expanded Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D data required time N/C data arrival time - 8.109 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 6.162 net: SDA_ID_i 7.363 i_SIU/I2CIF_INST/ix10529z14896:A (r) + 0.497 cell: ADLIB:MX2 7.860 i_SIU/I2CIF_INST/ix10529z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx10529z1 8.109 i_SIU/I2CIF_INST/reg_i2c_rddata(2):D (r) 8.109 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 1.172 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):D END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID Delay (ns): 10.757 Slack (ns): Arrival (ns): 15.872 Required (ns): Clock to Out (ns): 15.872 Path 2 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID Delay (ns): 10.155 Slack (ns): Arrival (ns): 15.273 Required (ns): Clock to Out (ns): 15.273 Path 3 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID Delay (ns): 10.156 Slack (ns): Arrival (ns): 15.271 Required (ns): Clock to Out (ns): 15.271 Path 4 From: i_SIU/reg_led3:CLK To: LED_SIU(3) Delay (ns): 9.790 Slack (ns): Arrival (ns): 14.905 Required (ns): Clock to Out (ns): 14.905 Path 5 From: i_SIU/reg_led4:CLK To: LED_SIU(4) Delay (ns): 7.961 Slack (ns): Arrival (ns): 13.076 Required (ns): Clock to Out (ns): 13.076 Expanded Path 1 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID data required time N/C data arrival time - 15.872 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 5.115 i_SIU/I2CIF_INST/reg_s_sda_ena:CLK (r) + 0.434 cell: ADLIB:DFN1P0 5.549 i_SIU/I2CIF_INST/reg_s_sda_ena:Q (r) + 5.421 net: SDA_ID_e 10.970 bbuf_SDA_ID/U0/U1:E (r) + 0.319 cell: ADLIB:IOBI_IB_OB_EB 11.289 bbuf_SDA_ID/U0/U1:EOUT (r) + 0.000 net: bbuf_SDA_ID/U0/NET2 11.289 bbuf_SDA_ID/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 15.872 bbuf_SDA_ID/U0/U0:PAD (f) + 0.000 net: SDA_ID 15.872 SDA_ID (f) 15.872 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (f) Expanded Path 2 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID data required time N/C data arrival time - 15.273 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.155 net: i_SIU/tx_clk_2b 5.118 i_SIU/I2CIF_INST/reg_i2c_scl:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.668 i_SIU/I2CIF_INST/reg_i2c_scl:Q (f) + 4.671 net: SCL_ID_i 10.339 obuf_SCL_ID_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 10.774 obuf_SCL_ID_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SCL_ID_U1/U0/NET1 10.774 obuf_SCL_ID_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 15.273 obuf_SCL_ID_U1/U0/U0:PAD (f) + 0.000 net: SCL_ID 15.273 SCL_ID (f) 15.273 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SCL_ID (f) Expanded Path 3 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID data required time N/C data arrival time - 15.271 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 5.115 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.665 i_SIU/I2CIF_INST/reg_s_sda_out:Q (f) + 4.672 net: SDA_ID_o 10.337 bbuf_SDA_ID/U0/U1:D (f) + 0.435 cell: ADLIB:IOBI_IB_OB_EB 10.772 bbuf_SDA_ID/U0/U1:DOUT (f) + 0.000 net: bbuf_SDA_ID/U0/NET1 10.772 bbuf_SDA_ID/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_BI 15.271 bbuf_SDA_ID/U0/U0:PAD (f) + 0.000 net: SDA_ID 15.271 SDA_ID (f) 15.271 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (f) Expanded Path 4 From: i_SIU/reg_led3:CLK To: LED_SIU(3) data required time N/C data arrival time - 14.905 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 5.115 i_SIU/reg_led3:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.665 i_SIU/reg_led3:Q (f) + 3.747 net: LED_SIU_i_3_ 9.412 genblk5[3].leds_siu_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 9.847 genblk5[3].leds_siu_U1/U0/U1:DOUT (f) + 0.000 net: genblk5[3]_leds_siu_U1/U0/NET1 9.847 genblk5[3].leds_siu_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 14.905 genblk5[3].leds_siu_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_3_ 14.905 LED_SIU(3) (f) 14.905 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(3) (f) Expanded Path 5 From: i_SIU/reg_led4:CLK To: LED_SIU(4) data required time N/C data arrival time - 13.076 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.427 net: i_SIU/tx_clk_2 3.427 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.963 i_SIU/cbuf_tx_clk_2:Y (r) + 1.152 net: i_SIU/tx_clk_2b 5.115 i_SIU/reg_led4:CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.665 i_SIU/reg_led4:Q (f) + 1.861 net: LED_SIU_i_4_ 7.526 genblk5[4].leds_siu_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 8.018 genblk5[4].leds_siu_U1/U0/U1:DOUT (f) + 0.000 net: genblk5[4]_leds_siu_U1/U0/NET1 8.018 genblk5[4].leds_siu_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 13.076 genblk5[4].leds_siu_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_4_ 13.076 LED_SIU(4) (f) 13.076 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(4) (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_adc/cdiv_reg_q:Q SET Register to Register Path 1 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(2)(7):E Delay (ns): 11.723 Slack (ns): 87.778 Arrival (ns): 14.915 Required (ns): 102.693 Setup (ns): 0.454 Minimum Period (ns): 12.222 Path 2 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(2)(4):E Delay (ns): 11.686 Slack (ns): 87.835 Arrival (ns): 14.878 Required (ns): 102.713 Setup (ns): 0.454 Minimum Period (ns): 12.165 Path 3 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(2)(7):E Delay (ns): 11.506 Slack (ns): 87.995 Arrival (ns): 14.698 Required (ns): 102.693 Setup (ns): 0.454 Minimum Period (ns): 12.005 Path 4 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(2)(4):E Delay (ns): 11.469 Slack (ns): 88.052 Arrival (ns): 14.661 Required (ns): 102.713 Setup (ns): 0.454 Minimum Period (ns): 11.948 Path 5 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/bsl/reg_retbyte(5):D Delay (ns): 11.417 Slack (ns): 88.107 Arrival (ns): 14.609 Required (ns): 102.716 Setup (ns): 0.428 Minimum Period (ns): 11.893 Path 6 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/bsl/reg_retbyte(1):D Delay (ns): 11.415 Slack (ns): 88.109 Arrival (ns): 14.607 Required (ns): 102.716 Setup (ns): 0.428 Minimum Period (ns): 11.891 Path 7 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/bsl/reg_retbyte(2):D Delay (ns): 11.328 Slack (ns): 88.200 Arrival (ns): 14.520 Required (ns): 102.720 Setup (ns): 0.428 Minimum Period (ns): 11.800 Path 8 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK To: i_adc/ds_tsens/reg_read_reg(2)(7):E Delay (ns): 11.315 Slack (ns): 88.214 Arrival (ns): 14.479 Required (ns): 102.693 Setup (ns): 0.454 Minimum Period (ns): 11.786 Path 9 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK To: i_adc/ds_tsens/reg_read_reg(2)(4):E Delay (ns): 11.278 Slack (ns): 88.271 Arrival (ns): 14.442 Required (ns): 102.713 Setup (ns): 0.454 Minimum Period (ns): 11.729 Path 10 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(2)(5):E Delay (ns): 11.224 Slack (ns): 88.282 Arrival (ns): 14.416 Required (ns): 102.698 Setup (ns): 0.454 Minimum Period (ns): 11.718 Expanded Path 1 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(2)(7):E data required time 102.693 data arrival time - 14.915 slack 87.778 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.626 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):Q (r) + 1.490 net: i_adc/ds_tsens/paddr_3_ 5.116 i_adc/ds_tsens/prg/ix30163z49935:A (r) + 0.384 cell: ADLIB:NAND2A 5.500 i_adc/ds_tsens/prg/ix30163z49935:Y (r) + 0.749 net: i_adc/ds_tsens/prg/nx30163z3 6.249 i_adc/ds_tsens/prg/ix27172z50932:B (r) + 0.453 cell: ADLIB:NAND3B 6.702 i_adc/ds_tsens/prg/ix27172z50932:Y (r) + 0.287 net: i_adc/ds_tsens/prg/nx27172z2 6.989 i_adc/ds_tsens/prg/ix27172z50930:B (r) + 0.365 cell: ADLIB:NAND3A 7.354 i_adc/ds_tsens/prg/ix27172z50930:Y (f) + 0.230 net: i_adc/ds_tsens/prg/nx27172z1 7.584 i_adc/ds_tsens/prg/rdata(3):A (f) + 0.392 cell: ADLIB:AND3A 7.976 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 9.127 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.637 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.886 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 10.365 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.547 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.894 i_adc/ds_tsens/ix50033z2957:Y (f) + 3.021 net: i_adc/ds_tsens/nx50033z1 14.915 i_adc/ds_tsens/reg_read_reg(2)(7):E (f) 14.915 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.148 net: i_adc/clk1MHz_b 103.147 i_adc/ds_tsens/reg_read_reg(2)(7):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.693 i_adc/ds_tsens/reg_read_reg(2)(7):E 102.693 data required time Expanded Path 2 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(2)(4):E data required time 102.713 data arrival time - 14.878 slack 87.835 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.626 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):Q (r) + 1.490 net: i_adc/ds_tsens/paddr_3_ 5.116 i_adc/ds_tsens/prg/ix30163z49935:A (r) + 0.384 cell: ADLIB:NAND2A 5.500 i_adc/ds_tsens/prg/ix30163z49935:Y (r) + 0.749 net: i_adc/ds_tsens/prg/nx30163z3 6.249 i_adc/ds_tsens/prg/ix27172z50932:B (r) + 0.453 cell: ADLIB:NAND3B 6.702 i_adc/ds_tsens/prg/ix27172z50932:Y (r) + 0.287 net: i_adc/ds_tsens/prg/nx27172z2 6.989 i_adc/ds_tsens/prg/ix27172z50930:B (r) + 0.365 cell: ADLIB:NAND3A 7.354 i_adc/ds_tsens/prg/ix27172z50930:Y (f) + 0.230 net: i_adc/ds_tsens/prg/nx27172z1 7.584 i_adc/ds_tsens/prg/rdata(3):A (f) + 0.392 cell: ADLIB:AND3A 7.976 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 9.127 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.637 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.886 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 10.365 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.547 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.894 i_adc/ds_tsens/ix50033z2957:Y (f) + 2.984 net: i_adc/ds_tsens/nx50033z1 14.878 i_adc/ds_tsens/reg_read_reg(2)(4):E (f) 14.878 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.168 net: i_adc/clk1MHz_b 103.167 i_adc/ds_tsens/reg_read_reg(2)(4):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.713 i_adc/ds_tsens/reg_read_reg(2)(4):E 102.713 data required time Expanded Path 3 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(2)(7):E data required time 102.693 data arrival time - 14.698 slack 87.995 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.742 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (f) + 1.304 net: i_adc/ds_tsens/paddr_0_ 5.046 i_adc/ds_tsens/prg/NOT_ix32157z50931:C (f) + 0.453 cell: ADLIB:NAND3A 5.499 i_adc/ds_tsens/prg/NOT_ix32157z50931:Y (r) + 0.916 net: i_adc/ds_tsens/prg/nx32157z2 6.415 i_adc/ds_tsens/prg/NOT_ix29166z50931:B (r) + 0.453 cell: ADLIB:NAND3B 6.868 i_adc/ds_tsens/prg/NOT_ix29166z50931:Y (r) + 0.356 net: i_adc/ds_tsens/prg/nx29166z1 7.224 i_adc/ds_tsens/prg/rdata(3):B (r) + 0.535 cell: ADLIB:AND3A 7.759 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 8.910 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.420 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.669 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 10.148 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.330 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.677 i_adc/ds_tsens/ix50033z2957:Y (f) + 3.021 net: i_adc/ds_tsens/nx50033z1 14.698 i_adc/ds_tsens/reg_read_reg(2)(7):E (f) 14.698 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.148 net: i_adc/clk1MHz_b 103.147 i_adc/ds_tsens/reg_read_reg(2)(7):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.693 i_adc/ds_tsens/reg_read_reg(2)(7):E 102.693 data required time Expanded Path 4 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(2)(4):E data required time 102.713 data arrival time - 14.661 slack 88.052 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.742 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (f) + 1.304 net: i_adc/ds_tsens/paddr_0_ 5.046 i_adc/ds_tsens/prg/NOT_ix32157z50931:C (f) + 0.453 cell: ADLIB:NAND3A 5.499 i_adc/ds_tsens/prg/NOT_ix32157z50931:Y (r) + 0.916 net: i_adc/ds_tsens/prg/nx32157z2 6.415 i_adc/ds_tsens/prg/NOT_ix29166z50931:B (r) + 0.453 cell: ADLIB:NAND3B 6.868 i_adc/ds_tsens/prg/NOT_ix29166z50931:Y (r) + 0.356 net: i_adc/ds_tsens/prg/nx29166z1 7.224 i_adc/ds_tsens/prg/rdata(3):B (r) + 0.535 cell: ADLIB:AND3A 7.759 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 8.910 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.420 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.669 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 10.148 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.330 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.677 i_adc/ds_tsens/ix50033z2957:Y (f) + 2.984 net: i_adc/ds_tsens/nx50033z1 14.661 i_adc/ds_tsens/reg_read_reg(2)(4):E (f) 14.661 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.168 net: i_adc/clk1MHz_b 103.167 i_adc/ds_tsens/reg_read_reg(2)(4):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.713 i_adc/ds_tsens/reg_read_reg(2)(4):E 102.713 data required time Expanded Path 5 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/bsl/reg_retbyte(5):D data required time 102.716 data arrival time - 14.609 slack 88.107 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.626 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 2.033 net: i_adc/ds_tsens/paddr_0_ 5.659 i_adc/ds_tsens/prg/ix33154z50936:B (r) + 0.479 cell: ADLIB:NAND3C 6.138 i_adc/ds_tsens/prg/ix33154z50936:Y (r) + 0.249 net: i_adc/ds_tsens/prg/nx33154z5 6.387 i_adc/ds_tsens/prg/ix33154z14899:A (r) + 0.497 cell: ADLIB:MX2 6.884 i_adc/ds_tsens/prg/ix33154z14899:Y (r) + 0.249 net: i_adc/ds_tsens/prg/nx33154z4 7.133 i_adc/ds_tsens/prg/rdata(9):C (r) + 0.497 cell: ADLIB:AND3A 7.630 i_adc/ds_tsens/prg/rdata(9):Y (r) + 1.590 net: i_adc/ds_tsens/pcmd_1_ 9.220 i_adc/ds_tsens/bsl/NOT_ix49087z49940:A (r) + 0.271 cell: ADLIB:NAND2B 9.491 i_adc/ds_tsens/bsl/NOT_ix49087z49940:Y (r) + 0.970 net: i_adc/ds_tsens/bsl/nx49087z7 10.461 i_adc/ds_tsens/bsl/ix3628z50938:B (r) + 0.453 cell: ADLIB:NAND3C 10.914 i_adc/ds_tsens/bsl/ix3628z50938:Y (r) + 2.264 net: i_adc/ds_tsens/bsl/nx3628z7 13.178 i_adc/ds_tsens/bsl/ix1634z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.750 i_adc/ds_tsens/bsl/ix1634z40560:Y (f) + 0.230 net: i_adc/ds_tsens/bsl/nx1634z2 13.980 i_adc/ds_tsens/bsl/ix1634z14896:S (f) + 0.388 cell: ADLIB:MX2 14.368 i_adc/ds_tsens/bsl/ix1634z14896:Y (f) + 0.241 net: i_adc/ds_tsens/bsl/nx1634z1 14.609 i_adc/ds_tsens/bsl/reg_retbyte(5):D (f) 14.609 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b 103.144 i_adc/ds_tsens/bsl/reg_retbyte(5):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 102.716 i_adc/ds_tsens/bsl/reg_retbyte(5):D 102.716 data required time Expanded Path 6 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/bsl/reg_retbyte(1):D data required time 102.716 data arrival time - 14.607 slack 88.109 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.626 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 2.033 net: i_adc/ds_tsens/paddr_0_ 5.659 i_adc/ds_tsens/prg/ix33154z50936:B (r) + 0.479 cell: ADLIB:NAND3C 6.138 i_adc/ds_tsens/prg/ix33154z50936:Y (r) + 0.249 net: i_adc/ds_tsens/prg/nx33154z5 6.387 i_adc/ds_tsens/prg/ix33154z14899:A (r) + 0.497 cell: ADLIB:MX2 6.884 i_adc/ds_tsens/prg/ix33154z14899:Y (r) + 0.249 net: i_adc/ds_tsens/prg/nx33154z4 7.133 i_adc/ds_tsens/prg/rdata(9):C (r) + 0.497 cell: ADLIB:AND3A 7.630 i_adc/ds_tsens/prg/rdata(9):Y (r) + 1.590 net: i_adc/ds_tsens/pcmd_1_ 9.220 i_adc/ds_tsens/bsl/NOT_ix49087z49940:A (r) + 0.271 cell: ADLIB:NAND2B 9.491 i_adc/ds_tsens/bsl/NOT_ix49087z49940:Y (r) + 0.970 net: i_adc/ds_tsens/bsl/nx49087z7 10.461 i_adc/ds_tsens/bsl/ix3628z50938:B (r) + 0.453 cell: ADLIB:NAND3C 10.914 i_adc/ds_tsens/bsl/ix3628z50938:Y (r) + 2.264 net: i_adc/ds_tsens/bsl/nx3628z7 13.178 i_adc/ds_tsens/bsl/ix63182z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.750 i_adc/ds_tsens/bsl/ix63182z40560:Y (f) + 0.230 net: i_adc/ds_tsens/bsl/nx63182z2 13.980 i_adc/ds_tsens/bsl/ix63182z14896:S (f) + 0.388 cell: ADLIB:MX2 14.368 i_adc/ds_tsens/bsl/ix63182z14896:Y (f) + 0.239 net: i_adc/ds_tsens/bsl/nx63182z1 14.607 i_adc/ds_tsens/bsl/reg_retbyte(1):D (f) 14.607 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b 103.144 i_adc/ds_tsens/bsl/reg_retbyte(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 102.716 i_adc/ds_tsens/bsl/reg_retbyte(1):D 102.716 data required time Expanded Path 7 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/bsl/reg_retbyte(2):D data required time 102.720 data arrival time - 14.520 slack 88.200 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.626 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 2.033 net: i_adc/ds_tsens/paddr_0_ 5.659 i_adc/ds_tsens/prg/ix33154z50936:B (r) + 0.479 cell: ADLIB:NAND3C 6.138 i_adc/ds_tsens/prg/ix33154z50936:Y (r) + 0.249 net: i_adc/ds_tsens/prg/nx33154z5 6.387 i_adc/ds_tsens/prg/ix33154z14899:A (r) + 0.497 cell: ADLIB:MX2 6.884 i_adc/ds_tsens/prg/ix33154z14899:Y (r) + 0.249 net: i_adc/ds_tsens/prg/nx33154z4 7.133 i_adc/ds_tsens/prg/rdata(9):C (r) + 0.497 cell: ADLIB:AND3A 7.630 i_adc/ds_tsens/prg/rdata(9):Y (r) + 1.590 net: i_adc/ds_tsens/pcmd_1_ 9.220 i_adc/ds_tsens/bsl/NOT_ix49087z49940:A (r) + 0.271 cell: ADLIB:NAND2B 9.491 i_adc/ds_tsens/bsl/NOT_ix49087z49940:Y (r) + 0.970 net: i_adc/ds_tsens/bsl/nx49087z7 10.461 i_adc/ds_tsens/bsl/ix3628z50938:B (r) + 0.453 cell: ADLIB:NAND3C 10.914 i_adc/ds_tsens/bsl/ix3628z50938:Y (r) + 2.175 net: i_adc/ds_tsens/bsl/nx3628z7 13.089 i_adc/ds_tsens/bsl/ix64179z40560:C (r) + 0.572 cell: ADLIB:AO1E 13.661 i_adc/ds_tsens/bsl/ix64179z40560:Y (f) + 0.230 net: i_adc/ds_tsens/bsl/nx64179z2 13.891 i_adc/ds_tsens/bsl/ix64179z14896:S (f) + 0.388 cell: ADLIB:MX2 14.279 i_adc/ds_tsens/bsl/ix64179z14896:Y (f) + 0.241 net: i_adc/ds_tsens/bsl/nx64179z1 14.520 i_adc/ds_tsens/bsl/reg_retbyte(2):D (f) 14.520 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.149 net: i_adc/clk1MHz_b 103.148 i_adc/ds_tsens/bsl/reg_retbyte(2):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 102.720 i_adc/ds_tsens/bsl/reg_retbyte(2):D 102.720 data required time Expanded Path 8 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK To: i_adc/ds_tsens/reg_read_reg(2)(7):E data required time 102.693 data arrival time - 14.479 slack 88.214 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.165 net: i_adc/clk1MHz_b 3.164 i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.714 i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):Q (f) + 1.962 net: i_adc/ds_tsens/paddr_2_ 5.676 i_adc/ds_tsens/prg/NOT_ix27172z50933:C (f) + 0.347 cell: ADLIB:NAND3B 6.023 i_adc/ds_tsens/prg/NOT_ix27172z50933:Y (r) + 0.361 net: i_adc/ds_tsens/prg/nx27172z3 6.384 i_adc/ds_tsens/prg/ix27172z50930:C (r) + 0.534 cell: ADLIB:NAND3A 6.918 i_adc/ds_tsens/prg/ix27172z50930:Y (f) + 0.230 net: i_adc/ds_tsens/prg/nx27172z1 7.148 i_adc/ds_tsens/prg/rdata(3):A (f) + 0.392 cell: ADLIB:AND3A 7.540 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 8.691 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.201 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.450 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 9.929 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.111 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.458 i_adc/ds_tsens/ix50033z2957:Y (f) + 3.021 net: i_adc/ds_tsens/nx50033z1 14.479 i_adc/ds_tsens/reg_read_reg(2)(7):E (f) 14.479 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.148 net: i_adc/clk1MHz_b 103.147 i_adc/ds_tsens/reg_read_reg(2)(7):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.693 i_adc/ds_tsens/reg_read_reg(2)(7):E 102.693 data required time Expanded Path 9 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK To: i_adc/ds_tsens/reg_read_reg(2)(4):E data required time 102.713 data arrival time - 14.442 slack 88.271 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.165 net: i_adc/clk1MHz_b 3.164 i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.714 i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):Q (f) + 1.962 net: i_adc/ds_tsens/paddr_2_ 5.676 i_adc/ds_tsens/prg/NOT_ix27172z50933:C (f) + 0.347 cell: ADLIB:NAND3B 6.023 i_adc/ds_tsens/prg/NOT_ix27172z50933:Y (r) + 0.361 net: i_adc/ds_tsens/prg/nx27172z3 6.384 i_adc/ds_tsens/prg/ix27172z50930:C (r) + 0.534 cell: ADLIB:NAND3A 6.918 i_adc/ds_tsens/prg/ix27172z50930:Y (f) + 0.230 net: i_adc/ds_tsens/prg/nx27172z1 7.148 i_adc/ds_tsens/prg/rdata(3):A (f) + 0.392 cell: ADLIB:AND3A 7.540 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 8.691 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.201 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.450 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 9.929 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.111 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.458 i_adc/ds_tsens/ix50033z2957:Y (f) + 2.984 net: i_adc/ds_tsens/nx50033z1 14.442 i_adc/ds_tsens/reg_read_reg(2)(4):E (f) 14.442 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.168 net: i_adc/clk1MHz_b 103.167 i_adc/ds_tsens/reg_read_reg(2)(4):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.713 i_adc/ds_tsens/reg_read_reg(2)(4):E 102.713 data required time Expanded Path 10 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(2)(5):E data required time 102.698 data arrival time - 14.416 slack 88.282 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.193 net: i_adc/clk1MHz_b 3.192 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.626 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):Q (r) + 1.490 net: i_adc/ds_tsens/paddr_3_ 5.116 i_adc/ds_tsens/prg/ix30163z49935:A (r) + 0.384 cell: ADLIB:NAND2A 5.500 i_adc/ds_tsens/prg/ix30163z49935:Y (r) + 0.749 net: i_adc/ds_tsens/prg/nx30163z3 6.249 i_adc/ds_tsens/prg/ix27172z50932:B (r) + 0.453 cell: ADLIB:NAND3B 6.702 i_adc/ds_tsens/prg/ix27172z50932:Y (r) + 0.287 net: i_adc/ds_tsens/prg/nx27172z2 6.989 i_adc/ds_tsens/prg/ix27172z50930:B (r) + 0.365 cell: ADLIB:NAND3A 7.354 i_adc/ds_tsens/prg/ix27172z50930:Y (f) + 0.230 net: i_adc/ds_tsens/prg/nx27172z1 7.584 i_adc/ds_tsens/prg/rdata(3):A (f) + 0.392 cell: ADLIB:AND3A 7.976 i_adc/ds_tsens/prg/rdata(3):Y (r) + 1.151 net: i_adc/ds_tsens/pdata_3_ 9.127 i_adc/ds_tsens/ix60303z50934:C (r) + 0.510 cell: ADLIB:NAND3C 9.637 i_adc/ds_tsens/ix60303z50934:Y (r) + 0.249 net: i_adc/ds_tsens/nx60303z3 9.886 i_adc/ds_tsens/ix60303z50932:A (r) + 0.479 cell: ADLIB:NAND3B 10.365 i_adc/ds_tsens/ix60303z50932:Y (r) + 1.182 net: i_adc/ds_tsens/nx60303z2 11.547 i_adc/ds_tsens/ix50033z2957:A (r) + 0.347 cell: ADLIB:AND3B 11.894 i_adc/ds_tsens/ix50033z2957:Y (f) + 2.522 net: i_adc/ds_tsens/nx50033z1 14.416 i_adc/ds_tsens/reg_read_reg(2)(5):E (f) 14.416 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 101.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.999 i_adc/cbuf_1MHz:Y (r) + 1.153 net: i_adc/clk1MHz_b 103.152 i_adc/ds_tsens/reg_read_reg(2)(5):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.698 i_adc/ds_tsens/reg_read_reg(2)(5):E 102.698 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D Delay (ns): 6.132 Slack (ns): Arrival (ns): 6.132 Required (ns): Setup (ns): 0.402 External Setup (ns): 3.387 Expanded Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D data required time N/C data arrival time - 6.132 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TSENS (r) + 0.000 net: TSENS 0.000 bbuf_TSENS/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_TSENS/U0/U0:Y (r) + 0.000 net: bbuf_TSENS/U0/NET3 1.169 bbuf_TSENS/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_TSENS/U0/U1:Y (r) + 4.176 net: TSENS_i 5.377 i_adc/ds_tsens/bsl/ts/ix5225z14896:B (r) + 0.506 cell: ADLIB:MX2 5.883 i_adc/ds_tsens/bsl/ts/ix5225z14896:Y (r) + 0.249 net: i_adc/ds_tsens/bsl/ts/nx5225z1 6.132 i_adc/ds_tsens/bsl/ts/reg_retbit:D (r) 6.132 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.148 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_retbit:CLK (r) - 0.402 Library setup time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_retbit:D END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS Delay (ns): 11.209 Slack (ns): Arrival (ns): 14.369 Required (ns): Clock to Out (ns): 14.369 Path 2 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS Delay (ns): 10.029 Slack (ns): Arrival (ns): 13.173 Required (ns): Clock to Out (ns): 13.173 Expanded Path 1 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS data required time N/C data arrival time - 14.369 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.161 net: i_adc/clk1MHz_b 3.160 i_adc/ds_tsens/bsl/reg_hold_high:CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.594 i_adc/ds_tsens/bsl/reg_hold_high:Q (r) + 1.599 net: TSENS_o 5.193 i_adc/ds_tsens/bsl/oe:A (r) + 0.271 cell: ADLIB:NAND2B 5.464 i_adc/ds_tsens/bsl/oe:Y (r) + 4.003 net: TSENS_e 9.467 bbuf_TSENS/U0/U1:E (r) + 0.319 cell: ADLIB:IOBI_IB_OB_EB 9.786 bbuf_TSENS/U0/U1:EOUT (r) + 0.000 net: bbuf_TSENS/U0/NET2 9.786 bbuf_TSENS/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 14.369 bbuf_TSENS/U0/U0:PAD (f) + 0.000 net: TSENS 14.369 TSENS (f) 14.369 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (f) Expanded Path 2 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS data required time N/C data arrival time - 13.173 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz 1.441 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.999 i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b 3.144 i_adc/ds_tsens/bsl/ts/reg_oe:CLK (r) + 0.434 cell: ADLIB:DFN1 3.578 i_adc/ds_tsens/bsl/ts/reg_oe:Q (r) + 0.249 net: i_adc/ds_tsens/bsl/oe_i 3.827 i_adc/ds_tsens/bsl/oe:B (r) + 0.441 cell: ADLIB:NAND2B 4.268 i_adc/ds_tsens/bsl/oe:Y (r) + 4.003 net: TSENS_e 8.271 bbuf_TSENS/U0/U1:E (r) + 0.319 cell: ADLIB:IOBI_IB_OB_EB 8.590 bbuf_TSENS/U0/U1:EOUT (r) + 0.000 net: bbuf_TSENS/U0/NET2 8.590 bbuf_TSENS/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 13.173 bbuf_TSENS/U0/U0:PAD (f) + 0.000 net: TSENS 13.173 TSENS (f) 13.173 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(0):CLR Delay (ns): 16.700 Slack (ns): Arrival (ns): 16.700 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 13.770 Path 2 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(7):CLR Delay (ns): 16.229 Slack (ns): Arrival (ns): 16.229 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 13.299 Path 3 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(3):CLR Delay (ns): 16.157 Slack (ns): Arrival (ns): 16.157 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 13.227 Path 4 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(5):CLR Delay (ns): 16.039 Slack (ns): Arrival (ns): 16.039 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 13.117 Path 5 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(1):CLR Delay (ns): 15.996 Slack (ns): Arrival (ns): 15.996 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 13.074 Path 6 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(4):CLR Delay (ns): 15.389 Slack (ns): Arrival (ns): 15.389 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 12.467 Path 7 From: PUSHB To: i_adc/ds_tsens/reg_q(16):CLR Delay (ns): 14.195 Slack (ns): Arrival (ns): 14.195 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.270 Path 8 From: PUSHB To: i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR Delay (ns): 14.063 Slack (ns): Arrival (ns): 14.063 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.141 Path 9 From: PUSHB To: i_adc/ds_tsens/reg_q(18):CLR Delay (ns): 14.064 Slack (ns): Arrival (ns): 14.064 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 11.139 Path 10 From: PUSHB To: i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLR Delay (ns): 13.774 Slack (ns): Arrival (ns): 13.774 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 10.832 Expanded Path 1 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(0):CLR data required time N/C data arrival time - 16.700 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.276 net: not_rst_n 16.700 i_adc/ds_tsens/bsl/reg_retbyte(0):CLR (f) 16.700 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.153 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(0):CLR Expanded Path 2 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(7):CLR data required time N/C data arrival time - 16.229 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 7.805 net: not_rst_n 16.229 i_adc/ds_tsens/bsl/reg_retbyte(7):CLR (f) 16.229 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.153 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(7):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(7):CLR Expanded Path 3 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(3):CLR data required time N/C data arrival time - 16.157 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 7.733 net: not_rst_n 16.157 i_adc/ds_tsens/bsl/reg_retbyte(3):CLR (f) 16.157 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.153 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(3):CLR Expanded Path 4 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(5):CLR data required time N/C data arrival time - 16.039 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 7.615 net: not_rst_n 16.039 i_adc/ds_tsens/bsl/reg_retbyte(5):CLR (f) 16.039 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(5):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(5):CLR Expanded Path 5 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(1):CLR data required time N/C data arrival time - 15.996 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 7.572 net: not_rst_n 15.996 i_adc/ds_tsens/bsl/reg_retbyte(1):CLR (f) 15.996 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(1):CLR Expanded Path 6 From: PUSHB To: i_adc/ds_tsens/bsl/reg_retbyte(4):CLR data required time N/C data arrival time - 15.389 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 6.965 net: not_rst_n 15.389 i_adc/ds_tsens/bsl/reg_retbyte(4):CLR (f) 15.389 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/reg_retbyte(4):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/reg_retbyte(4):CLR Expanded Path 7 From: PUSHB To: i_adc/ds_tsens/reg_q(16):CLR data required time N/C data arrival time - 14.195 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.771 net: not_rst_n 14.195 i_adc/ds_tsens/reg_q(16):CLR (f) 14.195 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.148 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(16):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(16):CLR Expanded Path 8 From: PUSHB To: i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR data required time N/C data arrival time - 14.063 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.639 net: not_rst_n 14.063 i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR (f) 14.063 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.145 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_counter(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR Expanded Path 9 From: PUSHB To: i_adc/ds_tsens/reg_q(18):CLR data required time N/C data arrival time - 14.064 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.640 net: not_rst_n 14.064 i_adc/ds_tsens/reg_q(18):CLR (f) 14.064 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.148 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(18):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(18):CLR Expanded Path 10 From: PUSHB To: i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLR data required time N/C data arrival time - 13.774 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 5.350 net: not_rst_n 13.774 i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLR (f) 13.774 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.441 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 1.165 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/modgen_counter_paddr_reg_q(2):CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLA SET Register to Register Path 1 From: i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:CLKB To: i_cbb/tim_ana/reg_trgd:D Delay (ns): 18.824 Slack (ns): 5.579 Arrival (ns): 27.802 Required (ns): 33.381 Setup (ns): 0.428 Minimum Period (ns): 19.421 Path 2 From: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:CLKB To: i_cbb/tim_ana/reg_trgd:D Delay (ns): 18.762 Slack (ns): 5.631 Arrival (ns): 27.750 Required (ns): 33.381 Setup (ns): 0.428 Minimum Period (ns): 19.369 Path 3 From: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:CLKB To: i_cbb/tim_ana/reg_trgd:D Delay (ns): 18.716 Slack (ns): 5.687 Arrival (ns): 27.694 Required (ns): 33.381 Setup (ns): 0.428 Minimum Period (ns): 19.313 Path 4 From: i_adc/adc/rfilt_4_rfi/reg_acc(7):CLK To: i_adc/adc/rfilt_4_rfi/reg_acc(18):D Delay (ns): 18.799 Slack (ns): 5.780 Arrival (ns): 27.608 Required (ns): 33.388 Setup (ns): 0.402 Minimum Period (ns): 19.220 Path 5 From: i_adc/adc/adci/reg_adc(2):CLK To: i_adc/adc/rfilt_4_rfi/reg_acc(18):D Delay (ns): 18.699 Slack (ns): 5.889 Arrival (ns): 27.499 Required (ns): 33.388 Setup (ns): 0.402 Minimum Period (ns): 19.111 Path 6 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D Delay (ns): 18.670 Slack (ns): 5.905 Arrival (ns): 27.479 Required (ns): 33.384 Setup (ns): 0.428 Minimum Period (ns): 19.095 Path 7 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D Delay (ns): 18.667 Slack (ns): 5.906 Arrival (ns): 27.448 Required (ns): 33.354 Setup (ns): 0.428 Minimum Period (ns): 19.094 Path 8 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D Delay (ns): 18.665 Slack (ns): 5.914 Arrival (ns): 27.440 Required (ns): 33.354 Setup (ns): 0.428 Minimum Period (ns): 19.086 Path 9 From: i_adc/adc/adci/reg_adc(0):CLK To: i_adc/adc/rfilt_5_rfi/reg_acc(17):D Delay (ns): 18.616 Slack (ns): 5.948 Arrival (ns): 27.409 Required (ns): 33.357 Setup (ns): 0.428 Minimum Period (ns): 19.052 Path 10 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(2):CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D Delay (ns): 18.580 Slack (ns): 5.994 Arrival (ns): 27.360 Required (ns): 33.354 Setup (ns): 0.428 Minimum Period (ns): 19.006 Expanded Path 1 From: i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:CLKB To: i_cbb/tim_ana/reg_trgd:D data required time 33.381 data arrival time - 27.802 slack 5.579 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.351 net: CLK40out 8.978 i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:CLKB (r) + 2.355 cell: ADLIB:RAM4K9 11.333 i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:DOUTB1 (r) + 1.122 net: i_cbb/trg_lut_inst/bram_lut_inst_dout_2__1_ 12.455 i_cbb/trg_lut_inst/ix21826z14897:A (r) + 0.497 cell: ADLIB:MX2 12.952 i_cbb/trg_lut_inst/ix21826z14897:Y (r) + 0.249 net: i_cbb/trg_lut_inst/nx21826z2 13.201 i_cbb/trg_lut_inst/trigger(1):B (r) + 0.437 cell: ADLIB:MX2 13.638 i_cbb/trg_lut_inst/trigger(1):Y (r) + 2.674 net: i_cbb/pt_trg_src_1_ 16.312 i_cbb/pt_align_inst/ix4955z40560:B (r) + 0.339 cell: ADLIB:AO1C 16.651 i_cbb/pt_align_inst/ix4955z40560:Y (r) + 1.161 net: i_cbb/pt_align_inst/nx4955z4 17.812 i_cbb/pt_align_inst/ix65132z40654:A (r) + 0.347 cell: ADLIB:AO1A 18.159 i_cbb/pt_align_inst/ix65132z40654:Y (f) + 0.241 net: i_cbb/pt_align_inst/nx65132z46 18.400 i_cbb/pt_align_inst/ix65132z5410:B (f) + 0.447 cell: ADLIB:AO1 18.847 i_cbb/pt_align_inst/ix65132z5410:Y (f) + 0.241 net: i_cbb/pt_align_inst/nx65132z42 19.088 i_cbb/pt_align_inst/ix65132z40591:B (f) + 0.445 cell: ADLIB:AO1B 19.533 i_cbb/pt_align_inst/ix65132z40591:Y (f) + 1.200 net: i_cbb/pt_align_inst/nx65132z34 20.733 i_cbb/pt_align_inst/trg_req:C (f) + 0.479 cell: ADLIB:NAND3A 21.212 i_cbb/pt_align_inst/trg_req:Y (r) + 1.282 net: i_cbb/ram_cnt_input_58_ 22.494 i_cbb/tim_ana/ix38912z5371:A (r) + 0.358 cell: ADLIB:AO1 22.852 i_cbb/tim_ana/ix38912z5371:Y (r) + 0.835 net: i_cbb/tim_ana/nx38912z6 23.687 i_cbb/tim_ana/ix38912z50933:B (r) + 0.479 cell: ADLIB:NAND3C 24.166 i_cbb/tim_ana/ix38912z50933:Y (r) + 0.839 net: i_cbb/tim_ana/nx38912z2 25.005 i_cbb/tim_ana/ix38912z50932:A (r) + 0.347 cell: ADLIB:NAND3C 25.352 i_cbb/tim_ana/ix38912z50932:Y (r) + 0.249 net: i_cbb/tim_ana/nx38912z1 25.601 i_cbb/tim_ana/status(3):C (r) + 0.572 cell: ADLIB:AO1 26.173 i_cbb/tim_ana/status(3):Y (r) + 0.361 net: i_cbb/tim_ana/status_3_ 26.534 i_cbb/tim_ana/ix24890z40556:C (r) + 0.489 cell: ADLIB:AO1A 27.023 i_cbb/tim_ana/ix24890z40556:Y (r) + 0.248 net: i_cbb/tim_ana/nx24890z2 27.271 i_cbb/tim_ana/ix24890z14896:S (r) + 0.278 cell: ADLIB:MX2 27.549 i_cbb/tim_ana/ix24890z14896:Y (f) + 0.253 net: i_cbb/tim_ana/nx24890z1 27.802 i_cbb/tim_ana/reg_trgd:D (f) 27.802 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.182 net: CLK40out 33.809 i_cbb/tim_ana/reg_trgd:CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.381 i_cbb/tim_ana/reg_trgd:D 33.381 data required time Expanded Path 2 From: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:CLKB To: i_cbb/tim_ana/reg_trgd:D data required time 33.381 data arrival time - 27.750 slack 5.631 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.361 net: CLK40out 8.988 i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:CLKB (r) + 2.355 cell: ADLIB:RAM4K9 11.343 i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:DOUTB1 (r) + 1.051 net: i_cbb/trg_lut_inst/bram_lut_inst_dout_3__1_ 12.394 i_cbb/trg_lut_inst/ix21826z14897:B (r) + 0.506 cell: ADLIB:MX2 12.900 i_cbb/trg_lut_inst/ix21826z14897:Y (r) + 0.249 net: i_cbb/trg_lut_inst/nx21826z2 13.149 i_cbb/trg_lut_inst/trigger(1):B (r) + 0.437 cell: ADLIB:MX2 13.586 i_cbb/trg_lut_inst/trigger(1):Y (r) + 2.674 net: i_cbb/pt_trg_src_1_ 16.260 i_cbb/pt_align_inst/ix4955z40560:B (r) + 0.339 cell: ADLIB:AO1C 16.599 i_cbb/pt_align_inst/ix4955z40560:Y (r) + 1.161 net: i_cbb/pt_align_inst/nx4955z4 17.760 i_cbb/pt_align_inst/ix65132z40654:A (r) + 0.347 cell: ADLIB:AO1A 18.107 i_cbb/pt_align_inst/ix65132z40654:Y (f) + 0.241 net: i_cbb/pt_align_inst/nx65132z46 18.348 i_cbb/pt_align_inst/ix65132z5410:B (f) + 0.447 cell: ADLIB:AO1 18.795 i_cbb/pt_align_inst/ix65132z5410:Y (f) + 0.241 net: i_cbb/pt_align_inst/nx65132z42 19.036 i_cbb/pt_align_inst/ix65132z40591:B (f) + 0.445 cell: ADLIB:AO1B 19.481 i_cbb/pt_align_inst/ix65132z40591:Y (f) + 1.200 net: i_cbb/pt_align_inst/nx65132z34 20.681 i_cbb/pt_align_inst/trg_req:C (f) + 0.479 cell: ADLIB:NAND3A 21.160 i_cbb/pt_align_inst/trg_req:Y (r) + 1.282 net: i_cbb/ram_cnt_input_58_ 22.442 i_cbb/tim_ana/ix38912z5371:A (r) + 0.358 cell: ADLIB:AO1 22.800 i_cbb/tim_ana/ix38912z5371:Y (r) + 0.835 net: i_cbb/tim_ana/nx38912z6 23.635 i_cbb/tim_ana/ix38912z50933:B (r) + 0.479 cell: ADLIB:NAND3C 24.114 i_cbb/tim_ana/ix38912z50933:Y (r) + 0.839 net: i_cbb/tim_ana/nx38912z2 24.953 i_cbb/tim_ana/ix38912z50932:A (r) + 0.347 cell: ADLIB:NAND3C 25.300 i_cbb/tim_ana/ix38912z50932:Y (r) + 0.249 net: i_cbb/tim_ana/nx38912z1 25.549 i_cbb/tim_ana/status(3):C (r) + 0.572 cell: ADLIB:AO1 26.121 i_cbb/tim_ana/status(3):Y (r) + 0.361 net: i_cbb/tim_ana/status_3_ 26.482 i_cbb/tim_ana/ix24890z40556:C (r) + 0.489 cell: ADLIB:AO1A 26.971 i_cbb/tim_ana/ix24890z40556:Y (r) + 0.248 net: i_cbb/tim_ana/nx24890z2 27.219 i_cbb/tim_ana/ix24890z14896:S (r) + 0.278 cell: ADLIB:MX2 27.497 i_cbb/tim_ana/ix24890z14896:Y (f) + 0.253 net: i_cbb/tim_ana/nx24890z1 27.750 i_cbb/tim_ana/reg_trgd:D (f) 27.750 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.182 net: CLK40out 33.809 i_cbb/tim_ana/reg_trgd:CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.381 i_cbb/tim_ana/reg_trgd:D 33.381 data required time Expanded Path 3 From: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:CLKB To: i_cbb/tim_ana/reg_trgd:D data required time 33.381 data arrival time - 27.694 slack 5.687 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.351 net: CLK40out 8.978 i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:CLKB (r) + 2.355 cell: ADLIB:RAM4K9 11.333 i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:DOUTB1 (r) + 1.018 net: i_cbb/trg_lut_inst/bram_lut_inst_dout_1__1_ 12.351 i_cbb/trg_lut_inst/ix21826z14896:B (r) + 0.506 cell: ADLIB:MX2 12.857 i_cbb/trg_lut_inst/ix21826z14896:Y (r) + 0.249 net: i_cbb/trg_lut_inst/nx21826z1 13.106 i_cbb/trg_lut_inst/trigger(1):A (r) + 0.424 cell: ADLIB:MX2 13.530 i_cbb/trg_lut_inst/trigger(1):Y (r) + 2.674 net: i_cbb/pt_trg_src_1_ 16.204 i_cbb/pt_align_inst/ix4955z40560:B (r) + 0.339 cell: ADLIB:AO1C 16.543 i_cbb/pt_align_inst/ix4955z40560:Y (r) + 1.161 net: i_cbb/pt_align_inst/nx4955z4 17.704 i_cbb/pt_align_inst/ix65132z40654:A (r) + 0.347 cell: ADLIB:AO1A 18.051 i_cbb/pt_align_inst/ix65132z40654:Y (f) + 0.241 net: i_cbb/pt_align_inst/nx65132z46 18.292 i_cbb/pt_align_inst/ix65132z5410:B (f) + 0.447 cell: ADLIB:AO1 18.739 i_cbb/pt_align_inst/ix65132z5410:Y (f) + 0.241 net: i_cbb/pt_align_inst/nx65132z42 18.980 i_cbb/pt_align_inst/ix65132z40591:B (f) + 0.445 cell: ADLIB:AO1B 19.425 i_cbb/pt_align_inst/ix65132z40591:Y (f) + 1.200 net: i_cbb/pt_align_inst/nx65132z34 20.625 i_cbb/pt_align_inst/trg_req:C (f) + 0.479 cell: ADLIB:NAND3A 21.104 i_cbb/pt_align_inst/trg_req:Y (r) + 1.282 net: i_cbb/ram_cnt_input_58_ 22.386 i_cbb/tim_ana/ix38912z5371:A (r) + 0.358 cell: ADLIB:AO1 22.744 i_cbb/tim_ana/ix38912z5371:Y (r) + 0.835 net: i_cbb/tim_ana/nx38912z6 23.579 i_cbb/tim_ana/ix38912z50933:B (r) + 0.479 cell: ADLIB:NAND3C 24.058 i_cbb/tim_ana/ix38912z50933:Y (r) + 0.839 net: i_cbb/tim_ana/nx38912z2 24.897 i_cbb/tim_ana/ix38912z50932:A (r) + 0.347 cell: ADLIB:NAND3C 25.244 i_cbb/tim_ana/ix38912z50932:Y (r) + 0.249 net: i_cbb/tim_ana/nx38912z1 25.493 i_cbb/tim_ana/status(3):C (r) + 0.572 cell: ADLIB:AO1 26.065 i_cbb/tim_ana/status(3):Y (r) + 0.361 net: i_cbb/tim_ana/status_3_ 26.426 i_cbb/tim_ana/ix24890z40556:C (r) + 0.489 cell: ADLIB:AO1A 26.915 i_cbb/tim_ana/ix24890z40556:Y (r) + 0.248 net: i_cbb/tim_ana/nx24890z2 27.163 i_cbb/tim_ana/ix24890z14896:S (r) + 0.278 cell: ADLIB:MX2 27.441 i_cbb/tim_ana/ix24890z14896:Y (f) + 0.253 net: i_cbb/tim_ana/nx24890z1 27.694 i_cbb/tim_ana/reg_trgd:D (f) 27.694 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.182 net: CLK40out 33.809 i_cbb/tim_ana/reg_trgd:CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.381 i_cbb/tim_ana/reg_trgd:D 33.381 data required time Expanded Path 4 From: i_adc/adc/rfilt_4_rfi/reg_acc(7):CLK To: i_adc/adc/rfilt_4_rfi/reg_acc(18):D data required time 33.388 data arrival time - 27.608 slack 5.780 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.182 net: CLK40out 8.809 i_adc/adc/rfilt_4_rfi/reg_acc(7):CLK (r) + 0.550 cell: ADLIB:DFN1E1 9.359 i_adc/adc/rfilt_4_rfi/reg_acc(7):Q (f) + 1.292 net: i_adc/adc/adc_4__0_ 10.651 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z49948:B (f) + 0.271 cell: ADLIB:NAND2A 10.922 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z49948:Y (r) + 0.303 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z15 11.225 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40555:B (r) + 0.546 cell: ADLIB:AO13 11.771 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40555:Y (r) + 0.500 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z14 12.271 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40566:B (r) + 0.497 cell: ADLIB:AO1A 12.768 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40566:Y (r) + 0.856 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z11 13.624 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40560:B (r) + 0.423 cell: ADLIB:AO1A 14.047 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40560:Y (r) + 1.564 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z5 15.611 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z40556:B (r) + 0.423 cell: ADLIB:AO1A 16.034 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z40556:Y (r) + 0.270 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx62798z1 16.304 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z36403:C (r) + 0.736 cell: ADLIB:XNOR3 17.040 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z36403:Y (f) + 0.316 net: i_adc/adc/rfilt_4_rfi/diff_10_ 17.356 i_adc/adc/rfilt_4_rfi/diffe_mux_0Bus3(10)_ix23050z14896:B (f) + 0.462 cell: ADLIB:MX2 17.818 i_adc/adc/rfilt_4_rfi/diffe_mux_0Bus3(10)_ix23050z14896:Y (f) + 0.856 net: i_adc/adc/rfilt_4_rfi/nx23050z1 18.674 i_adc/adc/rfilt_4_rfi/diffe(10):B (f) + 0.427 cell: ADLIB:MX2 19.101 i_adc/adc/rfilt_4_rfi/diffe(10):Y (f) + 0.389 net: i_adc/adc/rfilt_4_rfi/diffe_10_ 19.490 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z10885:B (f) + 0.700 cell: ADLIB:XOR2 20.190 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z10885:Y (r) + 0.770 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z10 20.960 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z44980:C (r) + 0.392 cell: ADLIB:XAI1 21.352 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z44980:Y (f) + 0.250 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z36 21.602 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40590:A (f) + 0.388 cell: ADLIB:AO1A 21.990 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40590:Y (r) + 1.072 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z35 23.062 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40588:B (r) + 0.423 cell: ADLIB:AO1A 23.485 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40588:Y (r) + 0.249 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z33 23.734 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40558:C (r) + 0.489 cell: ADLIB:AO1A 24.223 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40558:Y (r) + 1.474 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z4 25.697 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40556:B (r) + 0.423 cell: ADLIB:AO1A 26.120 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40556:Y (r) + 0.238 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z1 26.358 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z36403:A (r) + 0.297 cell: ADLIB:XNOR3 26.655 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z36403:Y (f) + 0.241 net: i_adc/adc/rfilt_4_rfi/acc_1n1s1_18_ 26.896 i_adc/adc/rfilt_4_rfi/ix56958z1959:B (f) + 0.471 cell: ADLIB:AND2A 27.367 i_adc/adc/rfilt_4_rfi/ix56958z1959:Y (f) + 0.241 net: i_adc/adc/rfilt_4_rfi/nx56958z1 27.608 i_adc/adc/rfilt_4_rfi/reg_acc(18):D (f) 27.608 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.163 net: CLK40out 33.790 i_adc/adc/rfilt_4_rfi/reg_acc(18):CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 33.388 i_adc/adc/rfilt_4_rfi/reg_acc(18):D 33.388 data required time Expanded Path 5 From: i_adc/adc/adci/reg_adc(2):CLK To: i_adc/adc/rfilt_4_rfi/reg_acc(18):D data required time 33.388 data arrival time - 27.499 slack 5.889 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.173 net: CLK40out 8.800 i_adc/adc/adci/reg_adc(2):CLK (r) + 0.434 cell: ADLIB:DFN1E1 9.234 i_adc/adc/adci/reg_adc(2):Q (r) + 1.637 net: i_adc/adc/dout_2_ 10.871 i_adc/adc/rfilt_4_rfi/diff_sub12_0/NOT_ix63795z49950:B (r) + 0.379 cell: ADLIB:NAND2A 11.250 i_adc/adc/rfilt_4_rfi/diff_sub12_0/NOT_ix63795z49950:Y (f) + 0.241 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z17 11.491 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40562:C (f) + 0.345 cell: ADLIB:AO18 11.836 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40562:Y (r) + 0.249 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z16 12.085 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40566:C (r) + 0.574 cell: ADLIB:AO1A 12.659 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40566:Y (r) + 0.856 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z11 13.515 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40560:B (r) + 0.423 cell: ADLIB:AO1A 13.938 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix63795z40560:Y (r) + 1.564 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx63795z5 15.502 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z40556:B (r) + 0.423 cell: ADLIB:AO1A 15.925 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z40556:Y (r) + 0.270 net: i_adc/adc/rfilt_4_rfi/diff_sub12_0/nx62798z1 16.195 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z36403:C (r) + 0.736 cell: ADLIB:XNOR3 16.931 i_adc/adc/rfilt_4_rfi/diff_sub12_0/ix62798z36403:Y (f) + 0.316 net: i_adc/adc/rfilt_4_rfi/diff_10_ 17.247 i_adc/adc/rfilt_4_rfi/diffe_mux_0Bus3(10)_ix23050z14896:B (f) + 0.462 cell: ADLIB:MX2 17.709 i_adc/adc/rfilt_4_rfi/diffe_mux_0Bus3(10)_ix23050z14896:Y (f) + 0.856 net: i_adc/adc/rfilt_4_rfi/nx23050z1 18.565 i_adc/adc/rfilt_4_rfi/diffe(10):B (f) + 0.427 cell: ADLIB:MX2 18.992 i_adc/adc/rfilt_4_rfi/diffe(10):Y (f) + 0.389 net: i_adc/adc/rfilt_4_rfi/diffe_10_ 19.381 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z10885:B (f) + 0.700 cell: ADLIB:XOR2 20.081 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z10885:Y (r) + 0.770 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z10 20.851 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z44980:C (r) + 0.392 cell: ADLIB:XAI1 21.243 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z44980:Y (f) + 0.250 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z36 21.493 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40590:A (f) + 0.388 cell: ADLIB:AO1A 21.881 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40590:Y (r) + 1.072 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z35 22.953 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40588:B (r) + 0.423 cell: ADLIB:AO1A 23.376 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40588:Y (r) + 0.249 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z33 23.625 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40558:C (r) + 0.489 cell: ADLIB:AO1A 24.114 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40558:Y (r) + 1.474 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z4 25.588 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40556:B (r) + 0.423 cell: ADLIB:AO1A 26.011 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z40556:Y (r) + 0.238 net: i_adc/adc/rfilt_4_rfi/acc_add19_1i1/nx5238z1 26.249 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z36403:A (r) + 0.297 cell: ADLIB:XNOR3 26.546 i_adc/adc/rfilt_4_rfi/acc_add19_1i1/ix5238z36403:Y (f) + 0.241 net: i_adc/adc/rfilt_4_rfi/acc_1n1s1_18_ 26.787 i_adc/adc/rfilt_4_rfi/ix56958z1959:B (f) + 0.471 cell: ADLIB:AND2A 27.258 i_adc/adc/rfilt_4_rfi/ix56958z1959:Y (f) + 0.241 net: i_adc/adc/rfilt_4_rfi/nx56958z1 27.499 i_adc/adc/rfilt_4_rfi/reg_acc(18):D (f) 27.499 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.163 net: CLK40out 33.790 i_adc/adc/rfilt_4_rfi/reg_acc(18):CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 33.388 i_adc/adc/rfilt_4_rfi/reg_acc(18):D 33.388 data required time Expanded Path 6 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D data required time 33.384 data arrival time - 27.479 slack 5.905 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.182 net: CLK40out 8.809 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.359 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(6):Q (f) + 0.743 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_out_6_ 10.102 i_cbb/scsn_inst_nw_nwl/sl1/ix25761z10876:B (f) + 0.700 cell: ADLIB:XOR2 10.802 i_cbb/scsn_inst_nw_nwl/sl1/ix25761z10876:Y (r) + 0.238 net: i_cbb/scsn_inst_nw_nwl/sl1/nx25761z1 11.040 i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom(0):A (r) + 0.257 cell: ADLIB:XNOR3 11.297 i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom(0):Y (r) + 1.439 net: i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom_0_ 12.736 i_cbb/scsn_inst_nw_nwl/sl1/NOT_current_state(3):A (r) + 0.724 cell: ADLIB:AX1D 13.460 i_cbb/scsn_inst_nw_nwl/sl1/NOT_current_state(3):Y (r) + 0.964 net: i_cbb/scsn_inst_nw_nwl/sl1/NOT_current_state_3_ 14.424 i_cbb/scsn_inst_nw_nwl/sl1/NOT_ix56755z24338:C (r) + 0.561 cell: ADLIB:NAND3 14.985 i_cbb/scsn_inst_nw_nwl/sl1/NOT_ix56755z24338:Y (f) + 0.251 net: i_cbb/scsn_inst_nw_nwl/sl1/nx56755z2 15.236 i_cbb/scsn_inst_nw_nwl/sl1/request_valid:A (f) + 0.365 cell: ADLIB:AND2A 15.601 i_cbb/scsn_inst_nw_nwl/sl1/request_valid:Y (r) + 0.303 net: i_cbb/scsn_inst_nw_nwl/rq1_valid 15.904 i_cbb/scsn_inst_nw_nwl/ix4416z40556:C (r) + 0.572 cell: ADLIB:AO1B 16.476 i_cbb/scsn_inst_nw_nwl/ix4416z40556:Y (f) + 0.239 net: i_cbb/scsn_inst_nw_nwl/nx4416z1 16.715 i_cbb/scsn_inst_nw_nwl/request_valid:C (f) + 0.527 cell: ADLIB:AO1B 17.242 i_cbb/scsn_inst_nw_nwl/request_valid:Y (r) + 0.723 net: i_cbb/scsn_inst_rq_valid 17.965 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (r) + 0.365 cell: ADLIB:XAI1 18.330 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (f) + 0.239 net: i_cbb/scsn_inst_nw_apl/nx4795z6 18.569 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (f) + 0.496 cell: ADLIB:NAND3C 19.065 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (f) + 1.053 net: i_cbb/nx16212z3 20.118 i_cbb/scsn_inst_nw_apl/bridge_alter:A (f) + 0.365 cell: ADLIB:AND2A 20.483 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (r) + 0.371 net: i_cbb/scsn_inst_b_alter 20.854 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (r) + 0.491 cell: ADLIB:MX2B 21.345 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 21.586 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (f) + 0.453 cell: ADLIB:NAND3A 22.039 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 22.288 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (r) + 0.572 cell: ADLIB:AO1E 22.860 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 23.090 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (f) + 0.269 cell: ADLIB:NAND3B 23.359 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (r) + 0.287 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 23.646 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:A (r) + 0.375 cell: ADLIB:AO1C 24.021 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:Y (f) + 0.237 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z5 24.258 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:A (f) + 0.388 cell: ADLIB:AO1A 24.646 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:Y (r) + 0.819 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z4 25.465 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):B (r) + 0.674 cell: ADLIB:OA1A 26.139 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):Y (r) + 0.636 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_1_ 26.775 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):B (r) + 0.463 cell: ADLIB:XOR3 27.238 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_7_ 27.479 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D (f) 27.479 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.185 net: CLK40out 33.812 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.384 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D 33.384 data required time Expanded Path 7 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D data required time 33.354 data arrival time - 27.448 slack 5.906 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.154 net: CLK40out 8.781 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.331 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(0):Q (f) + 0.285 net: i_adc/scsn_slv_nw_nwl/h1_hm_state_out_0_ 9.616 i_adc/scsn_slv_nw_nwl/NOT_h1_b0_h2_syndrom(0):C (f) + 0.562 cell: ADLIB:XNOR3 10.178 i_adc/scsn_slv_nw_nwl/NOT_h1_b0_h2_syndrom(0):Y (r) + 2.280 net: i_adc/scsn_slv_nw_nwl/NOT_h1_b0_h2_syndrom_0_ 12.458 i_adc/scsn_slv_nw_nwl/ix20210z24338:B (r) + 0.441 cell: ADLIB:NAND2 12.899 i_adc/scsn_slv_nw_nwl/ix20210z24338:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/nx20210z1 13.140 i_adc/scsn_slv_nw_nwl/current_state(2):A (f) + 0.535 cell: ADLIB:AX1A 13.675 i_adc/scsn_slv_nw_nwl/current_state(2):Y (r) + 1.142 net: i_adc/scsn_slv_nw_nwl/current_state_2_ 14.817 i_adc/scsn_slv_nw_nwl/ix3798z49935:A (r) + 0.348 cell: ADLIB:NAND2B 15.165 i_adc/scsn_slv_nw_nwl/ix3798z49935:Y (r) + 1.033 net: i_adc/scsn_slv_nw_nwl/nx3798z2 16.198 i_adc/scsn_slv_nw_nwl/ix4416z40556:A (r) + 0.288 cell: ADLIB:AO1B 16.486 i_adc/scsn_slv_nw_nwl/ix4416z40556:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/nx4416z1 16.735 i_adc/scsn_slv_nw_nwl/request_valid:C (r) + 0.572 cell: ADLIB:AO1B 17.307 i_adc/scsn_slv_nw_nwl/request_valid:Y (f) + 0.230 net: i_adc/scsn_slv_rq_valid 17.537 i_adc/scsn_slv_nw_apl/ix4795z44949:C (f) + 0.251 cell: ADLIB:XAI1 17.788 i_adc/scsn_slv_nw_apl/ix4795z44949:Y (r) + 0.303 net: i_adc/scsn_slv_nw_apl/nx4795z6 18.091 i_adc/scsn_slv_nw_apl/ix4795z50946:C (r) + 0.479 cell: ADLIB:NAND3C 18.570 i_adc/scsn_slv_nw_apl/ix4795z50946:Y (r) + 0.918 net: i_adc/nx54487z3 19.488 i_adc/scsn_slv_nw_apl/bridge_alter:A (r) + 0.384 cell: ADLIB:AND2A 19.872 i_adc/scsn_slv_nw_apl/bridge_alter:Y (f) + 0.334 net: i_adc/scsn_slv_b_alter 20.206 i_adc/scsn_slv_nw_nwl/ix51108z26295:B (f) + 0.496 cell: ADLIB:MX2B 20.702 i_adc/scsn_slv_nw_nwl/ix51108z26295:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/nx51108z4 20.951 i_adc/scsn_slv_nw_nwl/ix51108z50932:C (r) + 0.466 cell: ADLIB:NAND3A 21.417 i_adc/scsn_slv_nw_nwl/ix51108z50932:Y (f) + 0.239 net: i_adc/scsn_slv_nw_nwl/nx51108z3 21.656 i_adc/scsn_slv_nw_nwl/reply1_valid:C (f) + 0.526 cell: ADLIB:AO1E 22.182 i_adc/scsn_slv_nw_nwl/reply1_valid:Y (r) + 0.238 net: i_adc/scsn_slv_nw_nwl/reply1_valid 22.420 i_adc/scsn_slv_nw_nwl/sl1/ix3798z50935:C (r) + 0.365 cell: ADLIB:NAND3B 22.785 i_adc/scsn_slv_nw_nwl/sl1/ix3798z50935:Y (f) + 0.902 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z5 23.687 i_adc/scsn_slv_nw_nwl/sl1/ix3798z43529:C (f) + 0.393 cell: ADLIB:XO1A 24.080 i_adc/scsn_slv_nw_nwl/sl1/ix3798z43529:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z4 24.321 i_adc/scsn_slv_nw_nwl/sl1/ix3798z40556:B (f) + 0.454 cell: ADLIB:AO1B 24.775 i_adc/scsn_slv_nw_nwl/sl1/ix3798z40556:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z1 25.016 i_adc/scsn_slv_nw_nwl/sl1/next_state(2):A (f) + 0.735 cell: ADLIB:OA1A 25.751 i_adc/scsn_slv_nw_nwl/sl1/next_state(2):Y (r) + 1.152 net: i_adc/scsn_slv_nw_nwl/sl1/next_state_2_ 26.903 i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in(3):A (r) + 0.297 cell: ADLIB:XOR3 27.200 i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in(3):Y (f) + 0.248 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in_3_ 27.448 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D (f) 27.448 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.155 net: CLK40out 33.782 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.354 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D 33.354 data required time Expanded Path 8 From: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D data required time 33.354 data arrival time - 27.440 slack 5.914 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.148 net: CLK40out 8.775 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(6):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.325 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(6):Q (f) + 0.332 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_out_6_ 9.657 i_adc/scsn_slv_nw_nwl/sl1/ix25804z10876:B (f) + 0.700 cell: ADLIB:XOR2 10.357 i_adc/scsn_slv_nw_nwl/sl1/ix25804z10876:Y (r) + 1.068 net: i_adc/scsn_slv_nw_nwl/sl1/nx25804z1 11.425 i_adc/scsn_slv_nw_nwl/sl1/ix19213z64471:C (r) + 0.522 cell: ADLIB:AOI5 11.947 i_adc/scsn_slv_nw_nwl/sl1/ix19213z64471:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/sl1/nx19213z1 12.196 i_adc/scsn_slv_nw_nwl/sl1/current_state(1):B (r) + 0.748 cell: ADLIB:AX1B 12.944 i_adc/scsn_slv_nw_nwl/sl1/current_state(1):Y (f) + 1.248 net: i_adc/scsn_slv_nw_nwl/sl1/current_state_1_ 14.192 i_adc/scsn_slv_nw_nwl/sl1/NOT_ix56755z24338:B (f) + 0.453 cell: ADLIB:NAND3 14.645 i_adc/scsn_slv_nw_nwl/sl1/NOT_ix56755z24338:Y (r) + 0.238 net: i_adc/scsn_slv_nw_nwl/sl1/nx56755z2 14.883 i_adc/scsn_slv_nw_nwl/sl1/request_valid:A (r) + 0.384 cell: ADLIB:AND2A 15.267 i_adc/scsn_slv_nw_nwl/sl1/request_valid:Y (f) + 0.684 net: i_adc/scsn_slv_nw_nwl/rq1_valid 15.951 i_adc/scsn_slv_nw_nwl/ix4416z40556:C (f) + 0.527 cell: ADLIB:AO1B 16.478 i_adc/scsn_slv_nw_nwl/ix4416z40556:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/nx4416z1 16.727 i_adc/scsn_slv_nw_nwl/request_valid:C (r) + 0.572 cell: ADLIB:AO1B 17.299 i_adc/scsn_slv_nw_nwl/request_valid:Y (f) + 0.230 net: i_adc/scsn_slv_rq_valid 17.529 i_adc/scsn_slv_nw_apl/ix4795z44949:C (f) + 0.251 cell: ADLIB:XAI1 17.780 i_adc/scsn_slv_nw_apl/ix4795z44949:Y (r) + 0.303 net: i_adc/scsn_slv_nw_apl/nx4795z6 18.083 i_adc/scsn_slv_nw_apl/ix4795z50946:C (r) + 0.479 cell: ADLIB:NAND3C 18.562 i_adc/scsn_slv_nw_apl/ix4795z50946:Y (r) + 0.918 net: i_adc/nx54487z3 19.480 i_adc/scsn_slv_nw_apl/bridge_alter:A (r) + 0.384 cell: ADLIB:AND2A 19.864 i_adc/scsn_slv_nw_apl/bridge_alter:Y (f) + 0.334 net: i_adc/scsn_slv_b_alter 20.198 i_adc/scsn_slv_nw_nwl/ix51108z26295:B (f) + 0.496 cell: ADLIB:MX2B 20.694 i_adc/scsn_slv_nw_nwl/ix51108z26295:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/nx51108z4 20.943 i_adc/scsn_slv_nw_nwl/ix51108z50932:C (r) + 0.466 cell: ADLIB:NAND3A 21.409 i_adc/scsn_slv_nw_nwl/ix51108z50932:Y (f) + 0.239 net: i_adc/scsn_slv_nw_nwl/nx51108z3 21.648 i_adc/scsn_slv_nw_nwl/reply1_valid:C (f) + 0.526 cell: ADLIB:AO1E 22.174 i_adc/scsn_slv_nw_nwl/reply1_valid:Y (r) + 0.238 net: i_adc/scsn_slv_nw_nwl/reply1_valid 22.412 i_adc/scsn_slv_nw_nwl/sl1/ix3798z50935:C (r) + 0.365 cell: ADLIB:NAND3B 22.777 i_adc/scsn_slv_nw_nwl/sl1/ix3798z50935:Y (f) + 0.902 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z5 23.679 i_adc/scsn_slv_nw_nwl/sl1/ix3798z43529:C (f) + 0.393 cell: ADLIB:XO1A 24.072 i_adc/scsn_slv_nw_nwl/sl1/ix3798z43529:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z4 24.313 i_adc/scsn_slv_nw_nwl/sl1/ix3798z40556:B (f) + 0.454 cell: ADLIB:AO1B 24.767 i_adc/scsn_slv_nw_nwl/sl1/ix3798z40556:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z1 25.008 i_adc/scsn_slv_nw_nwl/sl1/next_state(2):A (f) + 0.735 cell: ADLIB:OA1A 25.743 i_adc/scsn_slv_nw_nwl/sl1/next_state(2):Y (r) + 1.152 net: i_adc/scsn_slv_nw_nwl/sl1/next_state_2_ 26.895 i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in(3):A (r) + 0.297 cell: ADLIB:XOR3 27.192 i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in(3):Y (f) + 0.248 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in_3_ 27.440 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D (f) 27.440 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.155 net: CLK40out 33.782 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.354 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D 33.354 data required time Expanded Path 9 From: i_adc/adc/adci/reg_adc(0):CLK To: i_adc/adc/rfilt_5_rfi/reg_acc(17):D data required time 33.357 data arrival time - 27.409 slack 5.948 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.166 net: CLK40out 8.793 i_adc/adc/adci/reg_adc(0):CLK (r) + 0.550 cell: ADLIB:DFN1E1 9.343 i_adc/adc/adci/reg_adc(0):Q (f) + 1.242 net: i_adc/adc/dout_0_ 10.585 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z49948:A (f) + 0.485 cell: ADLIB:NAND2A 11.070 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z49948:Y (f) + 0.286 net: i_adc/adc/rfilt_5_rfi/diff_sub12_0/nx63795z15 11.356 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z40555:B (f) + 0.735 cell: ADLIB:AO13 12.091 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z40555:Y (f) + 0.332 net: i_adc/adc/rfilt_5_rfi/diff_sub12_0/nx63795z14 12.423 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z40566:B (f) + 0.475 cell: ADLIB:AO1A 12.898 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z40566:Y (f) + 1.369 net: i_adc/adc/rfilt_5_rfi/diff_sub12_0/nx63795z11 14.267 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z40560:B (f) + 0.447 cell: ADLIB:AO1A 14.714 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix63795z40560:Y (f) + 0.781 net: i_adc/adc/rfilt_5_rfi/diff_sub12_0/nx63795z5 15.495 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix46946z40542:A (f) + 0.793 cell: ADLIB:AO13 16.288 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix46946z40542:Y (f) + 0.239 net: i_adc/adc/rfilt_5_rfi/diff_sub12_0/nx46946z1 16.527 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix46946z36403:C (f) + 0.652 cell: ADLIB:XNOR3 17.179 i_adc/adc/rfilt_5_rfi/diff_sub12_0/ix46946z36403:Y (r) + 0.303 net: i_adc/adc/rfilt_5_rfi/diff_9_ 17.482 i_adc/adc/rfilt_5_rfi/diffe_mux_0Bus3(10)_ix23050z14896:A (r) + 0.497 cell: ADLIB:MX2 17.979 i_adc/adc/rfilt_5_rfi/diffe_mux_0Bus3(10)_ix23050z14896:Y (r) + 0.303 net: i_adc/adc/rfilt_5_rfi/nx23050z1 18.282 i_adc/adc/rfilt_5_rfi/diffe(10):B (r) + 0.437 cell: ADLIB:MX2 18.719 i_adc/adc/rfilt_5_rfi/diffe(10):Y (r) + 1.587 net: i_adc/adc/rfilt_5_rfi/diffe_10_ 20.306 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z10885:B (r) + 0.496 cell: ADLIB:XOR2 20.802 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z10885:Y (r) + 0.290 net: i_adc/adc/rfilt_5_rfi/acc_add19_1i1/nx5238z10 21.092 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z44980:C (r) + 0.392 cell: ADLIB:XAI1 21.484 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z44980:Y (f) + 0.230 net: i_adc/adc/rfilt_5_rfi/acc_add19_1i1/nx5238z36 21.714 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z40590:A (f) + 0.388 cell: ADLIB:AO1A 22.102 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z40590:Y (r) + 0.905 net: i_adc/adc/rfilt_5_rfi/acc_add19_1i1/nx5238z35 23.007 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z40588:B (r) + 0.423 cell: ADLIB:AO1A 23.430 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z40588:Y (r) + 0.252 net: i_adc/adc/rfilt_5_rfi/acc_add19_1i1/nx5238z33 23.682 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z40558:C (r) + 0.489 cell: ADLIB:AO1A 24.171 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix5238z40558:Y (r) + 0.949 net: i_adc/adc/rfilt_5_rfi/acc_add19_1i1/nx5238z4 25.120 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix4241z40542:A (r) + 0.567 cell: ADLIB:AO13 25.687 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix4241z40542:Y (r) + 0.249 net: i_adc/adc/rfilt_5_rfi/acc_add19_1i1/nx4241z1 25.936 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix4241z36403:B (r) + 0.534 cell: ADLIB:XNOR3 26.470 i_adc/adc/rfilt_5_rfi/acc_add19_1i1/ix4241z36403:Y (r) + 0.249 net: i_adc/adc/rfilt_5_rfi/acc_1n1s1_17_ 26.719 i_adc/adc/rfilt_5_rfi/ix57955z1959:B (r) + 0.441 cell: ADLIB:AND2A 27.160 i_adc/adc/rfilt_5_rfi/ix57955z1959:Y (r) + 0.249 net: i_adc/adc/rfilt_5_rfi/nx57955z1 27.409 i_adc/adc/rfilt_5_rfi/reg_acc(17):D (r) 27.409 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.158 net: CLK40out 33.785 i_adc/adc/rfilt_5_rfi/reg_acc(17):CLK (r) - 0.428 Library setup time: ADLIB:DFN1E1 33.357 i_adc/adc/rfilt_5_rfi/reg_acc(17):D 33.357 data required time Expanded Path 10 From: i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(2):CLK To: i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D data required time 33.354 data arrival time - 27.360 slack 5.994 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.153 net: CLK40out 8.780 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(2):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.330 i_adc/scsn_slv_nw_nwl/h1_reg_hm_state_out(2):Q (f) + 0.285 net: i_adc/scsn_slv_nw_nwl/h1_hm_state_out_2_ 9.615 i_adc/scsn_slv_nw_nwl/NOT_h1_b0_h2_syndrom(0):B (f) + 0.475 cell: ADLIB:XNOR3 10.090 i_adc/scsn_slv_nw_nwl/NOT_h1_b0_h2_syndrom(0):Y (r) + 2.280 net: i_adc/scsn_slv_nw_nwl/NOT_h1_b0_h2_syndrom_0_ 12.370 i_adc/scsn_slv_nw_nwl/ix20210z24338:B (r) + 0.441 cell: ADLIB:NAND2 12.811 i_adc/scsn_slv_nw_nwl/ix20210z24338:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/nx20210z1 13.052 i_adc/scsn_slv_nw_nwl/current_state(2):A (f) + 0.535 cell: ADLIB:AX1A 13.587 i_adc/scsn_slv_nw_nwl/current_state(2):Y (r) + 1.142 net: i_adc/scsn_slv_nw_nwl/current_state_2_ 14.729 i_adc/scsn_slv_nw_nwl/ix3798z49935:A (r) + 0.348 cell: ADLIB:NAND2B 15.077 i_adc/scsn_slv_nw_nwl/ix3798z49935:Y (r) + 1.033 net: i_adc/scsn_slv_nw_nwl/nx3798z2 16.110 i_adc/scsn_slv_nw_nwl/ix4416z40556:A (r) + 0.288 cell: ADLIB:AO1B 16.398 i_adc/scsn_slv_nw_nwl/ix4416z40556:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/nx4416z1 16.647 i_adc/scsn_slv_nw_nwl/request_valid:C (r) + 0.572 cell: ADLIB:AO1B 17.219 i_adc/scsn_slv_nw_nwl/request_valid:Y (f) + 0.230 net: i_adc/scsn_slv_rq_valid 17.449 i_adc/scsn_slv_nw_apl/ix4795z44949:C (f) + 0.251 cell: ADLIB:XAI1 17.700 i_adc/scsn_slv_nw_apl/ix4795z44949:Y (r) + 0.303 net: i_adc/scsn_slv_nw_apl/nx4795z6 18.003 i_adc/scsn_slv_nw_apl/ix4795z50946:C (r) + 0.479 cell: ADLIB:NAND3C 18.482 i_adc/scsn_slv_nw_apl/ix4795z50946:Y (r) + 0.918 net: i_adc/nx54487z3 19.400 i_adc/scsn_slv_nw_apl/bridge_alter:A (r) + 0.384 cell: ADLIB:AND2A 19.784 i_adc/scsn_slv_nw_apl/bridge_alter:Y (f) + 0.334 net: i_adc/scsn_slv_b_alter 20.118 i_adc/scsn_slv_nw_nwl/ix51108z26295:B (f) + 0.496 cell: ADLIB:MX2B 20.614 i_adc/scsn_slv_nw_nwl/ix51108z26295:Y (r) + 0.249 net: i_adc/scsn_slv_nw_nwl/nx51108z4 20.863 i_adc/scsn_slv_nw_nwl/ix51108z50932:C (r) + 0.466 cell: ADLIB:NAND3A 21.329 i_adc/scsn_slv_nw_nwl/ix51108z50932:Y (f) + 0.239 net: i_adc/scsn_slv_nw_nwl/nx51108z3 21.568 i_adc/scsn_slv_nw_nwl/reply1_valid:C (f) + 0.526 cell: ADLIB:AO1E 22.094 i_adc/scsn_slv_nw_nwl/reply1_valid:Y (r) + 0.238 net: i_adc/scsn_slv_nw_nwl/reply1_valid 22.332 i_adc/scsn_slv_nw_nwl/sl1/ix3798z50935:C (r) + 0.365 cell: ADLIB:NAND3B 22.697 i_adc/scsn_slv_nw_nwl/sl1/ix3798z50935:Y (f) + 0.902 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z5 23.599 i_adc/scsn_slv_nw_nwl/sl1/ix3798z43529:C (f) + 0.393 cell: ADLIB:XO1A 23.992 i_adc/scsn_slv_nw_nwl/sl1/ix3798z43529:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z4 24.233 i_adc/scsn_slv_nw_nwl/sl1/ix3798z40556:B (f) + 0.454 cell: ADLIB:AO1B 24.687 i_adc/scsn_slv_nw_nwl/sl1/ix3798z40556:Y (f) + 0.241 net: i_adc/scsn_slv_nw_nwl/sl1/nx3798z1 24.928 i_adc/scsn_slv_nw_nwl/sl1/next_state(2):A (f) + 0.735 cell: ADLIB:OA1A 25.663 i_adc/scsn_slv_nw_nwl/sl1/next_state(2):Y (r) + 1.152 net: i_adc/scsn_slv_nw_nwl/sl1/next_state_2_ 26.815 i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in(3):A (r) + 0.297 cell: ADLIB:XOR3 27.112 i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in(3):Y (f) + 0.248 net: i_adc/scsn_slv_nw_nwl/sl1/h1_hm_state_in_3_ 27.360 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D (f) 27.360 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.155 net: CLK40out 33.782 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 33.354 i_adc/scsn_slv_nw_nwl/sl1/h1_reg_hm_state_out(3):D 33.354 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 Delay (ns): 17.072 Slack (ns): Arrival (ns): 17.072 Required (ns): Setup (ns): 0.209 External Setup (ns): 8.303 Path 2 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 Delay (ns): 17.043 Slack (ns): Arrival (ns): 17.043 Required (ns): Setup (ns): 0.209 External Setup (ns): 8.274 Path 3 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 Delay (ns): 16.558 Slack (ns): Arrival (ns): 16.558 Required (ns): Setup (ns): 0.209 External Setup (ns): 7.779 Path 4 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 Delay (ns): 16.529 Slack (ns): Arrival (ns): 16.529 Required (ns): Setup (ns): 0.209 External Setup (ns): 7.750 Path 5 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 Delay (ns): 16.490 Slack (ns): Arrival (ns): 16.490 Required (ns): Setup (ns): 0.209 External Setup (ns): 7.721 Path 6 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 Delay (ns): 16.461 Slack (ns): Arrival (ns): 16.461 Required (ns): Setup (ns): 0.209 External Setup (ns): 7.692 Path 7 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 Delay (ns): 15.887 Slack (ns): Arrival (ns): 15.887 Required (ns): Setup (ns): 0.209 External Setup (ns): 7.108 Path 8 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 Delay (ns): 15.858 Slack (ns): Arrival (ns): 15.858 Required (ns): Setup (ns): 0.209 External Setup (ns): 7.079 Path 9 From: TLMU_n(7) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB4 Delay (ns): 15.175 Slack (ns): Arrival (ns): 15.175 Required (ns): Setup (ns): 0.209 External Setup (ns): 6.396 Path 10 From: TLMU_n(7) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB4 Delay (ns): 15.151 Slack (ns): Arrival (ns): 15.151 Required (ns): Setup (ns): 0.209 External Setup (ns): 6.382 Expanded Path 1 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 data required time N/C data arrival time - 17.072 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(6) (r) + 0.000 net: TLMU_n_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.718 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.215 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.464 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.888 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.835 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.259 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 5.813 net: i_cbb/pt_trg_ctb_8_ 17.072 i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 (r) 17.072 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.351 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 Expanded Path 2 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 data required time N/C data arrival time - 17.043 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(6) (r) + 0.000 net: TLMU_p_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:PAD (r) + 3.444 cell: ADLIB:IOPADP_IN 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.476 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.689 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.186 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.435 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.859 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.806 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.230 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 5.813 net: i_cbb/pt_trg_ctb_8_ 17.043 i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 (r) 17.043 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.351 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB3 Expanded Path 3 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 data required time N/C data arrival time - 16.558 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(6) (r) + 0.000 net: TLMU_n_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.718 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.215 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.464 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.888 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.835 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.259 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 5.299 net: i_cbb/pt_trg_ctb_8_ 16.558 i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 (r) 16.558 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.361 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 Expanded Path 4 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 data required time N/C data arrival time - 16.529 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(6) (r) + 0.000 net: TLMU_p_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:PAD (r) + 3.444 cell: ADLIB:IOPADP_IN 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.476 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.689 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.186 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.435 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.859 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.806 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.230 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 5.299 net: i_cbb/pt_trg_ctb_8_ 16.529 i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 (r) 16.529 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.361 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_0_r4k9_ram:ADDRB3 Expanded Path 5 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 data required time N/C data arrival time - 16.490 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(6) (r) + 0.000 net: TLMU_n_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.718 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.215 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.464 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.888 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.835 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.259 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 5.231 net: i_cbb/pt_trg_ctb_8_ 16.490 i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 (r) 16.490 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.351 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 Expanded Path 6 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 data required time N/C data arrival time - 16.461 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(6) (r) + 0.000 net: TLMU_p_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:PAD (r) + 3.444 cell: ADLIB:IOPADP_IN 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.476 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.689 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.186 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.435 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.859 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.806 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.230 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 5.231 net: i_cbb/pt_trg_ctb_8_ 16.461 i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 (r) 16.461 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.351 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_2_r4k9_ram:ADDRB3 Expanded Path 7 From: TLMU_n(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 data required time N/C data arrival time - 15.887 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(6) (r) + 0.000 net: TLMU_n_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.718 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.215 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.464 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.888 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.835 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.259 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 4.628 net: i_cbb/pt_trg_ctb_8_ 15.887 i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 (r) 15.887 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.361 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 Expanded Path 8 From: TLMU_p(6) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 data required time N/C data arrival time - 15.858 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(6) (r) + 0.000 net: TLMU_p_6_ 0.000 tlmu_in[6].lvds_TLMU_U1/U0/U0:PAD (r) + 3.444 cell: ADLIB:IOPADP_IN 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[6]_lvds_TLMU_U1/U0/NET1 3.444 tlmu_in[6].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.476 tlmu_in[6].lvds_TLMU_U1/U0/U1:Y (r) + 5.213 net: TLMU_i_6_ 8.689 i_cbb/pt_align_inst/ix11934z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.186 i_cbb/pt_align_inst/ix11934z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx11934z2 9.435 i_cbb/pt_align_inst/ix11934z14896:A (r) + 0.424 cell: ADLIB:MX2 9.859 i_cbb/pt_align_inst/ix11934z14896:Y (r) + 0.947 net: i_cbb/pt_align_inst/nx11934z1 10.806 i_cbb/pt_align_inst/trg_ctb(8):A (r) + 0.424 cell: ADLIB:MX2 11.230 i_cbb/pt_align_inst/trg_ctb(8):Y (r) + 4.628 net: i_cbb/pt_trg_ctb_8_ 15.858 i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 (r) 15.858 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.361 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB3 Expanded Path 9 From: TLMU_n(7) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB4 data required time N/C data arrival time - 15.175 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(7) (r) + 0.000 net: TLMU_n_7_ 0.000 tlmu_in[7].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[7].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[7]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[7].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[7].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[7]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[7].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[7].lvds_TLMU_U1/U0/U1:Y (r) + 5.485 net: TLMU_i_7_ 8.990 i_cbb/pt_align_inst/ix12931z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.487 i_cbb/pt_align_inst/ix12931z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx12931z2 9.736 i_cbb/pt_align_inst/ix12931z14896:A (r) + 0.424 cell: ADLIB:MX2 10.160 i_cbb/pt_align_inst/ix12931z14896:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx12931z1 10.409 i_cbb/pt_align_inst/trg_ctb(9):A (r) + 0.424 cell: ADLIB:MX2 10.833 i_cbb/pt_align_inst/trg_ctb(9):Y (r) + 4.342 net: i_cbb/pt_trg_ctb_9_ 15.175 i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB4 (r) 15.175 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.361 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_3_r4k9_ram:ADDRB4 Expanded Path 10 From: TLMU_n(7) To: i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB4 data required time N/C data arrival time - 15.151 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(7) (r) + 0.000 net: TLMU_n_7_ 0.000 tlmu_in[7].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[7].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[7]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[7].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[7].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[7]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[7].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[7].lvds_TLMU_U1/U0/U1:Y (r) + 5.485 net: TLMU_i_7_ 8.990 i_cbb/pt_align_inst/ix12931z40556:B (r) + 0.497 cell: ADLIB:AO1A 9.487 i_cbb/pt_align_inst/ix12931z40556:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx12931z2 9.736 i_cbb/pt_align_inst/ix12931z14896:A (r) + 0.424 cell: ADLIB:MX2 10.160 i_cbb/pt_align_inst/ix12931z14896:Y (r) + 0.249 net: i_cbb/pt_align_inst/nx12931z1 10.409 i_cbb/pt_align_inst/trg_ctb(9):A (r) + 0.424 cell: ADLIB:MX2 10.833 i_cbb/pt_align_inst/trg_ctb(9):Y (r) + 4.318 net: i_cbb/pt_trg_ctb_9_ 15.151 i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB4 (r) 15.151 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.351 net: CLK40out N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:CLKB (r) - 0.209 Library setup time: ADLIB:RAM4K9 N/C i_cbb/trg_lut_inst/bram_lut_inst_iram_1_r4k9_ram:ADDRB4 END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: RESET_TOFFPGA Delay (ns): 15.151 Slack (ns): Arrival (ns): 23.945 Required (ns): Clock to Out (ns): 23.945 Path 2 From: i_cbb/sys_config0/reg_cbb_ctrl_i(1):CLK To: RESET_TOFFPGA Delay (ns): 12.598 Slack (ns): Arrival (ns): 21.370 Required (ns): Clock to Out (ns): 21.370 Path 3 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: CNRRL Delay (ns): 11.138 Slack (ns): Arrival (ns): 19.950 Required (ns): Clock to Out (ns): 19.950 Path 4 From: i_adc/adc/adci/reg_spi_cnv_i:CLK To: ADC_CSn Delay (ns): 9.768 Slack (ns): Arrival (ns): 18.554 Required (ns): Clock to Out (ns): 18.554 Path 5 From: i_adc/sfp_rd_reg_SFP_SDA_o_i:CLK To: SIU_SDA Delay (ns): 9.766 Slack (ns): Arrival (ns): 18.551 Required (ns): Clock to Out (ns): 18.551 Path 6 From: i_adc/adc/adci/reg_addr(4):CLK To: ADC_SDI Delay (ns): 9.357 Slack (ns): Arrival (ns): 18.157 Required (ns): Clock to Out (ns): 18.157 Path 7 From: i_adc/sfp_rd_reg_SFP_SCL_i:CLK To: SIU_SCL Delay (ns): 9.339 Slack (ns): Arrival (ns): 18.132 Required (ns): Clock to Out (ns): 18.132 Path 8 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA Delay (ns): 9.248 Slack (ns): Arrival (ns): 18.025 Required (ns): Clock to Out (ns): 18.025 Path 9 From: i_adc/adc/adci/reg_spi_clk_i:CLK To: ADC_SCLK Delay (ns): 8.645 Slack (ns): Arrival (ns): 17.412 Required (ns): Clock to Out (ns): 17.412 Path 10 From: i_cbb/ttcex_out_inst_reg_b_channel_out:CLK To: B_ECL Delay (ns): 8.484 Slack (ns): Arrival (ns): 17.257 Required (ns): Clock to Out (ns): 17.257 Expanded Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: RESET_TOFFPGA data required time N/C data arrival time - 23.945 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 5.435 net: i_cbb/rst_scsn 14.779 i_cbb/ix26613z10876:B (f) + 0.737 cell: ADLIB:XOR2 15.516 i_cbb/ix26613z10876:Y (f) + 3.438 net: RST2FPGA_i 18.954 obuf_RST2FPGA_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 19.446 obuf_RST2FPGA_U1/U0/U1:DOUT (f) + 0.000 net: obuf_RST2FPGA_U1/U0/NET1 19.446 obuf_RST2FPGA_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 23.945 obuf_RST2FPGA_U1/U0/U0:PAD (f) + 0.000 net: RESET_TOFFPGA 23.945 RESET_TOFFPGA (f) 23.945 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C RESET_TOFFPGA (f) Expanded Path 2 From: i_cbb/sys_config0/reg_cbb_ctrl_i(1):CLK To: RESET_TOFFPGA data required time N/C data arrival time - 21.370 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.145 net: CLK40out 8.772 i_cbb/sys_config0/reg_cbb_ctrl_i(1):CLK (r) + 0.550 cell: ADLIB:DFN1E1 9.322 i_cbb/sys_config0/reg_cbb_ctrl_i(1):Q (f) + 3.228 net: i_cbb/cbb_ctrl_1_ 12.550 i_cbb/ix26613z10876:A (f) + 0.391 cell: ADLIB:XOR2 12.941 i_cbb/ix26613z10876:Y (f) + 3.438 net: RST2FPGA_i 16.379 obuf_RST2FPGA_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 16.871 obuf_RST2FPGA_U1/U0/U1:DOUT (f) + 0.000 net: obuf_RST2FPGA_U1/U0/NET1 16.871 obuf_RST2FPGA_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 21.370 obuf_RST2FPGA_U1/U0/U0:PAD (f) + 0.000 net: RESET_TOFFPGA 21.370 RESET_TOFFPGA (f) 21.370 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C RESET_TOFFPGA (f) Expanded Path 3 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: CNRRL data required time N/C data arrival time - 19.950 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.185 net: CLK40out 8.812 i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK (r) + 0.550 cell: ADLIB:DFN1E1 9.362 i_cbb/sys_config0/reg_cbb_ctrl_i(0):Q (f) + 5.654 net: CNRRL_i 15.016 obuf_CNRRL_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 15.451 obuf_CNRRL_U1/U0/U1:DOUT (f) + 0.000 net: obuf_CNRRL_U1/U0/NET1 15.451 obuf_CNRRL_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 19.950 obuf_CNRRL_U1/U0/U0:PAD (f) + 0.000 net: CNRRL 19.950 CNRRL (f) 19.950 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C CNRRL (f) Expanded Path 4 From: i_adc/adc/adci/reg_spi_cnv_i:CLK To: ADC_CSn data required time N/C data arrival time - 18.554 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.159 net: CLK40out 8.786 i_adc/adc/adci/reg_spi_cnv_i:CLK (r) + 0.550 cell: ADLIB:DFN1 9.336 i_adc/adc/adci/reg_spi_cnv_i:Q (f) + 3.725 net: ADC_CSn_i 13.061 obuf_ADC_CSn_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 13.496 obuf_ADC_CSn_U1/U0/U1:DOUT (f) + 0.000 net: obuf_ADC_CSn_U1/U0/NET1 13.496 obuf_ADC_CSn_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 18.554 obuf_ADC_CSn_U1/U0/U0:PAD (f) + 0.000 net: ADC_CSn 18.554 ADC_CSn (f) 18.554 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C ADC_CSn (f) Expanded Path 5 From: i_adc/sfp_rd_reg_SFP_SDA_o_i:CLK To: SIU_SDA data required time N/C data arrival time - 18.551 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.158 net: CLK40out 8.785 i_adc/sfp_rd_reg_SFP_SDA_o_i:CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.335 i_adc/sfp_rd_reg_SFP_SDA_o_i:Q (f) + 4.225 net: SIU_SDA_o 13.560 bbuf_SIU_SDA/U0/U1:D (f) + 0.492 cell: ADLIB:IOBI_IB_OB_EB 14.052 bbuf_SIU_SDA/U0/U1:DOUT (f) + 0.000 net: bbuf_SIU_SDA/U0/NET1 14.052 bbuf_SIU_SDA/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_BI 18.551 bbuf_SIU_SDA/U0/U0:PAD (f) + 0.000 net: SIU_SDA 18.551 SIU_SDA (f) 18.551 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C SIU_SDA (f) Expanded Path 6 From: i_adc/adc/adci/reg_addr(4):CLK To: ADC_SDI data required time N/C data arrival time - 18.157 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.173 net: CLK40out 8.800 i_adc/adc/adci/reg_addr(4):CLK (r) + 0.550 cell: ADLIB:DFN1E1 9.350 i_adc/adc/adci/reg_addr(4):Q (f) + 3.873 net: ADC_SDI_i 13.223 obuf_ADC_SDI_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 13.658 obuf_ADC_SDI_U1/U0/U1:DOUT (f) + 0.000 net: obuf_ADC_SDI_U1/U0/NET1 13.658 obuf_ADC_SDI_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 18.157 obuf_ADC_SDI_U1/U0/U0:PAD (f) + 0.000 net: ADC_SDI 18.157 ADC_SDI (f) 18.157 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C ADC_SDI (f) Expanded Path 7 From: i_adc/sfp_rd_reg_SFP_SCL_i:CLK To: SIU_SCL data required time N/C data arrival time - 18.132 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.166 net: CLK40out 8.793 i_adc/sfp_rd_reg_SFP_SCL_i:CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.343 i_adc/sfp_rd_reg_SFP_SCL_i:Q (f) + 3.798 net: SIU_SCL_i 13.141 obuf_SIU_SCL_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 13.633 obuf_SIU_SCL_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SIU_SCL_U1/U0/NET1 13.633 obuf_SIU_SCL_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 18.132 obuf_SIU_SCL_U1/U0/U0:PAD (f) + 0.000 net: SIU_SCL 18.132 SIU_SCL (f) 18.132 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C SIU_SCL (f) Expanded Path 8 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA data required time N/C data arrival time - 18.025 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.150 net: CLK40out 8.777 i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK (r) + 0.434 cell: ADLIB:DFN1C1 9.211 i_adc/sfp_rd_reg_SFP_SDA_e_i:Q (r) + 3.882 net: SIU_SDA_e 13.093 bbuf_SIU_SDA/U0/U1:E (r) + 0.349 cell: ADLIB:IOBI_IB_OB_EB 13.442 bbuf_SIU_SDA/U0/U1:EOUT (r) + 0.000 net: bbuf_SIU_SDA/U0/NET2 13.442 bbuf_SIU_SDA/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 18.025 bbuf_SIU_SDA/U0/U0:PAD (f) + 0.000 net: SIU_SDA 18.025 SIU_SDA (f) 18.025 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C SIU_SDA (f) Expanded Path 9 From: i_adc/adc/adci/reg_spi_clk_i:CLK To: ADC_SCLK data required time N/C data arrival time - 17.412 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.140 net: CLK40out 8.767 i_adc/adc/adci/reg_spi_clk_i:CLK (r) + 0.550 cell: ADLIB:DFN1 9.317 i_adc/adc/adci/reg_spi_clk_i:Q (f) + 3.161 net: ADC_SCLK_i 12.478 obuf_ADC_SCLK_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 12.913 obuf_ADC_SCLK_U1/U0/U1:DOUT (f) + 0.000 net: obuf_ADC_SCLK_U1/U0/NET1 12.913 obuf_ADC_SCLK_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 17.412 obuf_ADC_SCLK_U1/U0/U0:PAD (f) + 0.000 net: ADC_SCLK 17.412 ADC_SCLK (f) 17.412 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C ADC_SCLK (f) Expanded Path 10 From: i_cbb/ttcex_out_inst_reg_b_channel_out:CLK To: B_ECL data required time N/C data arrival time - 17.257 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.146 net: CLK40out 8.773 i_cbb/ttcex_out_inst_reg_b_channel_out:CLK (r) + 0.550 cell: ADLIB:DFN1 9.323 i_cbb/ttcex_out_inst_reg_b_channel_out:Q (f) + 4.760 net: B_ECL_i 14.083 obuf_B_ECL_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 14.518 obuf_B_ECL_U1/U0/U1:DOUT (f) + 0.000 net: obuf_B_ECL_U1/U0/NET1 14.518 obuf_B_ECL_U1/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 17.257 obuf_B_ECL_U1/U0/U0:PAD (f) + 0.000 net: B_ECL 17.257 B_ECL (f) 17.257 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C N/C B_ECL (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(0):CLR Delay (ns): 10.142 Slack (ns): 14.671 Arrival (ns): 18.936 Required (ns): 33.607 Recovery (ns): 0.222 Minimum Period (ns): 10.329 Skew (ns): -0.035 Path 2 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(2):CLR Delay (ns): 9.888 Slack (ns): 14.915 Arrival (ns): 18.682 Required (ns): 33.597 Recovery (ns): 0.222 Minimum Period (ns): 10.085 Skew (ns): -0.025 Path 3 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(2):CLR Delay (ns): 9.864 Slack (ns): 14.944 Arrival (ns): 18.658 Required (ns): 33.602 Recovery (ns): 0.222 Minimum Period (ns): 10.056 Skew (ns): -0.030 Path 4 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_receiving:CLR Delay (ns): 9.769 Slack (ns): 15.001 Arrival (ns): 18.563 Required (ns): 33.564 Recovery (ns): 0.222 Minimum Period (ns): 9.999 Skew (ns): 0.008 Path 5 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ob0/reg_ob_data(16):CLR Delay (ns): 9.800 Slack (ns): 15.003 Arrival (ns): 18.594 Required (ns): 33.597 Recovery (ns): 0.222 Minimum Period (ns): 9.997 Skew (ns): -0.025 Path 6 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ib1/reg_b_data(60):CLR Delay (ns): 9.650 Slack (ns): 15.153 Arrival (ns): 18.444 Required (ns): 33.597 Recovery (ns): 0.222 Minimum Period (ns): 9.847 Skew (ns): -0.025 Path 7 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(3):CLR Delay (ns): 9.614 Slack (ns): 15.188 Arrival (ns): 18.408 Required (ns): 33.596 Recovery (ns): 0.222 Minimum Period (ns): 9.812 Skew (ns): -0.024 Path 8 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(1):CLR Delay (ns): 9.620 Slack (ns): 15.193 Arrival (ns): 18.414 Required (ns): 33.607 Recovery (ns): 0.222 Minimum Period (ns): 9.807 Skew (ns): -0.035 Path 9 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(3):CLR Delay (ns): 9.600 Slack (ns): 15.203 Arrival (ns): 18.394 Required (ns): 33.597 Recovery (ns): 0.222 Minimum Period (ns): 9.797 Skew (ns): -0.025 Path 10 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_apl/modgen_counter_waitcount_reg_q(5):CLR Delay (ns): 9.567 Slack (ns): 15.239 Arrival (ns): 18.361 Required (ns): 33.600 Recovery (ns): 0.222 Minimum Period (ns): 9.761 Skew (ns): -0.028 Expanded Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/sys_config0/reg_syscfg_wdata_r(0):CLR data required time 33.607 data arrival time - 18.936 slack 14.671 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.592 net: i_cbb/rst_scsn 18.936 i_cbb/sys_config0/reg_syscfg_wdata_r(0):CLR (f) 18.936 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.202 net: CLK40out 33.829 i_cbb/sys_config0/reg_syscfg_wdata_r(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.607 i_cbb/sys_config0/reg_syscfg_wdata_r(0):CLR 33.607 data required time Expanded Path 2 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(2):CLR data required time 33.597 data arrival time - 18.682 slack 14.915 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.338 net: i_cbb/rst_scsn 18.682 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(2):CLR (f) 18.682 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.192 net: CLK40out 33.819 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(2):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.597 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(2):CLR 33.597 data required time Expanded Path 3 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(2):CLR data required time 33.602 data arrival time - 18.658 slack 14.944 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.314 net: i_cbb/rst_scsn 18.658 i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(2):CLR (f) 18.658 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.197 net: CLK40out 33.824 i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(2):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.602 i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(2):CLR 33.602 data required time Expanded Path 4 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_receiving:CLR data required time 33.564 data arrival time - 18.563 slack 15.001 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.219 net: i_cbb/rst_scsn 18.563 i_cbb/cbbr_top_1/reg_receiving:CLR (f) 18.563 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.159 net: CLK40out 33.786 i_cbb/cbbr_top_1/reg_receiving:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.564 i_cbb/cbbr_top_1/reg_receiving:CLR 33.564 data required time Expanded Path 5 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ob0/reg_ob_data(16):CLR data required time 33.597 data arrival time - 18.594 slack 15.003 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.250 net: i_cbb/rst_scsn 18.594 i_cbb/scsn_inst_nw_dll_ob0/reg_ob_data(16):CLR (f) 18.594 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.192 net: CLK40out 33.819 i_cbb/scsn_inst_nw_dll_ob0/reg_ob_data(16):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.597 i_cbb/scsn_inst_nw_dll_ob0/reg_ob_data(16):CLR 33.597 data required time Expanded Path 6 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_dll_ib1/reg_b_data(60):CLR data required time 33.597 data arrival time - 18.444 slack 15.153 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.100 net: i_cbb/rst_scsn 18.444 i_cbb/scsn_inst_nw_dll_ib1/reg_b_data(60):CLR (f) 18.444 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.192 net: CLK40out 33.819 i_cbb/scsn_inst_nw_dll_ib1/reg_b_data(60):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.597 i_cbb/scsn_inst_nw_dll_ib1/reg_b_data(60):CLR 33.597 data required time Expanded Path 7 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(3):CLR data required time 33.596 data arrival time - 18.408 slack 15.188 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.064 net: i_cbb/rst_scsn 18.408 i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(3):CLR (f) 18.408 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.191 net: CLK40out 33.818 i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.596 i_cbb/cbbr_top_1/sfrs_1_cbbr_iserdes_1_reg_sfr(3):CLR 33.596 data required time Expanded Path 8 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(1):CLR data required time 33.607 data arrival time - 18.414 slack 15.193 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.070 net: i_cbb/rst_scsn 18.414 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(1):CLR (f) 18.414 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.202 net: CLK40out 33.829 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.607 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(1):CLR 33.607 data required time Expanded Path 9 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(3):CLR data required time 33.597 data arrival time - 18.394 slack 15.203 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.050 net: i_cbb/rst_scsn 18.394 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(3):CLR (f) 18.394 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.192 net: CLK40out 33.819 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.597 i_cbb/cbbr_top_1/modgen_counter_sample_cnt_reg_q(3):CLR 33.597 data required time Expanded Path 10 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/scsn_inst_nw_apl/modgen_counter_waitcount_reg_q(5):CLR data required time 33.600 data arrival time - 18.361 slack 15.239 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 7.627 + 1.167 net: CLK40out 8.794 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 9.344 i_cbb/clock_generation_reg_rst_master:Q (f) + 9.017 net: i_cbb/rst_scsn 18.361 i_cbb/scsn_inst_nw_apl/modgen_counter_waitcount_reg_q(5):CLR (f) 18.361 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation 32.627 + 1.195 net: CLK40out 33.822 i_cbb/scsn_inst_nw_apl/modgen_counter_waitcount_reg_q(5):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 33.600 i_cbb/scsn_inst_nw_apl/modgen_counter_waitcount_reg_q(5):CLR 33.600 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: i_adc/siu_i/reg_fbDin_i(7):CLR Delay (ns): 18.552 Slack (ns): Arrival (ns): 18.552 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.985 Path 2 From: PUSHB To: i_adc/siu_i/reg_dout(9):CLR Delay (ns): 18.394 Slack (ns): Arrival (ns): 18.394 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.816 Path 3 From: PUSHB To: i_adc/siu_i/reg_dout(1):CLR Delay (ns): 17.918 Slack (ns): Arrival (ns): 17.918 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.340 Path 4 From: PUSHB To: i_adc/siu_i/reg_dout(11):CLR Delay (ns): 17.858 Slack (ns): Arrival (ns): 17.858 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.280 Path 5 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib0/reg_b_data(23):CLR Delay (ns): 17.241 Slack (ns): Arrival (ns): 17.241 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.681 Path 6 From: PUSHB To: i_SIU/reg_s_fid(6):CLR Delay (ns): 17.231 Slack (ns): Arrival (ns): 17.231 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.656 Path 7 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(24):CLR Delay (ns): 17.079 Slack (ns): Arrival (ns): 17.079 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.524 Path 8 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(30):CLR Delay (ns): 16.830 Slack (ns): Arrival (ns): 16.830 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.275 Path 9 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib0/reg_b_data(22):CLR Delay (ns): 16.777 Slack (ns): Arrival (ns): 16.777 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.212 Path 10 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(28):CLR Delay (ns): 16.777 Slack (ns): Arrival (ns): 16.777 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.212 Expanded Path 1 From: PUSHB To: i_adc/siu_i/reg_fbDin_i(7):CLR data required time N/C data arrival time - 18.552 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 10.128 net: not_rst_n 18.552 i_adc/siu_i/reg_fbDin_i(7):CLR (f) 18.552 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.162 net: CLK40out N/C i_adc/siu_i/reg_fbDin_i(7):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/siu_i/reg_fbDin_i(7):CLR Expanded Path 2 From: PUSHB To: i_adc/siu_i/reg_dout(9):CLR data required time N/C data arrival time - 18.394 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 9.970 net: not_rst_n 18.394 i_adc/siu_i/reg_dout(9):CLR (f) 18.394 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.173 net: CLK40out N/C i_adc/siu_i/reg_dout(9):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/siu_i/reg_dout(9):CLR Expanded Path 3 From: PUSHB To: i_adc/siu_i/reg_dout(1):CLR data required time N/C data arrival time - 17.918 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 9.494 net: not_rst_n 17.918 i_adc/siu_i/reg_dout(1):CLR (f) 17.918 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.173 net: CLK40out N/C i_adc/siu_i/reg_dout(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/siu_i/reg_dout(1):CLR Expanded Path 4 From: PUSHB To: i_adc/siu_i/reg_dout(11):CLR data required time N/C data arrival time - 17.858 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 9.434 net: not_rst_n 17.858 i_adc/siu_i/reg_dout(11):CLR (f) 17.858 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.173 net: CLK40out N/C i_adc/siu_i/reg_dout(11):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/siu_i/reg_dout(11):CLR Expanded Path 5 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib0/reg_b_data(23):CLR data required time N/C data arrival time - 17.241 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.817 net: not_rst_n 17.241 i_adc/scsn_slv_nw_dll_ib0/reg_b_data(23):CLR (f) 17.241 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.155 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ib0/reg_b_data(23):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ib0/reg_b_data(23):CLR Expanded Path 6 From: PUSHB To: i_SIU/reg_s_fid(6):CLR data required time N/C data arrival time - 17.231 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.807 net: not_rst_n 17.231 i_SIU/reg_s_fid(6):CLR (f) 17.231 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.170 net: CLK40out N/C i_SIU/reg_s_fid(6):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_s_fid(6):CLR Expanded Path 7 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(24):CLR data required time N/C data arrival time - 17.079 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.655 net: not_rst_n 17.079 i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(24):CLR (f) 17.079 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.150 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(24):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(24):CLR Expanded Path 8 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(30):CLR data required time N/C data arrival time - 16.830 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.406 net: not_rst_n 16.830 i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(30):CLR (f) 16.830 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.150 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(30):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(30):CLR Expanded Path 9 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib0/reg_b_data(22):CLR data required time N/C data arrival time - 16.777 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.353 net: not_rst_n 16.777 i_adc/scsn_slv_nw_dll_ib0/reg_b_data(22):CLR (f) 16.777 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.160 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ib0/reg_b_data(22):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ib0/reg_b_data(22):CLR Expanded Path 10 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(28):CLR data required time N/C data arrival time - 16.777 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 6.873 net: PUSHB_i 7.983 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 8.424 i_adc/adc/ix4491z24338:Y (f) + 8.353 net: not_rst_n 16.777 i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(28):CLR (f) 16.777 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 7.627 Clock generation N/C + 1.160 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(28):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob1/reg_ob_data(28):CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLB Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin oddr_BC_ECL_ob/U0/U1:OCLK SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DR Delay (ns): 15.637 Slack (ns): Arrival (ns): 15.637 Required (ns): Setup (ns): 0.191 External Setup (ns): 3.924 Path 2 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DR Delay (ns): 15.608 Slack (ns): Arrival (ns): 15.608 Required (ns): Setup (ns): 0.191 External Setup (ns): 3.895 Path 3 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DF Delay (ns): 15.125 Slack (ns): Arrival (ns): 15.125 Required (ns): Setup (ns): 0.335 External Setup (ns): 3.556 Path 4 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DF Delay (ns): 15.096 Slack (ns): Arrival (ns): 15.096 Required (ns): Setup (ns): 0.335 External Setup (ns): 3.527 Expanded Path 1 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DR data required time N/C data arrival time - 15.637 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(1) (r) + 0.000 net: TLMU_n_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (r) + 6.027 net: TLMU_i_1_ 9.532 i_cbb/tin2_inst/ix2401z14896:A (r) + 0.497 cell: ADLIB:MX2 10.029 i_cbb/tin2_inst/ix2401z14896:Y (r) + 0.315 net: nx11205z1 10.344 ix11205z14896:A (r) + 0.424 cell: ADLIB:MX2 10.768 ix11205z14896:Y (r) + 4.869 net: not_PIMLINK_i_2 15.637 oddr_PIMLINK_2_ob/U0/U1:DR (r) 15.637 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C + 1.152 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) - 0.191 Library setup time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DR Expanded Path 2 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DR data required time N/C data arrival time - 15.608 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(1) (r) + 0.000 net: TLMU_p_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:PAD (r) + 3.444 cell: ADLIB:IOPADP_IN 3.444 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 3.444 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.476 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (r) + 6.027 net: TLMU_i_1_ 9.503 i_cbb/tin2_inst/ix2401z14896:A (r) + 0.497 cell: ADLIB:MX2 10.000 i_cbb/tin2_inst/ix2401z14896:Y (r) + 0.315 net: nx11205z1 10.315 ix11205z14896:A (r) + 0.424 cell: ADLIB:MX2 10.739 ix11205z14896:Y (r) + 4.869 net: not_PIMLINK_i_2 15.608 oddr_PIMLINK_2_ob/U0/U1:DR (r) 15.608 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C + 1.152 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) - 0.191 Library setup time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DR Expanded Path 3 From: TLMU_n(1) To: oddr_PIMLINK_2_ob/U0/U1:DF data required time N/C data arrival time - 15.125 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_n(1) (r) + 0.000 net: TLMU_n_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U2:N2POUT (r) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/U2_N2P 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:N2PIN (r) + 3.473 cell: ADLIB:IOPADP_IN 3.473 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 3.473 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.505 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (r) + 6.027 net: TLMU_i_1_ 9.532 i_cbb/tin2_inst/ix2401z14896:A (r) + 0.497 cell: ADLIB:MX2 10.029 i_cbb/tin2_inst/ix2401z14896:Y (r) + 0.304 net: nx11205z1 10.333 i_cbb/tin2_inst/NOT_trg_i:A (r) + 0.424 cell: ADLIB:MX2C 10.757 i_cbb/tin2_inst/NOT_trg_i:Y (f) + 4.368 net: PIMLINK_i_2_ 15.125 oddr_PIMLINK_2_ob/U0/U1:DF (f) 15.125 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C + 1.152 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) - 0.335 Library setup time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DF Expanded Path 4 From: TLMU_p(1) To: oddr_PIMLINK_2_ob/U0/U1:DF data required time N/C data arrival time - 15.096 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TLMU_p(1) (r) + 0.000 net: TLMU_p_1_ 0.000 tlmu_in[1].lvds_TLMU_U1/U0/U0:PAD (r) + 3.444 cell: ADLIB:IOPADP_IN 3.444 tlmu_in[1].lvds_TLMU_U1/U0/U0:Y (r) + 0.000 net: tlmu_in[1]_lvds_TLMU_U1/U0/NET1 3.444 tlmu_in[1].lvds_TLMU_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 3.476 tlmu_in[1].lvds_TLMU_U1/U0/U1:Y (r) + 6.027 net: TLMU_i_1_ 9.503 i_cbb/tin2_inst/ix2401z14896:A (r) + 0.497 cell: ADLIB:MX2 10.000 i_cbb/tin2_inst/ix2401z14896:Y (r) + 0.304 net: nx11205z1 10.304 i_cbb/tin2_inst/NOT_trg_i:A (r) + 0.424 cell: ADLIB:MX2C 10.728 i_cbb/tin2_inst/NOT_trg_i:Y (f) + 4.368 net: PIMLINK_i_2_ 15.096 oddr_PIMLINK_2_ob/U0/U1:DF (f) 15.096 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C + 1.152 net: CLK40out_90 N/C oddr_PIMLINK_2_ob/U0/U1:OCLK (r) - 0.335 Library setup time: ADLIB:IOTRI_OD_EB N/C oddr_PIMLINK_2_ob/U0/U1:DF END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL Delay (ns): 3.440 Slack (ns): Arrival (ns): 15.347 Required (ns): Clock to Out (ns): 15.347 Path 2 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) Delay (ns): 3.440 Slack (ns): Arrival (ns): 15.344 Required (ns): Clock to Out (ns): 15.344 Path 3 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) Delay (ns): 3.440 Slack (ns): Arrival (ns): 15.344 Required (ns): Clock to Out (ns): 15.344 Expanded Path 1 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL data required time N/C data arrival time - 15.347 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation 10.752 + 1.155 net: CLK40out_90 11.907 oddr_BC_ECL_ob/U0/U1:OCLK (r) + 0.701 cell: ADLIB:IOTRI_OD_EB 12.608 oddr_BC_ECL_ob/U0/U1:DOUT (f) + 0.000 net: oddr_BC_ECL_ob/U0/NET1 12.608 oddr_BC_ECL_ob/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 15.347 oddr_BC_ECL_ob/U0/U0:PAD (f) + 0.000 net: BC_ECL 15.347 BC_ECL (f) 15.347 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C N/C BC_ECL (f) Expanded Path 2 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) data required time N/C data arrival time - 15.344 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation 10.752 + 1.152 net: CLK40out_90 11.904 oddr_PIMLINK_1_ob/U0/U1:OCLK (r) + 0.701 cell: ADLIB:IOTRI_OD_EB 12.605 oddr_PIMLINK_1_ob/U0/U1:DOUT (f) + 0.000 net: oddr_PIMLINK_1_ob/U0/NET1 12.605 oddr_PIMLINK_1_ob/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 15.344 oddr_PIMLINK_1_ob/U0/U0:PAD (f) + 0.000 net: PIMLINK_1_ 15.344 PIMLINK(1) (f) 15.344 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C N/C PIMLINK(1) (f) Expanded Path 3 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) data required time N/C data arrival time - 15.344 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation 10.752 + 1.152 net: CLK40out_90 11.904 oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.701 cell: ADLIB:IOTRI_OD_EB 12.605 oddr_PIMLINK_2_ob/U0/U1:DOUT (f) + 0.000 net: oddr_PIMLINK_2_ob/U0/NET1 12.605 oddr_PIMLINK_2_ob/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 15.344 oddr_PIMLINK_2_ob/U0/U0:PAD (f) + 0.000 net: PIMLINK_2_ 15.344 PIMLINK(2) (f) 15.344 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.752 Clock generation N/C N/C PIMLINK(2) (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLC SET Register to Register Path 1 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(0):D Delay (ns): 6.156 Slack (ns): 5.843 Arrival (ns): 14.998 Required (ns): 20.841 Setup (ns): 0.428 Minimum Period (ns): 6.657 Path 2 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(0):D Delay (ns): 5.592 Slack (ns): 6.407 Arrival (ns): 14.434 Required (ns): 20.841 Setup (ns): 0.428 Minimum Period (ns): 6.093 Path 3 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D Delay (ns): 5.378 Slack (ns): 6.652 Arrival (ns): 14.220 Required (ns): 20.872 Setup (ns): 0.428 Minimum Period (ns): 5.848 Path 4 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D Delay (ns): 4.356 Slack (ns): 7.694 Arrival (ns): 13.156 Required (ns): 20.850 Setup (ns): 0.428 Minimum Period (ns): 4.806 Path 5 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D Delay (ns): 4.106 Slack (ns): 7.899 Arrival (ns): 12.948 Required (ns): 20.847 Setup (ns): 0.428 Minimum Period (ns): 4.601 Path 6 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D Delay (ns): 3.664 Slack (ns): 8.415 Arrival (ns): 12.439 Required (ns): 20.854 Setup (ns): 0.428 Minimum Period (ns): 4.085 Path 7 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D Delay (ns): 3.202 Slack (ns): 8.879 Arrival (ns): 11.971 Required (ns): 20.850 Setup (ns): 0.428 Minimum Period (ns): 3.621 Path 8 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D Delay (ns): 1.739 Slack (ns): 10.346 Arrival (ns): 10.508 Required (ns): 20.854 Setup (ns): 0.428 Minimum Period (ns): 2.154 Path 9 From: i_cbb/cbc_sample_reg_cb_par(2):CLK To: i_cbb/cbc_sample_reg_cb_par(4):D Delay (ns): 0.847 Slack (ns): 11.222 Arrival (ns): 9.625 Required (ns): 20.847 Setup (ns): 0.428 Minimum Period (ns): 1.278 Path 10 From: i_cbb/cba_sample_reg_cb_par(3):CLK To: i_cbb/cba_sample_reg_cb_par(5):D Delay (ns): 0.837 Slack (ns): 11.235 Arrival (ns): 9.619 Required (ns): 20.854 Setup (ns): 0.428 Minimum Period (ns): 1.265 Expanded Path 1 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(0):D data required time 20.841 data arrival time - 14.998 slack 5.843 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.215 net: CLK80out 8.842 iddr_CB_A_ib/U0/U1:ICLK (r) + 0.367 cell: ADLIB:IOIN_ID 9.209 iddr_CB_A_ib/U0/U1:YR (r) + 5.789 net: CB_A_i_0_ 14.998 i_cbb/cba_sample_reg_cb_par(0):D (r) 14.998 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.142 net: CLK80out 21.269 i_cbb/cba_sample_reg_cb_par(0):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.841 i_cbb/cba_sample_reg_cb_par(0):D 20.841 data required time Expanded Path 2 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(0):D data required time 20.841 data arrival time - 14.434 slack 6.407 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.215 net: CLK80out 8.842 iddr_CB_C_ib/U0/U1:ICLK (r) + 0.367 cell: ADLIB:IOIN_ID 9.209 iddr_CB_C_ib/U0/U1:YR (r) + 5.225 net: CB_C_i_0_ 14.434 i_cbb/cbc_sample_reg_cb_par(0):D (r) 14.434 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.142 net: CLK80out 21.269 i_cbb/cbc_sample_reg_cb_par(0):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.841 i_cbb/cbc_sample_reg_cb_par(0):D 20.841 data required time Expanded Path 3 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D data required time 20.872 data arrival time - 14.220 slack 6.652 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.215 net: CLK80out 8.842 iddr_CB_C_ib/U0/U1:ICLK (r) + 0.260 cell: ADLIB:IOIN_ID 9.102 iddr_CB_C_ib/U0/U1:YF (r) + 5.118 net: CB_C_i_1_ 14.220 i_cbb/cbc_sample_reg_cb_par(1):D (r) 14.220 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.173 net: CLK80out 21.300 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.872 i_cbb/cbc_sample_reg_cb_par(1):D 20.872 data required time Expanded Path 4 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D data required time 20.850 data arrival time - 13.156 slack 7.694 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.173 net: CLK80out 8.800 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.350 i_cbb/cbc_sample_reg_cb_par(1):Q (f) + 3.806 net: i_cbb/cbc_sample_cb_par_1_ 13.156 i_cbb/cbc_sample_reg_cb_par(3):D (f) 13.156 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.151 net: CLK80out 21.278 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.850 i_cbb/cbc_sample_reg_cb_par(3):D 20.850 data required time Expanded Path 5 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D data required time 20.847 data arrival time - 12.948 slack 7.899 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.215 net: CLK80out 8.842 iddr_CB_A_ib/U0/U1:ICLK (r) + 0.260 cell: ADLIB:IOIN_ID 9.102 iddr_CB_A_ib/U0/U1:YF (r) + 3.846 net: CB_A_i_1_ 12.948 i_cbb/cba_sample_reg_cb_par(1):D (r) 12.948 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.148 net: CLK80out 21.275 i_cbb/cba_sample_reg_cb_par(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.847 i_cbb/cba_sample_reg_cb_par(1):D 20.847 data required time Expanded Path 6 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D data required time 20.854 data arrival time - 12.439 slack 8.415 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.148 net: CLK80out 8.775 i_cbb/cba_sample_reg_cb_par(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.325 i_cbb/cba_sample_reg_cb_par(1):Q (f) + 3.114 net: i_cbb/cba_sample_cb_par_1_ 12.439 i_cbb/cba_sample_reg_cb_par(3):D (f) 12.439 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.155 net: CLK80out 21.282 i_cbb/cba_sample_reg_cb_par(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.854 i_cbb/cba_sample_reg_cb_par(3):D 20.854 data required time Expanded Path 7 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D data required time 20.850 data arrival time - 11.971 slack 8.879 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.142 net: CLK80out 8.769 i_cbb/cbc_sample_reg_cb_par(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.319 i_cbb/cbc_sample_reg_cb_par(0):Q (f) + 2.652 net: i_cbb/cbc_sample_cb_par_0_ 11.971 i_cbb/cbc_sample_reg_cb_par(2):D (f) 11.971 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.151 net: CLK80out 21.278 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.850 i_cbb/cbc_sample_reg_cb_par(2):D 20.850 data required time Expanded Path 8 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D data required time 20.854 data arrival time - 10.508 slack 10.346 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.142 net: CLK80out 8.769 i_cbb/cba_sample_reg_cb_par(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.319 i_cbb/cba_sample_reg_cb_par(0):Q (f) + 1.189 net: i_cbb/cba_sample_cb_par_0_ 10.508 i_cbb/cba_sample_reg_cb_par(2):D (f) 10.508 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.155 net: CLK80out 21.282 i_cbb/cba_sample_reg_cb_par(2):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.854 i_cbb/cba_sample_reg_cb_par(2):D 20.854 data required time Expanded Path 9 From: i_cbb/cbc_sample_reg_cb_par(2):CLK To: i_cbb/cbc_sample_reg_cb_par(4):D data required time 20.847 data arrival time - 9.625 slack 11.222 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.151 net: CLK80out 8.778 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.328 i_cbb/cbc_sample_reg_cb_par(2):Q (f) + 0.297 net: i_cbb/cbc_sample_cb_par_2_ 9.625 i_cbb/cbc_sample_reg_cb_par(4):D (f) 9.625 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.148 net: CLK80out 21.275 i_cbb/cbc_sample_reg_cb_par(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.847 i_cbb/cbc_sample_reg_cb_par(4):D 20.847 data required time Expanded Path 10 From: i_cbb/cba_sample_reg_cb_par(3):CLK To: i_cbb/cba_sample_reg_cb_par(5):D data required time 20.854 data arrival time - 9.619 slack 11.235 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.155 net: CLK80out 8.782 i_cbb/cba_sample_reg_cb_par(3):CLK (r) + 0.550 cell: ADLIB:DFN1C1 9.332 i_cbb/cba_sample_reg_cb_par(3):Q (f) + 0.287 net: i_cbb/cba_sample_cb_par_3_ 9.619 i_cbb/cba_sample_reg_cb_par(5):D (f) 9.619 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 20.127 + 1.155 net: CLK80out 21.282 i_cbb/cba_sample_reg_cb_par(5):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 20.854 i_cbb/cba_sample_reg_cb_par(5):D 20.854 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN Delay (ns): 0.898 Slack (ns): Arrival (ns): 0.898 Required (ns): Setup (ns): 0.245 External Setup (ns): -7.554 Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN Delay (ns): 0.898 Slack (ns): Arrival (ns): 0.898 Required (ns): Setup (ns): 0.245 External Setup (ns): -7.554 Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN Delay (ns): 0.898 Slack (ns): Arrival (ns): 0.898 Required (ns): Setup (ns): 0.245 External Setup (ns): -7.554 Expanded Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN data required time N/C data arrival time - 0.898 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_C (r) + 0.000 net: CB_C 0.000 iddr_CB_C_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 iddr_CB_C_ib/U0/U0:Y (r) + 0.000 net: iddr_CB_C_ib/U0/NET1 0.898 iddr_CB_C_ib/U0/U1:YIN (r) 0.898 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (f) + 7.479 Clock generation N/C + 1.218 net: CLK80out N/C iddr_CB_C_ib/U0/U1:ICLK (f) - 0.245 Library setup time: ADLIB:IOIN_ID N/C iddr_CB_C_ib/U0/U1:YIN Expanded Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN data required time N/C data arrival time - 0.898 slack N/C ________________________________________________________ Data arrival time calculation 0.000 BUSY (r) + 0.000 net: BUSY 0.000 iddr_busy_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 iddr_busy_ib/U0/U0:Y (r) + 0.000 net: iddr_busy_ib/U0/NET1 0.898 iddr_busy_ib/U0/U1:YIN (r) 0.898 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (f) + 7.479 Clock generation N/C + 1.218 net: CLK80out N/C iddr_busy_ib/U0/U1:ICLK (f) - 0.245 Library setup time: ADLIB:IOIN_ID N/C iddr_busy_ib/U0/U1:YIN Expanded Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN data required time N/C data arrival time - 0.898 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_A (r) + 0.000 net: CB_A 0.000 iddr_CB_A_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 iddr_CB_A_ib/U0/U0:Y (r) + 0.000 net: iddr_CB_A_ib/U0/NET1 0.898 iddr_CB_A_ib/U0/U1:YIN (r) 0.898 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (f) + 7.479 Clock generation N/C + 1.218 net: CLK80out N/C iddr_CB_A_ib/U0/U1:ICLK (f) - 0.245 Library setup time: ADLIB:IOIN_ID N/C iddr_CB_A_ib/U0/U1:YIN END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p Delay (ns): 13.909 Slack (ns): Arrival (ns): 22.751 Required (ns): Clock to Out (ns): 22.751 Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n Delay (ns): 13.909 Slack (ns): Arrival (ns): 22.751 Required (ns): Clock to Out (ns): 22.751 Expanded Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p data required time N/C data arrival time - 22.751 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.215 net: CLK80out 8.842 iddr_busy_ib/U0/U1:ICLK (r) + 0.260 cell: ADLIB:IOIN_ID 9.102 iddr_busy_ib/U0/U1:YF (r) + 5.234 net: BUSY_i_1_ 14.336 i_cbb/ix7212z10880:B (r) + 0.536 cell: ADLIB:XOR2 14.872 i_cbb/ix7212z10880:Y (r) + 3.899 net: i_cbb/nx7212z5 18.771 i_cbb/SPA:C (r) + 0.736 cell: ADLIB:XOR3 19.507 i_cbb/SPA:Y (f) + 1.316 net: SPA_i 20.823 lvds_SPA_iob/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 21.315 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 21.315 lvds_SPA_iob/U0/U0:D (f) + 1.436 cell: ADLIB:IOPADP_TRI 22.751 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 22.751 SPA_p (f) 22.751 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation N/C N/C SPA_p (f) Expanded Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n data required time N/C data arrival time - 22.751 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation 7.627 + 1.215 net: CLK80out 8.842 iddr_busy_ib/U0/U1:ICLK (r) + 0.260 cell: ADLIB:IOIN_ID 9.102 iddr_busy_ib/U0/U1:YF (r) + 5.234 net: BUSY_i_1_ 14.336 i_cbb/ix7212z10880:B (r) + 0.536 cell: ADLIB:XOR2 14.872 i_cbb/ix7212z10880:Y (r) + 3.899 net: i_cbb/nx7212z5 18.771 i_cbb/SPA:C (r) + 0.736 cell: ADLIB:XOR3 19.507 i_cbb/SPA:Y (f) + 1.316 net: SPA_i 20.823 lvds_SPA_iob/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 21.315 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 21.315 lvds_SPA_iob/U0/U2:DB (f) + 1.436 cell: ADLIB:IOPADN_OUT 22.751 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 22.751 SPA_n (r) 22.751 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 7.627 Clock generation N/C N/C SPA_n (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain CLK40p Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin lvds_clk40in_U1/U0/U0:PAD SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Setup No Path END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p Delay (ns): 5.097 Slack (ns): Arrival (ns): 10.724 Required (ns): Clock to Out (ns): 10.724 Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n Delay (ns): 5.097 Slack (ns): Arrival (ns): 10.724 Required (ns): Clock to Out (ns): 10.724 Expanded Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p data required time N/C data arrival time - 10.724 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (r) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_clk40in_U1/U0/U0:Y (r) + 0.000 net: lvds_clk40in_U1/U0/NET1 1.392 lvds_clk40in_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_clk40in_U1/U0/U1:Y (r) + 4.203 net: CLK40_i 5.627 i_cbb/clock_generation_ipll_Core:CLKA (r) + 2.000 cell: ADLIB:PLL 7.627 i_cbb/clock_generation_ipll_Core:GLA (r) + 1.196 net: CLK40out 8.823 lvds_clk40out_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 9.310 lvds_clk40out_iob/U0/U1:DOUT (r) + 0.000 net: lvds_clk40out_iob/U0/NET1 9.310 lvds_clk40out_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 10.724 lvds_clk40out_iob/U0/U0:PAD (r) + 0.000 net: CLK40T_p 10.724 CLK40T_p (r) 10.724 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_p (r) Expanded Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n data required time N/C data arrival time - 10.724 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (r) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_clk40in_U1/U0/U0:Y (r) + 0.000 net: lvds_clk40in_U1/U0/NET1 1.392 lvds_clk40in_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_clk40in_U1/U0/U1:Y (r) + 4.203 net: CLK40_i 5.627 i_cbb/clock_generation_ipll_Core:CLKA (r) + 2.000 cell: ADLIB:PLL 7.627 i_cbb/clock_generation_ipll_Core:GLA (r) + 1.196 net: CLK40out 8.823 lvds_clk40out_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 9.310 lvds_clk40out_iob/U0/U1:DOUT (r) + 0.000 net: lvds_clk40out_iob/U0/NET1 9.310 lvds_clk40out_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 10.724 lvds_clk40out_iob/U0/U2:PAD (f) + 0.000 net: CLK40T_n 10.724 CLK40T_n (f) 10.724 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_n (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Path set Pin to Pin SET Input to Output Path 1 From: IO_C(0) To: SPA_p Delay (ns): 14.068 Slack (ns): Arrival (ns): 14.068 Required (ns): Path 2 From: IO_C(0) To: SPA_n Delay (ns): 14.068 Slack (ns): Arrival (ns): 14.068 Required (ns): Path 3 From: SCSNFEBINn To: IF17x_SCSN_OUT_n Delay (ns): 12.336 Slack (ns): Arrival (ns): 12.336 Required (ns): Path 4 From: SCSNFEBINn To: IF17x_SCSN_OUT_p Delay (ns): 12.336 Slack (ns): Arrival (ns): 12.336 Required (ns): Path 5 From: SCSNFEBINp To: IF17x_SCSN_OUT_n Delay (ns): 12.307 Slack (ns): Arrival (ns): 12.307 Required (ns): Path 6 From: SCSNFEBINp To: IF17x_SCSN_OUT_p Delay (ns): 12.307 Slack (ns): Arrival (ns): 12.307 Required (ns): Path 7 From: IF17x_SCSN_IN_n To: SCSNFEBOUTp Delay (ns): 11.459 Slack (ns): Arrival (ns): 11.459 Required (ns): Path 8 From: IF17x_SCSN_IN_n To: SCSNFEBOUTn Delay (ns): 11.459 Slack (ns): Arrival (ns): 11.459 Required (ns): Path 9 From: IF17x_SCSN_IN_p To: SCSNFEBOUTp Delay (ns): 11.430 Slack (ns): Arrival (ns): 11.430 Required (ns): Path 10 From: IF17x_SCSN_IN_p To: SCSNFEBOUTn Delay (ns): 11.430 Slack (ns): Arrival (ns): 11.430 Required (ns): Expanded Path 1 From: IO_C(0) To: SPA_p data required time N/C data arrival time - 14.068 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(0) (r) + 0.000 net: IO_C_0_ 0.000 ibuf_IO_C0_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_IO_C0_ib/U0/U0:Y (r) + 0.000 net: ibuf_IO_C0_ib/U0/NET1 0.898 ibuf_IO_C0_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_IO_C0_ib/U0/U1:Y (r) + 7.764 net: IO_C_i_0_ 8.694 i_cbb/ix7212z10877:A (r) + 0.392 cell: ADLIB:XOR2 9.086 i_cbb/ix7212z10877:Y (r) + 0.238 net: i_cbb/nx7212z2 9.324 i_cbb/modgen_xor_1423_ix7212z10877:A (r) + 0.297 cell: ADLIB:XOR3 9.621 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.796 net: i_cbb/nx7212z1 10.417 i_cbb/SPA:A (f) + 0.365 cell: ADLIB:XOR3 10.782 i_cbb/SPA:Y (r) + 1.385 net: SPA_i 12.167 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 12.654 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 12.654 lvds_SPA_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 14.068 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 14.068 SPA_p (r) 14.068 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(0) (r) N/C SPA_p (r) N/C data required time Expanded Path 2 From: IO_C(0) To: SPA_n data required time N/C data arrival time - 14.068 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(0) (r) + 0.000 net: IO_C_0_ 0.000 ibuf_IO_C0_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_IO_C0_ib/U0/U0:Y (r) + 0.000 net: ibuf_IO_C0_ib/U0/NET1 0.898 ibuf_IO_C0_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_IO_C0_ib/U0/U1:Y (r) + 7.764 net: IO_C_i_0_ 8.694 i_cbb/ix7212z10877:A (r) + 0.392 cell: ADLIB:XOR2 9.086 i_cbb/ix7212z10877:Y (r) + 0.238 net: i_cbb/nx7212z2 9.324 i_cbb/modgen_xor_1423_ix7212z10877:A (r) + 0.297 cell: ADLIB:XOR3 9.621 i_cbb/modgen_xor_1423_ix7212z10877:Y (f) + 0.796 net: i_cbb/nx7212z1 10.417 i_cbb/SPA:A (f) + 0.365 cell: ADLIB:XOR3 10.782 i_cbb/SPA:Y (r) + 1.385 net: SPA_i 12.167 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 12.654 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 12.654 lvds_SPA_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 14.068 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 14.068 SPA_n (f) 14.068 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(0) (r) N/C SPA_n (f) N/C data required time Expanded Path 3 From: SCSNFEBINn To: IF17x_SCSN_OUT_n data required time N/C data arrival time - 12.336 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SCSNFEBINn (r) + 0.000 net: SCSNFEBINn 0.000 lvds_SCSNFEBIN_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_SCSNFEBIN_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_SCSNFEBIN_U1/U0/U2_N2P 0.000 lvds_SCSNFEBIN_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_SCSNFEBIN_U1/U0/U0:Y (r) + 0.000 net: lvds_SCSNFEBIN_U1/U0/NET1 1.421 lvds_SCSNFEBIN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_SCSNFEBIN_U1/U0/U1:Y (r) + 9.021 net: IF17x_SCSN_OUT_i 10.474 lvds_IF17x_SCSN_OUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.922 lvds_IF17x_SCSN_OUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_IF17x_SCSN_OUT_iob/U0/NET1 10.922 lvds_IF17x_SCSN_OUT_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 12.336 lvds_IF17x_SCSN_OUT_iob/U0/U2:PAD (f) + 0.000 net: IF17x_SCSN_OUT_n 12.336 IF17x_SCSN_OUT_n (f) 12.336 data arrival time ________________________________________________________ Data required time calculation N/C SCSNFEBINn (r) N/C IF17x_SCSN_OUT_n (f) N/C data required time Expanded Path 4 From: SCSNFEBINn To: IF17x_SCSN_OUT_p data required time N/C data arrival time - 12.336 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SCSNFEBINn (r) + 0.000 net: SCSNFEBINn 0.000 lvds_SCSNFEBIN_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_SCSNFEBIN_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_SCSNFEBIN_U1/U0/U2_N2P 0.000 lvds_SCSNFEBIN_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_SCSNFEBIN_U1/U0/U0:Y (r) + 0.000 net: lvds_SCSNFEBIN_U1/U0/NET1 1.421 lvds_SCSNFEBIN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_SCSNFEBIN_U1/U0/U1:Y (r) + 9.021 net: IF17x_SCSN_OUT_i 10.474 lvds_IF17x_SCSN_OUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.922 lvds_IF17x_SCSN_OUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_IF17x_SCSN_OUT_iob/U0/NET1 10.922 lvds_IF17x_SCSN_OUT_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 12.336 lvds_IF17x_SCSN_OUT_iob/U0/U0:PAD (r) + 0.000 net: IF17x_SCSN_OUT_p 12.336 IF17x_SCSN_OUT_p (r) 12.336 data arrival time ________________________________________________________ Data required time calculation N/C SCSNFEBINn (r) N/C IF17x_SCSN_OUT_p (r) N/C data required time Expanded Path 5 From: SCSNFEBINp To: IF17x_SCSN_OUT_n data required time N/C data arrival time - 12.307 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SCSNFEBINp (r) + 0.000 net: SCSNFEBINp 0.000 lvds_SCSNFEBIN_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_SCSNFEBIN_U1/U0/U0:Y (r) + 0.000 net: lvds_SCSNFEBIN_U1/U0/NET1 1.392 lvds_SCSNFEBIN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_SCSNFEBIN_U1/U0/U1:Y (r) + 9.021 net: IF17x_SCSN_OUT_i 10.445 lvds_IF17x_SCSN_OUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.893 lvds_IF17x_SCSN_OUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_IF17x_SCSN_OUT_iob/U0/NET1 10.893 lvds_IF17x_SCSN_OUT_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 12.307 lvds_IF17x_SCSN_OUT_iob/U0/U2:PAD (f) + 0.000 net: IF17x_SCSN_OUT_n 12.307 IF17x_SCSN_OUT_n (f) 12.307 data arrival time ________________________________________________________ Data required time calculation N/C SCSNFEBINp (r) N/C IF17x_SCSN_OUT_n (f) N/C data required time Expanded Path 6 From: SCSNFEBINp To: IF17x_SCSN_OUT_p data required time N/C data arrival time - 12.307 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SCSNFEBINp (r) + 0.000 net: SCSNFEBINp 0.000 lvds_SCSNFEBIN_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_SCSNFEBIN_U1/U0/U0:Y (r) + 0.000 net: lvds_SCSNFEBIN_U1/U0/NET1 1.392 lvds_SCSNFEBIN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_SCSNFEBIN_U1/U0/U1:Y (r) + 9.021 net: IF17x_SCSN_OUT_i 10.445 lvds_IF17x_SCSN_OUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.893 lvds_IF17x_SCSN_OUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_IF17x_SCSN_OUT_iob/U0/NET1 10.893 lvds_IF17x_SCSN_OUT_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 12.307 lvds_IF17x_SCSN_OUT_iob/U0/U0:PAD (r) + 0.000 net: IF17x_SCSN_OUT_p 12.307 IF17x_SCSN_OUT_p (r) 12.307 data arrival time ________________________________________________________ Data required time calculation N/C SCSNFEBINp (r) N/C IF17x_SCSN_OUT_p (r) N/C data required time Expanded Path 7 From: IF17x_SCSN_IN_n To: SCSNFEBOUTp data required time N/C data arrival time - 11.459 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IF17x_SCSN_IN_n (r) + 0.000 net: IF17x_SCSN_IN_n 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/U2_N2P 0.000 lvds_IF17x_SCSN_IN_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_IF17x_SCSN_IN_U1/U0/U0:Y (r) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/NET1 1.421 lvds_IF17x_SCSN_IN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_IF17x_SCSN_IN_U1/U0/U1:Y (r) + 8.144 net: SCSNFEBOUT_i 9.597 lvds_SCSNFEBOUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.045 lvds_SCSNFEBOUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SCSNFEBOUT_iob/U0/NET1 10.045 lvds_SCSNFEBOUT_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 11.459 lvds_SCSNFEBOUT_iob/U0/U0:PAD (r) + 0.000 net: SCSNFEBOUTp 11.459 SCSNFEBOUTp (r) 11.459 data arrival time ________________________________________________________ Data required time calculation N/C IF17x_SCSN_IN_n (r) N/C SCSNFEBOUTp (r) N/C data required time Expanded Path 8 From: IF17x_SCSN_IN_n To: SCSNFEBOUTn data required time N/C data arrival time - 11.459 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IF17x_SCSN_IN_n (r) + 0.000 net: IF17x_SCSN_IN_n 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_IF17x_SCSN_IN_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/U2_N2P 0.000 lvds_IF17x_SCSN_IN_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_IF17x_SCSN_IN_U1/U0/U0:Y (r) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/NET1 1.421 lvds_IF17x_SCSN_IN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_IF17x_SCSN_IN_U1/U0/U1:Y (r) + 8.144 net: SCSNFEBOUT_i 9.597 lvds_SCSNFEBOUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.045 lvds_SCSNFEBOUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SCSNFEBOUT_iob/U0/NET1 10.045 lvds_SCSNFEBOUT_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 11.459 lvds_SCSNFEBOUT_iob/U0/U2:PAD (f) + 0.000 net: SCSNFEBOUTn 11.459 SCSNFEBOUTn (f) 11.459 data arrival time ________________________________________________________ Data required time calculation N/C IF17x_SCSN_IN_n (r) N/C SCSNFEBOUTn (f) N/C data required time Expanded Path 9 From: IF17x_SCSN_IN_p To: SCSNFEBOUTp data required time N/C data arrival time - 11.430 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IF17x_SCSN_IN_p (r) + 0.000 net: IF17x_SCSN_IN_p 0.000 lvds_IF17x_SCSN_IN_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_IF17x_SCSN_IN_U1/U0/U0:Y (r) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/NET1 1.392 lvds_IF17x_SCSN_IN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_IF17x_SCSN_IN_U1/U0/U1:Y (r) + 8.144 net: SCSNFEBOUT_i 9.568 lvds_SCSNFEBOUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.016 lvds_SCSNFEBOUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SCSNFEBOUT_iob/U0/NET1 10.016 lvds_SCSNFEBOUT_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 11.430 lvds_SCSNFEBOUT_iob/U0/U0:PAD (r) + 0.000 net: SCSNFEBOUTp 11.430 SCSNFEBOUTp (r) 11.430 data arrival time ________________________________________________________ Data required time calculation N/C IF17x_SCSN_IN_p (r) N/C SCSNFEBOUTp (r) N/C data required time Expanded Path 10 From: IF17x_SCSN_IN_p To: SCSNFEBOUTn data required time N/C data arrival time - 11.430 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IF17x_SCSN_IN_p (r) + 0.000 net: IF17x_SCSN_IN_p 0.000 lvds_IF17x_SCSN_IN_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_IF17x_SCSN_IN_U1/U0/U0:Y (r) + 0.000 net: lvds_IF17x_SCSN_IN_U1/U0/NET1 1.392 lvds_IF17x_SCSN_IN_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_IF17x_SCSN_IN_U1/U0/U1:Y (r) + 8.144 net: SCSNFEBOUT_i 9.568 lvds_SCSNFEBOUT_iob/U0/U1:D (r) + 0.448 cell: ADLIB:IOTRI_OB_EB 10.016 lvds_SCSNFEBOUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SCSNFEBOUT_iob/U0/NET1 10.016 lvds_SCSNFEBOUT_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 11.430 lvds_SCSNFEBOUT_iob/U0/U2:PAD (f) + 0.000 net: SCSNFEBOUTn 11.430 SCSNFEBOUTn (f) 11.430 data arrival time ________________________________________________________ Data required time calculation N/C IF17x_SCSN_IN_p (r) N/C SCSNFEBOUTn (f) N/C data required time END SET Input to Output ---------------------------------------------------- Path set User Sets