Timing Report Max Delay Analysis SmartTime Version v9.1 SP3 Actel Corporation - Actel Designer Software Release v9.1 SP3 (Version 9.1.3.4) Copyright (c) 1989-2010 Date: Tue Sep 6 16:48:17 2011 Design: actel_par_A3PE1500 Family: ProASIC3E Die: A3PE1500 Package: 208 PQFP Temperature: COM Voltage: COM Speed Grade: -2 Design State: Post-Layout Data source: Silicon verified Min Operating Condition: BEST Max Operating Condition: WORST Using Enhanced Min Delay Analysis Scenario for Timing Analysis: Primary ----------------------------------------------------- SUMMARY Clock Domain: SIU_RXCLK Period (ns): 6.763 Frequency (MHz): 147.863 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 1.647 External Hold (ns): 0.326 Min Clock-To-Out (ns): N/A Max Clock-To-Out (ns): N/A Clock Domain: SIU_TXCLK Period (ns): 6.719 Frequency (MHz): 148.832 Required Period (ns): 9.091 Required Frequency (MHz): 109.999 External Setup (ns): 6.418 External Hold (ns): 1.525 Min Clock-To-Out (ns): 3.130 Max Clock-To-Out (ns): 14.389 Clock Domain: i_SIU/reg_tx_clk_2:Q Period (ns): 8.543 Frequency (MHz): 117.055 Required Period (ns): 18.182 Required Frequency (MHz): 54.999 External Setup (ns): 2.145 External Hold (ns): 0.738 Min Clock-To-Out (ns): 5.042 Max Clock-To-Out (ns): 13.371 Clock Domain: i_adc/cdiv_reg_q:Q Period (ns): 13.986 Frequency (MHz): 71.500 Required Period (ns): 100.000 Required Frequency (MHz): 10.000 External Setup (ns): 1.881 External Hold (ns): -0.136 Min Clock-To-Out (ns): 3.833 Max Clock-To-Out (ns): 10.207 Clock Domain: i_cbb/clock_generation_ipll_Core:GLA Period (ns): 19.159 Frequency (MHz): 52.195 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): 4.729 External Hold (ns): 2.756 Min Clock-To-Out (ns): 5.218 Max Clock-To-Out (ns): 19.544 Clock Domain: i_cbb/clock_generation_ipll_Core:GLB Period (ns): 0.796 Frequency (MHz): 1256.281 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 8.344 Max Clock-To-Out (ns): 14.272 Clock Domain: i_cbb/clock_generation_ipll_Core:GLC Period (ns): 4.450 Frequency (MHz): 224.719 Required Period (ns): 12.500 Required Frequency (MHz): 80.000 External Setup (ns): -6.546 External Hold (ns): 3.852 Min Clock-To-Out (ns): 9.450 Max Clock-To-Out (ns): 19.731 Clock Domain: CLK40p Period (ns): 2.860 Frequency (MHz): 349.650 Required Period (ns): 25.000 Required Frequency (MHz): 40.000 External Setup (ns): N/A External Hold (ns): N/A Min Clock-To-Out (ns): 4.824 Max Clock-To-Out (ns): 9.703 Input to Output Min Delay (ns): 4.530 Max Delay (ns): 13.313 END SUMMARY ----------------------------------------------------- Clock Domain SIU_RXCLK SET Register to Register Path 1 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(10):D Delay (ns): 6.392 Slack (ns): 2.328 Arrival (ns): 10.486 Required (ns): 12.814 Setup (ns): 0.402 Minimum Period (ns): 6.763 Path 2 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(9):D Delay (ns): 6.283 Slack (ns): 2.451 Arrival (ns): 10.377 Required (ns): 12.828 Setup (ns): 0.402 Minimum Period (ns): 6.640 Path 3 From: i_SIU/RXDATA_INST/reg_b_rx_data:CLK To: i_SIU/RXDATA_INST/reg_q(7):D Delay (ns): 6.074 Slack (ns): 2.672 Arrival (ns): 10.199 Required (ns): 12.871 Setup (ns): 0.428 Minimum Period (ns): 6.419 Path 4 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(11):D Delay (ns): 5.960 Slack (ns): 2.711 Arrival (ns): 10.054 Required (ns): 12.765 Setup (ns): 0.402 Minimum Period (ns): 6.380 Path 5 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(10):D Delay (ns): 5.963 Slack (ns): 2.775 Arrival (ns): 10.039 Required (ns): 12.814 Setup (ns): 0.402 Minimum Period (ns): 6.316 Path 6 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(16):D Delay (ns): 5.912 Slack (ns): 2.777 Arrival (ns): 10.006 Required (ns): 12.783 Setup (ns): 0.402 Minimum Period (ns): 6.314 Path 7 From: i_SIU/reg_q(0):CLK To: i_SIU/reg_q(10):D Delay (ns): 5.931 Slack (ns): 2.807 Arrival (ns): 10.007 Required (ns): 12.814 Setup (ns): 0.402 Minimum Period (ns): 6.284 Path 8 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(12):D Delay (ns): 5.887 Slack (ns): 2.818 Arrival (ns): 9.981 Required (ns): 12.799 Setup (ns): 0.402 Minimum Period (ns): 6.273 Path 9 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(9):D Delay (ns): 5.854 Slack (ns): 2.898 Arrival (ns): 9.930 Required (ns): 12.828 Setup (ns): 0.402 Minimum Period (ns): 6.193 Path 10 From: i_SIU/reg_q(0):CLK To: i_SIU/reg_q(9):D Delay (ns): 5.822 Slack (ns): 2.930 Arrival (ns): 9.898 Required (ns): 12.828 Setup (ns): 0.402 Minimum Period (ns): 6.161 Expanded Path 1 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(10):D data required time 12.814 data arrival time - 10.486 slack 2.328 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.569 net: SIU_RXCLK_cb 4.094 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.644 i_SIU/reg_q(16):Q (f) + 0.521 net: i_SIU/RXIN_INST_v_por_timer_16_ 5.165 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 5.726 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 6.056 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.553 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 7.300 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.692 i_SIU/NOT_a(0):Y (f) + 1.080 net: i_SIU/NOT_a_0_ 8.772 i_SIU/NOT_ix17096z50931:A (f) + 0.497 cell: ADLIB:NAND3A 9.269 i_SIU/NOT_ix17096z50931:Y (f) + 0.241 net: i_SIU/nx17096z2 9.510 i_SIU/ix17096z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.247 i_SIU/ix17096z21032:Y (f) + 0.239 net: i_SIU/nx17096z1 10.486 i_SIU/reg_q(10):D (f) 10.486 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.600 net: SIU_RXCLK_cb 13.216 i_SIU/reg_q(10):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.814 i_SIU/reg_q(10):D 12.814 data required time Expanded Path 2 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(9):D data required time 12.828 data arrival time - 10.377 slack 2.451 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.569 net: SIU_RXCLK_cb 4.094 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.644 i_SIU/reg_q(16):Q (f) + 0.521 net: i_SIU/RXIN_INST_v_por_timer_16_ 5.165 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 5.726 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 6.056 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.553 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 7.300 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.692 i_SIU/NOT_a(0):Y (f) + 0.983 net: i_SIU/NOT_a_0_ 8.675 i_SIU/NOT_ix60244z49934:A (f) + 0.485 cell: ADLIB:NAND2A 9.160 i_SIU/NOT_ix60244z49934:Y (f) + 0.241 net: i_SIU/nx60244z2 9.401 i_SIU/ix60244z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.138 i_SIU/ix60244z21032:Y (f) + 0.239 net: i_SIU/nx60244z1 10.377 i_SIU/reg_q(9):D (f) 10.377 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.614 net: SIU_RXCLK_cb 13.230 i_SIU/reg_q(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.828 i_SIU/reg_q(9):D 12.828 data required time Expanded Path 3 From: i_SIU/RXDATA_INST/reg_b_rx_data:CLK To: i_SIU/RXDATA_INST/reg_q(7):D data required time 12.871 data arrival time - 10.199 slack 2.672 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.600 net: SIU_RXCLK_cb 4.125 i_SIU/RXDATA_INST/reg_b_rx_data:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.675 i_SIU/RXDATA_INST/reg_b_rx_data:Q (f) + 0.720 net: i_SIU/b_rx_data_dup_100 5.395 i_SIU/RXDATA_INST/NOT_ix52268z24340:A (f) + 0.384 cell: ADLIB:NAND2 5.779 i_SIU/RXDATA_INST/NOT_ix52268z24340:Y (r) + 0.303 net: i_SIU/RXDATA_INST/nx52268z3 6.082 i_SIU/RXDATA_INST/NOT_ix54262z50932:A (r) + 0.509 cell: ADLIB:NAND3A 6.591 i_SIU/RXDATA_INST/NOT_ix54262z50932:Y (r) + 1.269 net: i_SIU/RXDATA_INST/nx54262z3 7.860 i_SIU/RXDATA_INST/NOT_ix58250z50934:A (r) + 0.347 cell: ADLIB:NAND3C 8.207 i_SIU/RXDATA_INST/NOT_ix58250z50934:Y (r) + 0.249 net: i_SIU/RXDATA_INST/nx58250z3 8.456 i_SIU/RXDATA_INST/ix58250z64468:B (r) + 0.546 cell: ADLIB:AOI1 9.002 i_SIU/RXDATA_INST/ix58250z64468:Y (f) + 0.241 net: i_SIU/RXDATA_INST/nx58250z2 9.243 i_SIU/RXDATA_INST/ix58250z4191:B (f) + 0.707 cell: ADLIB:AXOI5 9.950 i_SIU/RXDATA_INST/ix58250z4191:Y (r) + 0.249 net: i_SIU/RXDATA_INST/nx58250z1 10.199 i_SIU/RXDATA_INST/reg_q(7):D (r) 10.199 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.683 net: SIU_RXCLK_cb 13.299 i_SIU/RXDATA_INST/reg_q(7):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 12.871 i_SIU/RXDATA_INST/reg_q(7):D 12.871 data required time Expanded Path 4 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(11):D data required time 12.765 data arrival time - 10.054 slack 2.711 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.569 net: SIU_RXCLK_cb 4.094 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.644 i_SIU/reg_q(16):Q (f) + 0.521 net: i_SIU/RXIN_INST_v_por_timer_16_ 5.165 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 5.726 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 6.056 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.553 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 7.300 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.692 i_SIU/NOT_a(0):Y (f) + 0.647 net: i_SIU/NOT_a_0_ 8.339 i_SIU/NOT_ix18093z50932:A (f) + 0.496 cell: ADLIB:NAND3B 8.835 i_SIU/NOT_ix18093z50932:Y (f) + 0.241 net: i_SIU/nx18093z2 9.076 i_SIU/ix18093z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.813 i_SIU/ix18093z21032:Y (f) + 0.241 net: i_SIU/nx18093z1 10.054 i_SIU/reg_q(11):D (f) 10.054 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.551 net: SIU_RXCLK_cb 13.167 i_SIU/reg_q(11):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.765 i_SIU/reg_q(11):D 12.765 data required time Expanded Path 5 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(10):D data required time 12.814 data arrival time - 10.039 slack 2.775 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.551 net: SIU_RXCLK_cb 4.076 i_SIU/reg_q(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.510 i_SIU/reg_q(1):Q (r) + 0.303 net: i_SIU/nx32078z4 4.813 i_SIU/NOT_ix32078z50931:C (r) + 0.466 cell: ADLIB:NAND3A 5.279 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 5.609 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.106 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 6.853 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.245 i_SIU/NOT_a(0):Y (f) + 1.080 net: i_SIU/NOT_a_0_ 8.325 i_SIU/NOT_ix17096z50931:A (f) + 0.497 cell: ADLIB:NAND3A 8.822 i_SIU/NOT_ix17096z50931:Y (f) + 0.241 net: i_SIU/nx17096z2 9.063 i_SIU/ix17096z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.800 i_SIU/ix17096z21032:Y (f) + 0.239 net: i_SIU/nx17096z1 10.039 i_SIU/reg_q(10):D (f) 10.039 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.600 net: SIU_RXCLK_cb 13.216 i_SIU/reg_q(10):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.814 i_SIU/reg_q(10):D 12.814 data required time Expanded Path 6 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(16):D data required time 12.783 data arrival time - 10.006 slack 2.777 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.569 net: SIU_RXCLK_cb 4.094 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.644 i_SIU/reg_q(16):Q (f) + 0.521 net: i_SIU/RXIN_INST_v_por_timer_16_ 5.165 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 5.726 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 6.056 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.553 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 7.300 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.692 i_SIU/NOT_a(0):Y (f) + 0.703 net: i_SIU/NOT_a_0_ 8.395 i_SIU/NOT_ix23078z50933:A (f) + 0.392 cell: ADLIB:NAND3C 8.787 i_SIU/NOT_ix23078z50933:Y (f) + 0.241 net: i_SIU/nx23078z2 9.028 i_SIU/ix23078z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.765 i_SIU/ix23078z21032:Y (f) + 0.241 net: i_SIU/nx23078z1 10.006 i_SIU/reg_q(16):D (f) 10.006 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.569 net: SIU_RXCLK_cb 13.185 i_SIU/reg_q(16):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.783 i_SIU/reg_q(16):D 12.783 data required time Expanded Path 7 From: i_SIU/reg_q(0):CLK To: i_SIU/reg_q(10):D data required time 12.814 data arrival time - 10.007 slack 2.807 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.551 net: SIU_RXCLK_cb 4.076 i_SIU/reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.510 i_SIU/reg_q(0):Q (r) + 0.345 net: i_SIU/nx32078z3 4.855 i_SIU/NOT_ix32078z50931:B (r) + 0.392 cell: ADLIB:NAND3A 5.247 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 5.577 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.074 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 6.821 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.213 i_SIU/NOT_a(0):Y (f) + 1.080 net: i_SIU/NOT_a_0_ 8.293 i_SIU/NOT_ix17096z50931:A (f) + 0.497 cell: ADLIB:NAND3A 8.790 i_SIU/NOT_ix17096z50931:Y (f) + 0.241 net: i_SIU/nx17096z2 9.031 i_SIU/ix17096z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.768 i_SIU/ix17096z21032:Y (f) + 0.239 net: i_SIU/nx17096z1 10.007 i_SIU/reg_q(10):D (f) 10.007 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.600 net: SIU_RXCLK_cb 13.216 i_SIU/reg_q(10):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.814 i_SIU/reg_q(10):D 12.814 data required time Expanded Path 8 From: i_SIU/reg_q(16):CLK To: i_SIU/reg_q(12):D data required time 12.799 data arrival time - 9.981 slack 2.818 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.569 net: SIU_RXCLK_cb 4.094 i_SIU/reg_q(16):CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.644 i_SIU/reg_q(16):Q (f) + 0.521 net: i_SIU/RXIN_INST_v_por_timer_16_ 5.165 i_SIU/NOT_ix32078z50931:A (f) + 0.561 cell: ADLIB:NAND3A 5.726 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 6.056 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.553 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 7.300 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.692 i_SIU/NOT_a(0):Y (f) + 0.671 net: i_SIU/NOT_a_0_ 8.363 i_SIU/NOT_ix19090z49935:A (f) + 0.401 cell: ADLIB:NAND2B 8.764 i_SIU/NOT_ix19090z49935:Y (f) + 0.241 net: i_SIU/nx19090z2 9.005 i_SIU/ix19090z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.742 i_SIU/ix19090z21032:Y (f) + 0.239 net: i_SIU/nx19090z1 9.981 i_SIU/reg_q(12):D (f) 9.981 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.585 net: SIU_RXCLK_cb 13.201 i_SIU/reg_q(12):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.799 i_SIU/reg_q(12):D 12.799 data required time Expanded Path 9 From: i_SIU/reg_q(1):CLK To: i_SIU/reg_q(9):D data required time 12.828 data arrival time - 9.930 slack 2.898 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.551 net: SIU_RXCLK_cb 4.076 i_SIU/reg_q(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.510 i_SIU/reg_q(1):Q (r) + 0.303 net: i_SIU/nx32078z4 4.813 i_SIU/NOT_ix32078z50931:C (r) + 0.466 cell: ADLIB:NAND3A 5.279 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 5.609 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.106 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 6.853 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.245 i_SIU/NOT_a(0):Y (f) + 0.983 net: i_SIU/NOT_a_0_ 8.228 i_SIU/NOT_ix60244z49934:A (f) + 0.485 cell: ADLIB:NAND2A 8.713 i_SIU/NOT_ix60244z49934:Y (f) + 0.241 net: i_SIU/nx60244z2 8.954 i_SIU/ix60244z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.691 i_SIU/ix60244z21032:Y (f) + 0.239 net: i_SIU/nx60244z1 9.930 i_SIU/reg_q(9):D (f) 9.930 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.614 net: SIU_RXCLK_cb 13.230 i_SIU/reg_q(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.828 i_SIU/reg_q(9):D 12.828 data required time Expanded Path 10 From: i_SIU/reg_q(0):CLK To: i_SIU/reg_q(9):D data required time 12.828 data arrival time - 9.898 slack 2.930 ________________________________________________________ Data arrival time calculation 0.000 SIU_RXCLK + 0.000 Clock source 0.000 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 0.000 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 1.129 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 2.967 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.525 cbuf_SIU_RXCLK:Y (r) + 0.551 net: SIU_RXCLK_cb 4.076 i_SIU/reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.510 i_SIU/reg_q(0):Q (r) + 0.345 net: i_SIU/nx32078z3 4.855 i_SIU/NOT_ix32078z50931:B (r) + 0.392 cell: ADLIB:NAND3A 5.247 i_SIU/NOT_ix32078z50931:Y (f) + 0.330 net: i_SIU/nx32078z2 5.577 i_SIU/NOT_ix32078z50930:A (f) + 0.497 cell: ADLIB:NAND3A 6.074 i_SIU/NOT_ix32078z50930:Y (f) + 0.747 net: i_SIU/nx32078z1 6.821 i_SIU/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 7.213 i_SIU/NOT_a(0):Y (f) + 0.983 net: i_SIU/NOT_a_0_ 8.196 i_SIU/NOT_ix60244z49934:A (f) + 0.485 cell: ADLIB:NAND2A 8.681 i_SIU/NOT_ix60244z49934:Y (f) + 0.241 net: i_SIU/nx60244z2 8.922 i_SIU/ix60244z21032:B (f) + 0.737 cell: ADLIB:XA1A 9.659 i_SIU/ix60244z21032:Y (f) + 0.239 net: i_SIU/nx60244z1 9.898 i_SIU/reg_q(9):D (f) 9.898 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_RXCLK + 0.000 Clock source 9.091 SIU_RXCLK (r) + 0.000 net: SIU_RXCLK 9.091 ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 10.220 ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i 12.058 cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.616 cbuf_SIU_RXCLK:Y (r) + 0.614 net: SIU_RXCLK_cb 13.230 i_SIU/reg_q(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.828 i_SIU/reg_q(9):D 12.828 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: SIU_RXD(11) To: addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.647 Path 2 From: SIU_RXD(8) To: addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.647 Path 3 From: SIU_RXD(15) To: addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.639 Path 4 From: SIU_RXD(4) To: addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.639 Path 5 From: SIU_RXD(5) To: addds[5].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.639 Path 6 From: SIU_RXD(14) To: addds[14].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.639 Path 7 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.638 Path 8 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.638 Path 9 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.638 Path 10 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN Delay (ns): 5.547 Slack (ns): Arrival (ns): 5.547 Required (ns): Setup (ns): 0.226 External Setup (ns): 1.638 Expanded Path 1 From: SIU_RXD(11) To: addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(11) (r) + 0.000 net: SIU_RXD_11_ 0.000 addds[11].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[11].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[11]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.601 net: SIU_RXCLK_cb N/C addds[11].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[11].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 2 From: SIU_RXD(8) To: addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(8) (r) + 0.000 net: SIU_RXD_8_ 0.000 addds[8].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[8].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[8]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.601 net: SIU_RXCLK_cb N/C addds[8].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[8].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 3 From: SIU_RXD(15) To: addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(15) (r) + 0.000 net: SIU_RXD_15_ 0.000 addds[15].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[15].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[15]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.609 net: SIU_RXCLK_cb N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[15].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 4 From: SIU_RXD(4) To: addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(4) (r) + 0.000 net: SIU_RXD_4_ 0.000 addds[4].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[4].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[4]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.609 net: SIU_RXCLK_cb N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[4].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 5 From: SIU_RXD(5) To: addds[5].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(5) (r) + 0.000 net: SIU_RXD_5_ 0.000 addds[5].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[5].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[5]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[5].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.609 net: SIU_RXCLK_cb N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[5].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 6 From: SIU_RXD(14) To: addds[14].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(14) (r) + 0.000 net: SIU_RXD_14_ 0.000 addds[14].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[14].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[14]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[14].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.609 net: SIU_RXCLK_cb N/C addds[14].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[14].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 7 From: SIU_RXDV To: ibuf_SIU_RXDV_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXDV (r) + 0.000 net: SIU_RXDV 0.000 ibuf_SIU_RXDV_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 ibuf_SIU_RXDV_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXDV_ib/U0/NET1 5.547 ibuf_SIU_RXDV_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.610 net: SIU_RXCLK_cb N/C ibuf_SIU_RXDV_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXDV_ib/U0/U1:YIN Expanded Path 8 From: SIU_RXD(7) To: addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(7) (r) + 0.000 net: SIU_RXD_7_ 0.000 addds[7].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[7].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[7]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.610 net: SIU_RXCLK_cb N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[7].ibuf_SIU_RXD_ib/U0/U1:YIN Expanded Path 9 From: SIU_RXER To: ibuf_SIU_RXER_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXER (r) + 0.000 net: SIU_RXER 0.000 ibuf_SIU_RXER_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 ibuf_SIU_RXER_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXER_ib/U0/NET1 5.547 ibuf_SIU_RXER_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.610 net: SIU_RXCLK_cb N/C ibuf_SIU_RXER_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C ibuf_SIU_RXER_ib/U0/U1:YIN Expanded Path 10 From: SIU_RXD(9) To: addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN data required time N/C data arrival time - 5.547 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_RXD(9) (r) + 0.000 net: SIU_RXD_9_ 0.000 addds[9].ibuf_SIU_RXD_ib/U0/U0:PAD (r) + 5.547 cell: ADLIB:IOPAD_IN 5.547 addds[9].ibuf_SIU_RXD_ib/U0/U0:Y (r) + 0.000 net: addds[9]_ibuf_SIU_RXD_ib/U0/NET1 5.547 addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN (r) 5.547 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.610 net: SIU_RXCLK_cb N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:ICLK (r) - 0.226 Library setup time: ADLIB:IOIN_IRC N/C addds[9].ibuf_SIU_RXD_ib/U0/U1:YIN END SET External Setup ---------------------------------------------------- SET Clock to Output No Path END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: i_SIU/modgen_counter_srst_count_reg_q(0):CLR Delay (ns): 12.085 Slack (ns): Arrival (ns): 12.085 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.236 Path 2 From: RST_n To: i_SIU/modgen_counter_srst_count_reg_q(0):CLR Delay (ns): 11.891 Slack (ns): Arrival (ns): 11.891 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.042 Path 3 From: PUSHB To: i_SIU/reg_b_rx_data:CLR Delay (ns): 11.802 Slack (ns): Arrival (ns): 11.802 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.936 Path 4 From: PUSHB To: i_SIU/reg_b_rx_cext_d1:CLR Delay (ns): 11.802 Slack (ns): Arrival (ns): 11.802 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.936 Path 5 From: PUSHB To: i_SIU/reg_b_srst_set:CLR Delay (ns): 11.802 Slack (ns): Arrival (ns): 11.802 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.936 Path 6 From: RST_n To: i_SIU/reg_b_rx_data:CLR Delay (ns): 11.608 Slack (ns): Arrival (ns): 11.608 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.742 Path 7 From: RST_n To: i_SIU/reg_b_rx_cext_d1:CLR Delay (ns): 11.608 Slack (ns): Arrival (ns): 11.608 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.742 Path 8 From: RST_n To: i_SIU/reg_b_srst_set:CLR Delay (ns): 11.608 Slack (ns): Arrival (ns): 11.608 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.742 Path 9 From: PUSHB To: i_SIU/modgen_counter_srst_count_reg_q(1):CLR Delay (ns): 11.463 Slack (ns): Arrival (ns): 11.463 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.614 Path 10 From: PUSHB To: i_SIU/reg_b_srst_nset:CLR Delay (ns): 11.463 Slack (ns): Arrival (ns): 11.463 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.597 Expanded Path 1 From: PUSHB To: i_SIU/modgen_counter_srst_count_reg_q(0):CLR data required time N/C data arrival time - 12.085 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 6.532 net: not_rst_n 12.085 i_SIU/modgen_counter_srst_count_reg_q(0):CLR (f) 12.085 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.546 net: SIU_RXCLK_cb N/C i_SIU/modgen_counter_srst_count_reg_q(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/modgen_counter_srst_count_reg_q(0):CLR Expanded Path 2 From: RST_n To: i_SIU/modgen_counter_srst_count_reg_q(0):CLR data required time N/C data arrival time - 11.891 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 6.532 net: not_rst_n 11.891 i_SIU/modgen_counter_srst_count_reg_q(0):CLR (f) 11.891 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.546 net: SIU_RXCLK_cb N/C i_SIU/modgen_counter_srst_count_reg_q(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/modgen_counter_srst_count_reg_q(0):CLR Expanded Path 3 From: PUSHB To: i_SIU/reg_b_rx_data:CLR data required time N/C data arrival time - 11.802 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 6.249 net: not_rst_n 11.802 i_SIU/reg_b_rx_data:CLR (f) 11.802 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_rx_data:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_rx_data:CLR Expanded Path 4 From: PUSHB To: i_SIU/reg_b_rx_cext_d1:CLR data required time N/C data arrival time - 11.802 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 6.249 net: not_rst_n 11.802 i_SIU/reg_b_rx_cext_d1:CLR (f) 11.802 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_rx_cext_d1:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_rx_cext_d1:CLR Expanded Path 5 From: PUSHB To: i_SIU/reg_b_srst_set:CLR data required time N/C data arrival time - 11.802 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 6.249 net: not_rst_n 11.802 i_SIU/reg_b_srst_set:CLR (f) 11.802 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_srst_set:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_srst_set:CLR Expanded Path 6 From: RST_n To: i_SIU/reg_b_rx_data:CLR data required time N/C data arrival time - 11.608 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 6.249 net: not_rst_n 11.608 i_SIU/reg_b_rx_data:CLR (f) 11.608 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_rx_data:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_rx_data:CLR Expanded Path 7 From: RST_n To: i_SIU/reg_b_rx_cext_d1:CLR data required time N/C data arrival time - 11.608 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 6.249 net: not_rst_n 11.608 i_SIU/reg_b_rx_cext_d1:CLR (f) 11.608 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_rx_cext_d1:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_rx_cext_d1:CLR Expanded Path 8 From: RST_n To: i_SIU/reg_b_srst_set:CLR data required time N/C data arrival time - 11.608 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 6.249 net: not_rst_n 11.608 i_SIU/reg_b_srst_set:CLR (f) 11.608 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_srst_set:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_srst_set:CLR Expanded Path 9 From: PUSHB To: i_SIU/modgen_counter_srst_count_reg_q(1):CLR data required time N/C data arrival time - 11.463 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 5.910 net: not_rst_n 11.463 i_SIU/modgen_counter_srst_count_reg_q(1):CLR (f) 11.463 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.546 net: SIU_RXCLK_cb N/C i_SIU/modgen_counter_srst_count_reg_q(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/modgen_counter_srst_count_reg_q(1):CLR Expanded Path 10 From: PUSHB To: i_SIU/reg_b_srst_nset:CLR data required time N/C data arrival time - 11.463 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 5.910 net: not_rst_n 11.463 i_SIU/reg_b_srst_nset:CLR (f) 11.463 data arrival time ________________________________________________________ Data required time calculation N/C SIU_RXCLK + 0.000 Clock source N/C SIU_RXCLK (r) + 0.000 net: SIU_RXCLK N/C ibuf_SIU_RXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_RXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_RXCLK_ib/U0/NET1 N/C ibuf_SIU_RXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_RXCLK_ib/U0/U1:Y (r) + 1.806 net: SIU_RXCLK_i N/C cbuf_SIU_RXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_RXCLK:Y (r) + 0.563 net: SIU_RXCLK_cb N/C i_SIU/reg_b_srst_nset:CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_SIU/reg_b_srst_nset:CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain SIU_TXCLK SET Register to Register Path 1 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_tx_present(6):D Delay (ns): 6.183 Slack (ns): 2.372 Arrival (ns): 10.638 Required (ns): 13.010 Setup (ns): 0.402 Minimum Period (ns): 6.719 Path 2 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_tx_present(16):D Delay (ns): 6.171 Slack (ns): 2.381 Arrival (ns): 10.626 Required (ns): 13.007 Setup (ns): 0.402 Minimum Period (ns): 6.710 Path 3 From: i_SIU/CMSIU_INST/reg_q(0):CLK To: i_SIU/CMSIU_INST/reg_q(13):D Delay (ns): 6.186 Slack (ns): 2.397 Arrival (ns): 10.569 Required (ns): 12.966 Setup (ns): 0.402 Minimum Period (ns): 6.694 Path 4 From: i_SIU/FRAMING_INST/reg_tx_present(14):CLK To: i_SIU/FRAMING_INST/reg_txd_sts2(12):D Delay (ns): 6.171 Slack (ns): 2.518 Arrival (ns): 10.548 Required (ns): 13.066 Setup (ns): 0.402 Minimum Period (ns): 6.573 Path 5 From: i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK To: i_SIU/LMSIU_INST/reg_q(9)_dup_371:D Delay (ns): 6.089 Slack (ns): 2.585 Arrival (ns): 10.416 Required (ns): 13.001 Setup (ns): 0.402 Minimum Period (ns): 6.506 Path 6 From: i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK To: i_SIU/LMSIU_INST/reg_q(10)_dup_370:D Delay (ns): 6.064 Slack (ns): 2.610 Arrival (ns): 10.391 Required (ns): 13.001 Setup (ns): 0.402 Minimum Period (ns): 6.481 Path 7 From: i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK To: i_SIU/LMSIU_INST/reg_q(12):D Delay (ns): 6.038 Slack (ns): 2.678 Arrival (ns): 10.365 Required (ns): 13.043 Setup (ns): 0.402 Minimum Period (ns): 6.413 Path 8 From: i_SIU/FRAMING_INST/reg_tx_present(11):CLK To: i_SIU/FRAMING_INST/reg_txd_sts2(12):D Delay (ns): 6.064 Slack (ns): 2.681 Arrival (ns): 10.385 Required (ns): 13.066 Setup (ns): 0.402 Minimum Period (ns): 6.410 Path 9 From: i_SIU/LMSIU_INST/reg_q(1)_dup_379:CLK To: i_SIU/LMSIU_INST/reg_q(9)_dup_371:D Delay (ns): 5.936 Slack (ns): 2.712 Arrival (ns): 10.289 Required (ns): 13.001 Setup (ns): 0.402 Minimum Period (ns): 6.379 Path 10 From: i_SIU/LMSIU_INST/reg_q(1)_dup_379:CLK To: i_SIU/LMSIU_INST/reg_q(10)_dup_370:D Delay (ns): 5.911 Slack (ns): 2.737 Arrival (ns): 10.264 Required (ns): 13.001 Setup (ns): 0.402 Minimum Period (ns): 6.354 Expanded Path 1 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_tx_present(6):D data required time 13.010 data arrival time - 10.638 slack 2.372 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.998 net: SIU_TXCLK_cb 4.455 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) + 2.165 cell: ADLIB:FIFO4K18 6.620 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RD15 (r) + 1.358 net: i_SIU/s_txdf_q_33_ 7.978 i_SIU/FRAMING_INST/NOT_specflag_2n4s1:A (r) + 0.304 cell: ADLIB:NAND2 8.282 i_SIU/FRAMING_INST/NOT_specflag_2n4s1:Y (f) + 0.339 net: i_SIU/FRAMING_INST/NOT_specflag_2n4s1 8.621 i_SIU/FRAMING_INST/ix48632z50933:C (f) + 0.561 cell: ADLIB:NAND3C 9.182 i_SIU/FRAMING_INST/ix48632z50933:Y (f) + 0.461 net: i_SIU/FRAMING_INST/nx48632z2 9.643 i_SIU/FRAMING_INST/ix48632z47388:B (f) + 0.735 cell: ADLIB:AOI1A 10.378 i_SIU/FRAMING_INST/ix48632z47388:Y (r) + 0.260 net: i_SIU/FRAMING_INST/nx48632z1 10.638 i_SIU/FRAMING_INST/reg_tx_present(6):D (r) 10.638 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.864 net: SIU_TXCLK_cb 13.412 i_SIU/FRAMING_INST/reg_tx_present(6):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.010 i_SIU/FRAMING_INST/reg_tx_present(6):D 13.010 data required time Expanded Path 2 From: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK To: i_SIU/FRAMING_INST/reg_tx_present(16):D data required time 13.007 data arrival time - 10.626 slack 2.381 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.998 net: SIU_TXCLK_cb 4.455 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) + 2.131 cell: ADLIB:FIFO4K18 6.586 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RD15 (f) + 1.293 net: i_SIU/s_txdf_q_33_ 7.879 i_SIU/FRAMING_INST/NOT_specflag_2n4s1:A (f) + 0.288 cell: ADLIB:NAND2 8.167 i_SIU/FRAMING_INST/NOT_specflag_2n4s1:Y (r) + 0.355 net: i_SIU/FRAMING_INST/NOT_specflag_2n4s1 8.522 i_SIU/FRAMING_INST/ix52379z50932:C (r) + 0.392 cell: ADLIB:NAND3B 8.914 i_SIU/FRAMING_INST/ix52379z50932:Y (f) + 0.296 net: i_SIU/FRAMING_INST/nx52379z2 9.210 i_SIU/FRAMING_INST/ix52379z47388:B (f) + 0.735 cell: ADLIB:AOI1A 9.945 i_SIU/FRAMING_INST/ix52379z47388:Y (r) + 0.681 net: i_SIU/FRAMING_INST/nx52379z1 10.626 i_SIU/FRAMING_INST/reg_tx_present(16):D (r) 10.626 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.861 net: SIU_TXCLK_cb 13.409 i_SIU/FRAMING_INST/reg_tx_present(16):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.007 i_SIU/FRAMING_INST/reg_tx_present(16):D 13.007 data required time Expanded Path 3 From: i_SIU/CMSIU_INST/reg_q(0):CLK To: i_SIU/CMSIU_INST/reg_q(13):D data required time 12.966 data arrival time - 10.569 slack 2.397 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.926 net: SIU_TXCLK_cb 4.383 i_SIU/CMSIU_INST/reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.817 i_SIU/CMSIU_INST/reg_q(0):Q (r) + 0.786 net: i_SIU/CMSIU_INST/nx52268z2 5.603 i_SIU/CMSIU_INST/NOT_ix22081z24342:B (r) + 0.386 cell: ADLIB:NAND2 5.989 i_SIU/CMSIU_INST/NOT_ix22081z24342:Y (f) + 0.288 net: i_SIU/CMSIU_INST/nx22081z5 6.277 i_SIU/CMSIU_INST/NOT_ix22081z50933:A (f) + 0.561 cell: ADLIB:NAND3A 6.838 i_SIU/CMSIU_INST/NOT_ix22081z50933:Y (f) + 0.910 net: i_SIU/CMSIU_INST/nx22081z4 7.748 i_SIU/CMSIU_INST/NOT_a(0):A (f) + 0.392 cell: ADLIB:NAND3C 8.140 i_SIU/CMSIU_INST/NOT_a(0):Y (f) + 0.711 net: i_SIU/CMSIU_INST/NOT_a_0_ 8.851 i_SIU/CMSIU_INST/NOT_ix20087z50932:A (f) + 0.496 cell: ADLIB:NAND3B 9.347 i_SIU/CMSIU_INST/NOT_ix20087z50932:Y (f) + 0.244 net: i_SIU/CMSIU_INST/nx20087z2 9.591 i_SIU/CMSIU_INST/ix20087z21032:B (f) + 0.737 cell: ADLIB:XA1A 10.328 i_SIU/CMSIU_INST/ix20087z21032:Y (f) + 0.241 net: i_SIU/CMSIU_INST/nx20087z1 10.569 i_SIU/CMSIU_INST/reg_q(13):D (f) 10.569 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.820 net: SIU_TXCLK_cb 13.368 i_SIU/CMSIU_INST/reg_q(13):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 12.966 i_SIU/CMSIU_INST/reg_q(13):D 12.966 data required time Expanded Path 4 From: i_SIU/FRAMING_INST/reg_tx_present(14):CLK To: i_SIU/FRAMING_INST/reg_txd_sts2(12):D data required time 13.066 data arrival time - 10.548 slack 2.518 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.920 net: SIU_TXCLK_cb 4.377 i_SIU/FRAMING_INST/reg_tx_present(14):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.811 i_SIU/FRAMING_INST/reg_tx_present(14):Q (r) + 0.858 net: i_SIU/FRAMING_INST/tx_present_14_ 5.669 i_SIU/FRAMING_INST/ix50624z49935:B (r) + 0.384 cell: ADLIB:NAND2B 6.053 i_SIU/FRAMING_INST/ix50624z49935:Y (r) + 0.808 net: i_SIU/FRAMING_INST/nx50624z2 6.861 i_SIU/FRAMING_INST/ix49627z47392:B (r) + 0.680 cell: ADLIB:AOI1D 7.541 i_SIU/FRAMING_INST/ix49627z47392:Y (r) + 0.841 net: i_SIU/FRAMING_INST/nx49627z2 8.382 i_SIU/FRAMING_INST/ix47633z24339:A (r) + 0.365 cell: ADLIB:NAND2 8.747 i_SIU/FRAMING_INST/ix47633z24339:Y (f) + 0.239 net: i_SIU/FRAMING_INST/nx47633z2 8.986 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(12):B (f) + 0.456 cell: ADLIB:MX2B 9.442 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(12):Y (r) + 1.106 net: i_SIU/FRAMING_INST/txd_sts2_2n22ss1_12_ 10.548 i_SIU/FRAMING_INST/reg_txd_sts2(12):D (r) 10.548 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.920 net: SIU_TXCLK_cb 13.468 i_SIU/FRAMING_INST/reg_txd_sts2(12):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.066 i_SIU/FRAMING_INST/reg_txd_sts2(12):D 13.066 data required time Expanded Path 5 From: i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK To: i_SIU/LMSIU_INST/reg_q(9)_dup_371:D data required time 13.001 data arrival time - 10.416 slack 2.585 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.870 net: SIU_TXCLK_cb 4.327 i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.877 i_SIU/LMSIU_INST/reg_q(0)_dup_380:Q (f) + 0.389 net: i_SIU/LMSIU_INST/nx33974z2 5.266 i_SIU/LMSIU_INST/NOT_ix32078z24339:B (f) + 0.469 cell: ADLIB:NAND2 5.735 i_SIU/LMSIU_INST/NOT_ix32078z24339:Y (r) + 0.303 net: i_SIU/LMSIU_INST/nx32078z2 6.038 i_SIU/LMSIU_INST/NOT_ix32078z50930:A (r) + 0.509 cell: ADLIB:NAND3A 6.547 i_SIU/LMSIU_INST/NOT_ix32078z50930:Y (r) + 0.817 net: i_SIU/LMSIU_INST/nx32078z1 7.364 i_SIU/LMSIU_INST/NOT_a(0):A (r) + 0.347 cell: ADLIB:NAND3C 7.711 i_SIU/LMSIU_INST/NOT_a(0):Y (r) + 1.005 net: i_SIU/LMSIU_INST/NOT_a_0_ 8.716 i_SIU/LMSIU_INST/ix42710z14340:A (r) + 0.705 cell: ADLIB:AX1 9.421 i_SIU/LMSIU_INST/ix42710z14340:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx42710z2 9.670 i_SIU/LMSIU_INST/ix42710z2956:C (r) + 0.497 cell: ADLIB:AND3A 10.167 i_SIU/LMSIU_INST/ix42710z2956:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx42710z1 10.416 i_SIU/LMSIU_INST/reg_q(9)_dup_371:D (r) 10.416 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.855 net: SIU_TXCLK_cb 13.403 i_SIU/LMSIU_INST/reg_q(9)_dup_371:CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.001 i_SIU/LMSIU_INST/reg_q(9)_dup_371:D 13.001 data required time Expanded Path 6 From: i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK To: i_SIU/LMSIU_INST/reg_q(10)_dup_370:D data required time 13.001 data arrival time - 10.391 slack 2.610 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.870 net: SIU_TXCLK_cb 4.327 i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.877 i_SIU/LMSIU_INST/reg_q(0)_dup_380:Q (f) + 0.389 net: i_SIU/LMSIU_INST/nx33974z2 5.266 i_SIU/LMSIU_INST/NOT_ix32078z24339:B (f) + 0.469 cell: ADLIB:NAND2 5.735 i_SIU/LMSIU_INST/NOT_ix32078z24339:Y (r) + 0.303 net: i_SIU/LMSIU_INST/nx32078z2 6.038 i_SIU/LMSIU_INST/NOT_ix32078z50930:A (r) + 0.509 cell: ADLIB:NAND3A 6.547 i_SIU/LMSIU_INST/NOT_ix32078z50930:Y (r) + 0.817 net: i_SIU/LMSIU_INST/nx32078z1 7.364 i_SIU/LMSIU_INST/NOT_a(0):A (r) + 0.347 cell: ADLIB:NAND3C 7.711 i_SIU/LMSIU_INST/NOT_a(0):Y (r) + 0.980 net: i_SIU/LMSIU_INST/NOT_a_0_ 8.691 i_SIU/LMSIU_INST/ix39991z8206:A (r) + 0.705 cell: ADLIB:AX1B 9.396 i_SIU/LMSIU_INST/ix39991z8206:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx39991z2 9.645 i_SIU/LMSIU_INST/ix39991z2956:C (r) + 0.497 cell: ADLIB:AND3A 10.142 i_SIU/LMSIU_INST/ix39991z2956:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx39991z1 10.391 i_SIU/LMSIU_INST/reg_q(10)_dup_370:D (r) 10.391 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.855 net: SIU_TXCLK_cb 13.403 i_SIU/LMSIU_INST/reg_q(10)_dup_370:CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.001 i_SIU/LMSIU_INST/reg_q(10)_dup_370:D 13.001 data required time Expanded Path 7 From: i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK To: i_SIU/LMSIU_INST/reg_q(12):D data required time 13.043 data arrival time - 10.365 slack 2.678 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.870 net: SIU_TXCLK_cb 4.327 i_SIU/LMSIU_INST/reg_q(0)_dup_380:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.877 i_SIU/LMSIU_INST/reg_q(0)_dup_380:Q (f) + 0.389 net: i_SIU/LMSIU_INST/nx33974z2 5.266 i_SIU/LMSIU_INST/NOT_ix32078z24339:B (f) + 0.469 cell: ADLIB:NAND2 5.735 i_SIU/LMSIU_INST/NOT_ix32078z24339:Y (r) + 0.303 net: i_SIU/LMSIU_INST/nx32078z2 6.038 i_SIU/LMSIU_INST/NOT_ix32078z50930:A (r) + 0.509 cell: ADLIB:NAND3A 6.547 i_SIU/LMSIU_INST/NOT_ix32078z50930:Y (r) + 0.817 net: i_SIU/LMSIU_INST/nx32078z1 7.364 i_SIU/LMSIU_INST/NOT_a(0):A (r) + 0.347 cell: ADLIB:NAND3C 7.711 i_SIU/LMSIU_INST/NOT_a(0):Y (r) + 0.951 net: i_SIU/LMSIU_INST/NOT_a_0_ 8.662 i_SIU/LMSIU_INST/ix19090z8206:A (r) + 0.705 cell: ADLIB:AX1B 9.367 i_SIU/LMSIU_INST/ix19090z8206:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx19090z2 9.616 i_SIU/LMSIU_INST/ix19090z2956:C (r) + 0.497 cell: ADLIB:AND3A 10.113 i_SIU/LMSIU_INST/ix19090z2956:Y (r) + 0.252 net: i_SIU/LMSIU_INST/nx19090z1 10.365 i_SIU/LMSIU_INST/reg_q(12):D (r) 10.365 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.897 net: SIU_TXCLK_cb 13.445 i_SIU/LMSIU_INST/reg_q(12):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.043 i_SIU/LMSIU_INST/reg_q(12):D 13.043 data required time Expanded Path 8 From: i_SIU/FRAMING_INST/reg_tx_present(11):CLK To: i_SIU/FRAMING_INST/reg_txd_sts2(12):D data required time 13.066 data arrival time - 10.385 slack 2.681 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.864 net: SIU_TXCLK_cb 4.321 i_SIU/FRAMING_INST/reg_tx_present(11):CLK (r) + 0.434 cell: ADLIB:DFN1C0 4.755 i_SIU/FRAMING_INST/reg_tx_present(11):Q (r) + 0.361 net: i_SIU/FRAMING_INST/tx_present_11_ 5.116 i_SIU/FRAMING_INST/ix50624z49937:B (r) + 0.384 cell: ADLIB:NAND2B 5.500 i_SIU/FRAMING_INST/ix50624z49937:Y (r) + 1.181 net: i_SIU/FRAMING_INST/nx50624z4 6.681 i_SIU/FRAMING_INST/ix49627z47392:A (r) + 0.697 cell: ADLIB:AOI1D 7.378 i_SIU/FRAMING_INST/ix49627z47392:Y (r) + 0.841 net: i_SIU/FRAMING_INST/nx49627z2 8.219 i_SIU/FRAMING_INST/ix47633z24339:A (r) + 0.365 cell: ADLIB:NAND2 8.584 i_SIU/FRAMING_INST/ix47633z24339:Y (f) + 0.239 net: i_SIU/FRAMING_INST/nx47633z2 8.823 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(12):B (f) + 0.456 cell: ADLIB:MX2B 9.279 i_SIU/FRAMING_INST/txd_sts2_2n22ss1(12):Y (r) + 1.106 net: i_SIU/FRAMING_INST/txd_sts2_2n22ss1_12_ 10.385 i_SIU/FRAMING_INST/reg_txd_sts2(12):D (r) 10.385 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.920 net: SIU_TXCLK_cb 13.468 i_SIU/FRAMING_INST/reg_txd_sts2(12):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.066 i_SIU/FRAMING_INST/reg_txd_sts2(12):D 13.066 data required time Expanded Path 9 From: i_SIU/LMSIU_INST/reg_q(1)_dup_379:CLK To: i_SIU/LMSIU_INST/reg_q(9)_dup_371:D data required time 13.001 data arrival time - 10.289 slack 2.712 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.896 net: SIU_TXCLK_cb 4.353 i_SIU/LMSIU_INST/reg_q(1)_dup_379:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.903 i_SIU/LMSIU_INST/reg_q(1)_dup_379:Q (f) + 0.321 net: i_SIU/LMSIU_INST/nx32078z3 5.224 i_SIU/LMSIU_INST/NOT_ix32078z24339:A (f) + 0.384 cell: ADLIB:NAND2 5.608 i_SIU/LMSIU_INST/NOT_ix32078z24339:Y (r) + 0.303 net: i_SIU/LMSIU_INST/nx32078z2 5.911 i_SIU/LMSIU_INST/NOT_ix32078z50930:A (r) + 0.509 cell: ADLIB:NAND3A 6.420 i_SIU/LMSIU_INST/NOT_ix32078z50930:Y (r) + 0.817 net: i_SIU/LMSIU_INST/nx32078z1 7.237 i_SIU/LMSIU_INST/NOT_a(0):A (r) + 0.347 cell: ADLIB:NAND3C 7.584 i_SIU/LMSIU_INST/NOT_a(0):Y (r) + 1.005 net: i_SIU/LMSIU_INST/NOT_a_0_ 8.589 i_SIU/LMSIU_INST/ix42710z14340:A (r) + 0.705 cell: ADLIB:AX1 9.294 i_SIU/LMSIU_INST/ix42710z14340:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx42710z2 9.543 i_SIU/LMSIU_INST/ix42710z2956:C (r) + 0.497 cell: ADLIB:AND3A 10.040 i_SIU/LMSIU_INST/ix42710z2956:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx42710z1 10.289 i_SIU/LMSIU_INST/reg_q(9)_dup_371:D (r) 10.289 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.855 net: SIU_TXCLK_cb 13.403 i_SIU/LMSIU_INST/reg_q(9)_dup_371:CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.001 i_SIU/LMSIU_INST/reg_q(9)_dup_371:D 13.001 data required time Expanded Path 10 From: i_SIU/LMSIU_INST/reg_q(1)_dup_379:CLK To: i_SIU/LMSIU_INST/reg_q(10)_dup_370:D data required time 13.001 data arrival time - 10.264 slack 2.737 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.896 net: SIU_TXCLK_cb 4.353 i_SIU/LMSIU_INST/reg_q(1)_dup_379:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.903 i_SIU/LMSIU_INST/reg_q(1)_dup_379:Q (f) + 0.321 net: i_SIU/LMSIU_INST/nx32078z3 5.224 i_SIU/LMSIU_INST/NOT_ix32078z24339:A (f) + 0.384 cell: ADLIB:NAND2 5.608 i_SIU/LMSIU_INST/NOT_ix32078z24339:Y (r) + 0.303 net: i_SIU/LMSIU_INST/nx32078z2 5.911 i_SIU/LMSIU_INST/NOT_ix32078z50930:A (r) + 0.509 cell: ADLIB:NAND3A 6.420 i_SIU/LMSIU_INST/NOT_ix32078z50930:Y (r) + 0.817 net: i_SIU/LMSIU_INST/nx32078z1 7.237 i_SIU/LMSIU_INST/NOT_a(0):A (r) + 0.347 cell: ADLIB:NAND3C 7.584 i_SIU/LMSIU_INST/NOT_a(0):Y (r) + 0.980 net: i_SIU/LMSIU_INST/NOT_a_0_ 8.564 i_SIU/LMSIU_INST/ix39991z8206:A (r) + 0.705 cell: ADLIB:AX1B 9.269 i_SIU/LMSIU_INST/ix39991z8206:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx39991z2 9.518 i_SIU/LMSIU_INST/ix39991z2956:C (r) + 0.497 cell: ADLIB:AND3A 10.015 i_SIU/LMSIU_INST/ix39991z2956:Y (r) + 0.249 net: i_SIU/LMSIU_INST/nx39991z1 10.264 i_SIU/LMSIU_INST/reg_q(10)_dup_370:D (r) 10.264 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.855 net: SIU_TXCLK_cb 13.403 i_SIU/LMSIU_INST/reg_q(10)_dup_370:CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 13.001 i_SIU/LMSIU_INST/reg_q(10)_dup_370:D 13.001 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: RST_n To: reg_q(11):E Delay (ns): 10.361 Slack (ns): Arrival (ns): 10.361 Required (ns): Setup (ns): 0.325 External Setup (ns): 6.418 Path 2 From: RST_n To: reg_q(12):E Delay (ns): 10.357 Slack (ns): Arrival (ns): 10.357 Required (ns): Setup (ns): 0.325 External Setup (ns): 6.415 Path 3 From: RST_n To: reg_q(8):E Delay (ns): 10.298 Slack (ns): Arrival (ns): 10.298 Required (ns): Setup (ns): 0.325 External Setup (ns): 6.346 Path 4 From: RST_n To: reg_q(5):D Delay (ns): 10.148 Slack (ns): Arrival (ns): 10.148 Required (ns): Setup (ns): 0.402 External Setup (ns): 6.273 Path 5 From: RST_n To: reg_q(3):E Delay (ns): 10.050 Slack (ns): Arrival (ns): 10.050 Required (ns): Setup (ns): 0.325 External Setup (ns): 6.095 Path 6 From: RST_n To: reg_q(2):D Delay (ns): 9.952 Slack (ns): Arrival (ns): 9.952 Required (ns): Setup (ns): 0.402 External Setup (ns): 6.074 Path 7 From: RST_n To: reg_q(13):E Delay (ns): 10.009 Slack (ns): Arrival (ns): 10.009 Required (ns): Setup (ns): 0.325 External Setup (ns): 6.072 Path 8 From: RST_n To: reg_q(21):E Delay (ns): 9.913 Slack (ns): Arrival (ns): 9.913 Required (ns): Setup (ns): 0.325 External Setup (ns): 5.963 Path 9 From: RST_n To: reg_q(22):E Delay (ns): 9.913 Slack (ns): Arrival (ns): 9.913 Required (ns): Setup (ns): 0.325 External Setup (ns): 5.963 Path 10 From: RST_n To: reg_q(14):E Delay (ns): 9.813 Slack (ns): Arrival (ns): 9.813 Required (ns): Setup (ns): 0.325 External Setup (ns): 5.876 Expanded Path 1 From: RST_n To: reg_q(11):E data required time N/C data arrival time - 10.361 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 3.041 net: nx21420z1 9.557 ix18093z40560:C (r) + 0.572 cell: ADLIB:AO1E 10.129 ix18093z40560:Y (f) + 0.232 net: nx18093z2 10.361 reg_q(11):E (f) 10.361 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.811 net: SIU_TXCLK_cb N/C reg_q(11):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(11):E Expanded Path 2 From: RST_n To: reg_q(12):E data required time N/C data arrival time - 10.357 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 3.039 net: nx21420z1 9.555 ix19090z40560:C (r) + 0.572 cell: ADLIB:AO1E 10.127 ix19090z40560:Y (f) + 0.230 net: nx19090z2 10.357 reg_q(12):E (f) 10.357 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.810 net: SIU_TXCLK_cb N/C reg_q(12):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(12):E Expanded Path 3 From: RST_n To: reg_q(8):E data required time N/C data arrival time - 10.298 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 2.493 net: nx21420z1 9.009 ix59247z40560:C (r) + 0.572 cell: ADLIB:AO1E 9.581 ix59247z40560:Y (f) + 0.717 net: nx59247z2 10.298 reg_q(8):E (f) 10.298 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.820 net: SIU_TXCLK_cb N/C reg_q(8):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(8):E Expanded Path 4 From: RST_n To: reg_q(5):D data required time N/C data arrival time - 10.148 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 8.160 net: RST_n_i 9.361 ix56256z2956:B (r) + 0.535 cell: ADLIB:AND3A 9.896 ix56256z2956:Y (r) + 0.252 net: nx56256z1 10.148 reg_q(5):D (r) 10.148 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.820 net: SIU_TXCLK_cb N/C reg_q(5):CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 N/C reg_q(5):D Expanded Path 5 From: RST_n To: reg_q(3):E data required time N/C data arrival time - 10.050 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 2.732 net: nx21420z1 9.248 ix54262z40558:C (r) + 0.572 cell: ADLIB:AO1C 9.820 ix54262z40558:Y (f) + 0.230 net: nx54262z2 10.050 reg_q(3):E (f) 10.050 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.823 net: SIU_TXCLK_cb N/C reg_q(3):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(3):E Expanded Path 6 From: RST_n To: reg_q(2):D data required time N/C data arrival time - 9.952 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 7.967 net: RST_n_i 9.168 ix53265z2956:B (r) + 0.535 cell: ADLIB:AND3A 9.703 ix53265z2956:Y (r) + 0.249 net: nx53265z1 9.952 reg_q(2):D (r) 9.952 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.823 net: SIU_TXCLK_cb N/C reg_q(2):CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 N/C reg_q(2):D Expanded Path 7 From: RST_n To: reg_q(13):E data required time N/C data arrival time - 10.009 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 2.691 net: nx21420z1 9.207 ix20087z40560:C (r) + 0.572 cell: ADLIB:AO1E 9.779 ix20087z40560:Y (f) + 0.230 net: nx20087z2 10.009 reg_q(13):E (f) 10.009 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.805 net: SIU_TXCLK_cb N/C reg_q(13):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(13):E Expanded Path 8 From: RST_n To: reg_q(21):E data required time N/C data arrival time - 9.913 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 2.595 net: nx21420z1 9.111 ix29062z40560:C (r) + 0.572 cell: ADLIB:AO1E 9.683 ix29062z40560:Y (f) + 0.230 net: nx29062z2 9.913 reg_q(21):E (f) 9.913 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.818 net: SIU_TXCLK_cb N/C reg_q(21):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(21):E Expanded Path 9 From: RST_n To: reg_q(22):E data required time N/C data arrival time - 9.913 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 2.595 net: nx21420z1 9.111 ix30059z40560:C (r) + 0.572 cell: ADLIB:AO1E 9.683 ix30059z40560:Y (f) + 0.230 net: nx30059z2 9.913 reg_q(22):E (f) 9.913 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.818 net: SIU_TXCLK_cb N/C reg_q(22):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(22):E Expanded Path 10 From: RST_n To: reg_q(14):E data required time N/C data arrival time - 9.813 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 5.011 net: RST_n_i 6.212 NOT_ix21420z48514:A (r) + 0.304 cell: ADLIB:AND2 6.516 NOT_ix21420z48514:Y (r) + 2.495 net: nx21420z1 9.011 ix21084z40560:C (r) + 0.572 cell: ADLIB:AO1E 9.583 ix21084z40560:Y (f) + 0.230 net: nx21084z2 9.813 reg_q(14):E (f) 9.813 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.805 net: SIU_TXCLK_cb N/C reg_q(14):CLK (r) - 0.325 Library setup time: ADLIB:DFN1E1 N/C reg_q(14):E END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_SIU/LMSIU_INST/reg_sd_prbsen:CLK To: SIU_PRBSEN Delay (ns): 10.031 Slack (ns): Arrival (ns): 14.389 Required (ns): Clock to Out (ns): 14.389 Path 2 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SIU_ENABLE Delay (ns): 9.978 Slack (ns): Arrival (ns): 14.332 Required (ns): Clock to Out (ns): 14.332 Path 3 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SFP_TX_DIS Delay (ns): 8.709 Slack (ns): Arrival (ns): 13.063 Required (ns): Clock to Out (ns): 13.063 Path 4 From: i_SIU/INST_PMIF/reg_pm_ncs:CLK To: SFPP_SCSn Delay (ns): 8.541 Slack (ns): Arrival (ns): 12.887 Required (ns): Clock to Out (ns): 12.887 Path 5 From: reg_q(26):CLK To: LED_SIU(1) Delay (ns): 8.419 Slack (ns): Arrival (ns): 12.694 Required (ns): Clock to Out (ns): 12.694 Path 6 From: i_SIU/INST_PMIF/reg_pm_clk:CLK To: SFPP_SCLK Delay (ns): 8.166 Slack (ns): Arrival (ns): 12.518 Required (ns): Clock to Out (ns): 12.518 Path 7 From: reg_q(25):CLK To: LED_SIU(2) Delay (ns): 8.094 Slack (ns): Arrival (ns): 12.365 Required (ns): Clock to Out (ns): 12.365 Path 8 From: addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(13) Delay (ns): 3.007 Slack (ns): Arrival (ns): 7.450 Required (ns): Clock to Out (ns): 7.450 Path 9 From: addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(14) Delay (ns): 3.007 Slack (ns): Arrival (ns): 7.450 Required (ns): Clock to Out (ns): 7.450 Path 10 From: addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(15) Delay (ns): 3.007 Slack (ns): Arrival (ns): 7.450 Required (ns): Clock to Out (ns): 7.450 Expanded Path 1 From: i_SIU/LMSIU_INST/reg_sd_prbsen:CLK To: SIU_PRBSEN data required time N/C data arrival time - 14.389 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.901 net: SIU_TXCLK_cb 4.358 i_SIU/LMSIU_INST/reg_sd_prbsen:CLK (r) + 0.550 cell: ADLIB:DFN1C0 4.908 i_SIU/LMSIU_INST/reg_sd_prbsen:Q (f) + 3.931 net: SIU_PRBSEN_i 8.839 obuf_SIU_PRBSEN_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 9.331 obuf_SIU_PRBSEN_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SIU_PRBSEN_U1/U0/NET1 9.331 obuf_SIU_PRBSEN_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 14.389 obuf_SIU_PRBSEN_U1/U0/U0:PAD (f) + 0.000 net: SIU_PRBSEN 14.389 SIU_PRBSEN (f) 14.389 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_PRBSEN (f) Expanded Path 2 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SIU_ENABLE data required time N/C data arrival time - 14.332 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.897 net: SIU_TXCLK_cb 4.354 i_SIU/LMSIU_INST/reg_ot_lon:CLK (r) + 0.550 cell: ADLIB:DFN1P0 4.904 i_SIU/LMSIU_INST/reg_ot_lon:Q (f) + 3.935 net: SIU_ENABLE_i 8.839 obuf_SIU_ENABLE_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 9.274 obuf_SIU_ENABLE_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SIU_ENABLE_U1/U0/NET1 9.274 obuf_SIU_ENABLE_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 14.332 obuf_SIU_ENABLE_U1/U0/U0:PAD (f) + 0.000 net: SIU_ENABLE 14.332 SIU_ENABLE (f) 14.332 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_ENABLE (f) Expanded Path 3 From: i_SIU/LMSIU_INST/reg_ot_lon:CLK To: SFP_TX_DIS data required time N/C data arrival time - 13.063 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.897 net: SIU_TXCLK_cb 4.354 i_SIU/LMSIU_INST/reg_ot_lon:CLK (r) + 0.434 cell: ADLIB:DFN1P0 4.788 i_SIU/LMSIU_INST/reg_ot_lon:Q (r) + 2.058 net: SIU_ENABLE_i 6.846 i_SIU/ot_td:A (r) + 0.348 cell: ADLIB:INV 7.194 i_SIU/ot_td:Y (f) + 0.878 net: SFP_TX_DIS_i 8.072 obuf_SFP_TX_DIS_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 8.564 obuf_SFP_TX_DIS_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SFP_TX_DIS_U1/U0/NET1 8.564 obuf_SFP_TX_DIS_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 13.063 obuf_SFP_TX_DIS_U1/U0/U0:PAD (f) + 0.000 net: SFP_TX_DIS 13.063 SFP_TX_DIS (f) 13.063 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SFP_TX_DIS (f) Expanded Path 4 From: i_SIU/INST_PMIF/reg_pm_ncs:CLK To: SFPP_SCSn data required time N/C data arrival time - 12.887 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.889 net: SIU_TXCLK_cb 4.346 i_SIU/INST_PMIF/reg_pm_ncs:CLK (r) + 0.550 cell: ADLIB:DFN1P0 4.896 i_SIU/INST_PMIF/reg_pm_ncs:Q (f) + 3.057 net: SFPP_SCSn_i 7.953 obuf_SFPP_SCSn_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 8.388 obuf_SFPP_SCSn_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SFPP_SCSn_U1/U0/NET1 8.388 obuf_SFPP_SCSn_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 12.887 obuf_SFPP_SCSn_U1/U0/U0:PAD (f) + 0.000 net: SFPP_SCSn 12.887 SFPP_SCSn (f) 12.887 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SFPP_SCSn (f) Expanded Path 5 From: reg_q(26):CLK To: LED_SIU(1) data required time N/C data arrival time - 12.694 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.818 net: SIU_TXCLK_cb 4.275 reg_q(26):CLK (r) + 0.550 cell: ADLIB:DFN1E1 4.825 reg_q(26):Q (f) + 2.376 net: led_cnt_26_ 7.201 genblk4[1].leds_cnt_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 7.636 genblk4[1].leds_cnt_U1/U0/U1:DOUT (f) + 0.000 net: genblk4[1]_leds_cnt_U1/U0/NET1 7.636 genblk4[1].leds_cnt_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 12.694 genblk4[1].leds_cnt_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_1_ 12.694 LED_SIU(1) (f) 12.694 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C LED_SIU(1) (f) Expanded Path 6 From: i_SIU/INST_PMIF/reg_pm_clk:CLK To: SFPP_SCLK data required time N/C data arrival time - 12.518 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.895 net: SIU_TXCLK_cb 4.352 i_SIU/INST_PMIF/reg_pm_clk:CLK (r) + 0.550 cell: ADLIB:DFN1P0 4.902 i_SIU/INST_PMIF/reg_pm_clk:Q (f) + 2.682 net: SFPP_SCLK_i 7.584 obuf_SFPP_SCLK_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 8.019 obuf_SFPP_SCLK_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SFPP_SCLK_U1/U0/NET1 8.019 obuf_SFPP_SCLK_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 12.518 obuf_SFPP_SCLK_U1/U0/U0:PAD (f) + 0.000 net: SFPP_SCLK 12.518 SFPP_SCLK (f) 12.518 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SFPP_SCLK (f) Expanded Path 7 From: reg_q(25):CLK To: LED_SIU(2) data required time N/C data arrival time - 12.365 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.814 net: SIU_TXCLK_cb 4.271 reg_q(25):CLK (r) + 0.550 cell: ADLIB:DFN1E1 4.821 reg_q(25):Q (f) + 2.051 net: led_cnt_25_ 6.872 genblk4[2].leds_cnt_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 7.307 genblk4[2].leds_cnt_U1/U0/U1:DOUT (f) + 0.000 net: genblk4[2]_leds_cnt_U1/U0/NET1 7.307 genblk4[2].leds_cnt_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 12.365 genblk4[2].leds_cnt_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_2_ 12.365 LED_SIU(2) (f) 12.365 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C LED_SIU(2) (f) Expanded Path 8 From: addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(13) data required time N/C data arrival time - 7.450 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.986 net: SIU_TXCLK_cb 4.443 addds[13].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.572 cell: ADLIB:IOTRI_ORC_EB 5.015 addds[13].obuf_SIU_TXD_U1/U0/U1:DOUT (f) + 0.000 net: addds[13]_obuf_SIU_TXD_U1/U0/NET1 5.015 addds[13].obuf_SIU_TXD_U1/U0/U0:D (f) + 2.435 cell: ADLIB:IOPAD_TRI 7.450 addds[13].obuf_SIU_TXD_U1/U0/U0:PAD (f) + 0.000 net: SIU_TXD_13_ 7.450 SIU_TXD(13) (f) 7.450 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(13) (f) Expanded Path 9 From: addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(14) data required time N/C data arrival time - 7.450 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.986 net: SIU_TXCLK_cb 4.443 addds[14].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.572 cell: ADLIB:IOTRI_ORC_EB 5.015 addds[14].obuf_SIU_TXD_U1/U0/U1:DOUT (f) + 0.000 net: addds[14]_obuf_SIU_TXD_U1/U0/NET1 5.015 addds[14].obuf_SIU_TXD_U1/U0/U0:D (f) + 2.435 cell: ADLIB:IOPAD_TRI 7.450 addds[14].obuf_SIU_TXD_U1/U0/U0:PAD (f) + 0.000 net: SIU_TXD_14_ 7.450 SIU_TXD(14) (f) 7.450 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(14) (f) Expanded Path 10 From: addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK To: SIU_TXD(15) data required time N/C data arrival time - 7.450 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.986 net: SIU_TXCLK_cb 4.443 addds[15].obuf_SIU_TXD_U1/U0/U1:OCLK (r) + 0.572 cell: ADLIB:IOTRI_ORC_EB 5.015 addds[15].obuf_SIU_TXD_U1/U0/U1:DOUT (f) + 0.000 net: addds[15]_obuf_SIU_TXD_U1/U0/NET1 5.015 addds[15].obuf_SIU_TXD_U1/U0/U0:D (f) + 2.435 cell: ADLIB:IOPAD_TRI 7.450 addds[15].obuf_SIU_TXD_U1/U0/U0:PAD (f) + 0.000 net: SIU_TXD_15_ 7.450 SIU_TXD(15) (f) 7.450 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) N/C SIU_TXD(15) (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_s_crc_in(0):CLR Delay (ns): 3.948 Slack (ns): 4.789 Arrival (ns): 8.361 Required (ns): 13.150 Recovery (ns): 0.222 Minimum Period (ns): 4.302 Skew (ns): 0.132 Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_clkdiv_cnt(0):PRE Delay (ns): 3.847 Slack (ns): 4.873 Arrival (ns): 8.260 Required (ns): 13.133 Recovery (ns): 0.222 Minimum Period (ns): 4.218 Skew (ns): 0.149 Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_s_crc_in(14):CLR Delay (ns): 3.817 Slack (ns): 4.945 Arrival (ns): 8.230 Required (ns): 13.175 Recovery (ns): 0.222 Minimum Period (ns): 4.146 Skew (ns): 0.107 Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst:RESET Delay (ns): 2.695 Slack (ns): 4.951 Arrival (ns): 7.108 Required (ns): 12.059 Recovery (ns): 1.460 Minimum Period (ns): 4.140 Skew (ns): -0.015 Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RESET Delay (ns): 2.698 Slack (ns): 4.975 Arrival (ns): 7.111 Required (ns): 12.086 Recovery (ns): 1.460 Minimum Period (ns): 4.116 Skew (ns): -0.042 Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_clkdiv_cnt(4):CLR Delay (ns): 3.742 Slack (ns): 4.995 Arrival (ns): 8.155 Required (ns): 13.150 Recovery (ns): 0.222 Minimum Period (ns): 4.096 Skew (ns): 0.132 Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(8):CLR Delay (ns): 3.751 Slack (ns): 4.999 Arrival (ns): 8.164 Required (ns): 13.163 Recovery (ns): 0.222 Minimum Period (ns): 4.092 Skew (ns): 0.119 Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_clkdiv_cnt(5):CLR Delay (ns): 3.714 Slack (ns): 5.023 Arrival (ns): 8.127 Required (ns): 13.150 Recovery (ns): 0.222 Minimum Period (ns): 4.068 Skew (ns): 0.132 Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts2(15):CLR Delay (ns): 3.666 Slack (ns): 5.167 Arrival (ns): 8.079 Required (ns): 13.246 Recovery (ns): 0.222 Minimum Period (ns): 3.924 Skew (ns): 0.036 Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(2):CLR Delay (ns): 3.624 Slack (ns): 5.178 Arrival (ns): 8.037 Required (ns): 13.215 Recovery (ns): 0.222 Minimum Period (ns): 3.913 Skew (ns): 0.067 Expanded Path 1 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_s_crc_in(0):CLR data required time 13.150 data arrival time - 8.361 slack 4.789 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.514 net: i_SIU/s_arstn 8.361 i_SIU/FRAMING_INST/reg_s_crc_in(0):CLR (r) 8.361 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.824 net: SIU_TXCLK_cb 13.372 i_SIU/FRAMING_INST/reg_s_crc_in(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.150 i_SIU/FRAMING_INST/reg_s_crc_in(0):CLR 13.150 data required time Expanded Path 2 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_clkdiv_cnt(0):PRE data required time 13.133 data arrival time - 8.260 slack 4.873 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.413 net: i_SIU/s_arstn 8.260 i_SIU/INST_PMIF/reg_clkdiv_cnt(0):PRE (r) 8.260 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.807 net: SIU_TXCLK_cb 13.355 i_SIU/INST_PMIF/reg_clkdiv_cnt(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1P0 13.133 i_SIU/INST_PMIF/reg_clkdiv_cnt(0):PRE 13.133 data required time Expanded Path 3 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_s_crc_in(14):CLR data required time 13.175 data arrival time - 8.230 slack 4.945 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.383 net: i_SIU/s_arstn 8.230 i_SIU/FRAMING_INST/reg_s_crc_in(14):CLR (r) 8.230 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.849 net: SIU_TXCLK_cb 13.397 i_SIU/FRAMING_INST/reg_s_crc_in(14):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.175 i_SIU/FRAMING_INST/reg_s_crc_in(14):CLR 13.175 data required time Expanded Path 4 From: i_SIU/reg_s_arstn:CLK To: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst:RESET data required time 12.059 data arrival time - 7.108 slack 4.951 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 2.261 net: i_SIU/s_arstn 7.108 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst:RESET (r) 7.108 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.971 net: SIU_TXCLK_cb 13.519 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst:RCLK (r) - 1.460 Library recovery time: ADLIB:FIFO4K18 12.059 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_0_inst:RESET 12.059 data required time Expanded Path 5 From: i_SIU/reg_s_arstn:CLK To: i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RESET data required time 12.086 data arrival time - 7.111 slack 4.975 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 2.264 net: i_SIU/s_arstn 7.111 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RESET (r) 7.111 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.998 net: SIU_TXCLK_cb 13.546 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RCLK (r) - 1.460 Library recovery time: ADLIB:FIFO4K18 12.086 i_SIU/TXDF_INST_TXDF_CORE_INST_FIFOBLOCK_1_inst:RESET 12.086 data required time Expanded Path 6 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_clkdiv_cnt(4):CLR data required time 13.150 data arrival time - 8.155 slack 4.995 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.308 net: i_SIU/s_arstn 8.155 i_SIU/INST_PMIF/reg_clkdiv_cnt(4):CLR (r) 8.155 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.824 net: SIU_TXCLK_cb 13.372 i_SIU/INST_PMIF/reg_clkdiv_cnt(4):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.150 i_SIU/INST_PMIF/reg_clkdiv_cnt(4):CLR 13.150 data required time Expanded Path 7 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(8):CLR data required time 13.163 data arrival time - 8.164 slack 4.999 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.317 net: i_SIU/s_arstn 8.164 i_SIU/INST_PMIF/reg_pm_value_int(8):CLR (r) 8.164 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.837 net: SIU_TXCLK_cb 13.385 i_SIU/INST_PMIF/reg_pm_value_int(8):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.163 i_SIU/INST_PMIF/reg_pm_value_int(8):CLR 13.163 data required time Expanded Path 8 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_clkdiv_cnt(5):CLR data required time 13.150 data arrival time - 8.127 slack 5.023 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.280 net: i_SIU/s_arstn 8.127 i_SIU/INST_PMIF/reg_clkdiv_cnt(5):CLR (r) 8.127 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.824 net: SIU_TXCLK_cb 13.372 i_SIU/INST_PMIF/reg_clkdiv_cnt(5):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.150 i_SIU/INST_PMIF/reg_clkdiv_cnt(5):CLR 13.150 data required time Expanded Path 9 From: i_SIU/reg_s_arstn:CLK To: i_SIU/FRAMING_INST/reg_txd_sts2(15):CLR data required time 13.246 data arrival time - 8.079 slack 5.167 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.232 net: i_SIU/s_arstn 8.079 i_SIU/FRAMING_INST/reg_txd_sts2(15):CLR (r) 8.079 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.920 net: SIU_TXCLK_cb 13.468 i_SIU/FRAMING_INST/reg_txd_sts2(15):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.246 i_SIU/FRAMING_INST/reg_txd_sts2(15):CLR 13.246 data required time Expanded Path 10 From: i_SIU/reg_s_arstn:CLK To: i_SIU/INST_PMIF/reg_pm_value_int(2):CLR data required time 13.215 data arrival time - 8.037 slack 5.178 ________________________________________________________ Data arrival time calculation 0.000 SIU_TXCLK + 0.000 Clock source 0.000 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 0.000 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 1.129 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 2.899 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 3.457 cbuf_SIU_TXCLK:Y (r) + 0.956 net: SIU_TXCLK_cb 4.413 i_SIU/reg_s_arstn:CLK (r) + 0.434 cell: ADLIB:DFN1C1 4.847 i_SIU/reg_s_arstn:Q (r) + 3.190 net: i_SIU/s_arstn 8.037 i_SIU/INST_PMIF/reg_pm_value_int(2):CLR (r) 8.037 data arrival time ________________________________________________________ Data required time calculation 9.091 SIU_TXCLK + 0.000 Clock source 9.091 SIU_TXCLK (r) + 0.000 net: SIU_TXCLK 9.091 ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 10.220 ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 10.220 ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 10.252 ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i 11.990 cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT 12.548 cbuf_SIU_TXCLK:Y (r) + 0.889 net: SIU_TXCLK_cb 13.437 i_SIU/INST_PMIF/reg_pm_value_int(2):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C0 13.215 i_SIU/INST_PMIF/reg_pm_value_int(2):CLR 13.215 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: addds[2].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 13.094 Slack (ns): Arrival (ns): 13.094 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.051 Path 2 From: PUSHB To: addds[1].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 13.094 Slack (ns): Arrival (ns): 13.094 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.046 Path 3 From: PUSHB To: addds[0].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 13.062 Slack (ns): Arrival (ns): 13.062 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 9.014 Path 4 From: PUSHB To: addds[3].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 13.041 Slack (ns): Arrival (ns): 13.041 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.998 Path 5 From: PUSHB To: addds[4].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 13.022 Slack (ns): Arrival (ns): 13.022 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.974 Path 6 From: PUSHB To: addds[5].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 13.022 Slack (ns): Arrival (ns): 13.022 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.974 Path 7 From: RST_n To: addds[2].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 12.900 Slack (ns): Arrival (ns): 12.900 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.857 Path 8 From: RST_n To: addds[1].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 12.900 Slack (ns): Arrival (ns): 12.900 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.852 Path 9 From: RST_n To: addds[0].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 12.868 Slack (ns): Arrival (ns): 12.868 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.820 Path 10 From: RST_n To: addds[3].obuf_SIU_TXD_U1/U0/U1:CLR Delay (ns): 12.847 Slack (ns): Arrival (ns): 12.847 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.804 Expanded Path 1 From: PUSHB To: addds[2].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 13.094 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 7.541 net: not_rst_n 13.094 addds[2].obuf_SIU_TXD_U1/U0/U1:CLR (f) 13.094 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.808 net: SIU_TXCLK_cb N/C addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[2].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 2 From: PUSHB To: addds[1].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 13.094 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 7.541 net: not_rst_n 13.094 addds[1].obuf_SIU_TXD_U1/U0/U1:CLR (f) 13.094 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.813 net: SIU_TXCLK_cb N/C addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[1].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 3 From: PUSHB To: addds[0].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 13.062 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 7.509 net: not_rst_n 13.062 addds[0].obuf_SIU_TXD_U1/U0/U1:CLR (f) 13.062 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.813 net: SIU_TXCLK_cb N/C addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[0].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 4 From: PUSHB To: addds[3].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 13.041 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 7.488 net: not_rst_n 13.041 addds[3].obuf_SIU_TXD_U1/U0/U1:CLR (f) 13.041 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.808 net: SIU_TXCLK_cb N/C addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[3].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 5 From: PUSHB To: addds[4].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 13.022 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 7.469 net: not_rst_n 13.022 addds[4].obuf_SIU_TXD_U1/U0/U1:CLR (f) 13.022 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.813 net: SIU_TXCLK_cb N/C addds[4].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[4].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 6 From: PUSHB To: addds[5].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 13.022 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 7.469 net: not_rst_n 13.022 addds[5].obuf_SIU_TXD_U1/U0/U1:CLR (f) 13.022 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.813 net: SIU_TXCLK_cb N/C addds[5].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[5].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 7 From: RST_n To: addds[2].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 12.900 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 7.541 net: not_rst_n 12.900 addds[2].obuf_SIU_TXD_U1/U0/U1:CLR (f) 12.900 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.808 net: SIU_TXCLK_cb N/C addds[2].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[2].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 8 From: RST_n To: addds[1].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 12.900 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 7.541 net: not_rst_n 12.900 addds[1].obuf_SIU_TXD_U1/U0/U1:CLR (f) 12.900 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.813 net: SIU_TXCLK_cb N/C addds[1].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[1].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 9 From: RST_n To: addds[0].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 12.868 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 7.509 net: not_rst_n 12.868 addds[0].obuf_SIU_TXD_U1/U0/U1:CLR (f) 12.868 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.813 net: SIU_TXCLK_cb N/C addds[0].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[0].obuf_SIU_TXD_U1/U0/U1:CLR Expanded Path 10 From: RST_n To: addds[3].obuf_SIU_TXD_U1/U0/U1:CLR data required time N/C data arrival time - 12.847 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 7.488 net: not_rst_n 12.847 addds[3].obuf_SIU_TXD_U1/U0/U1:CLR (f) 12.847 data arrival time ________________________________________________________ Data required time calculation N/C SIU_TXCLK + 0.000 Clock source N/C SIU_TXCLK (r) + 0.000 net: SIU_TXCLK N/C ibuf_SIU_TXCLK_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN N/C ibuf_SIU_TXCLK_ib/U0/U0:Y (r) + 0.000 net: ibuf_SIU_TXCLK_ib/U0/NET1 N/C ibuf_SIU_TXCLK_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB N/C ibuf_SIU_TXCLK_ib/U0/U1:Y (r) + 1.738 net: SIU_TXCLK_i N/C cbuf_SIU_TXCLK:A (r) + 0.558 cell: ADLIB:CLKINT N/C cbuf_SIU_TXCLK:Y (r) + 0.808 net: SIU_TXCLK_cb N/C addds[3].obuf_SIU_TXD_U1/U0/U1:OCLK (r) - 0.222 Library recovery time: ADLIB:IOTRI_ORC_EB N/C addds[3].obuf_SIU_TXD_U1/U0/U1:CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_SIU/reg_tx_clk_2:Q SET Register to Register Path 1 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D Delay (ns): 8.123 Slack (ns): 9.639 Arrival (ns): 12.957 Required (ns): 22.596 Setup (ns): 0.402 Minimum Period (ns): 8.543 Path 2 From: i_SIU/I2CIF_INST/reg_bit_count(1):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D Delay (ns): 7.388 Slack (ns): 10.375 Arrival (ns): 12.195 Required (ns): 22.570 Setup (ns): 0.428 Minimum Period (ns): 7.807 Path 3 From: i_SIU/I2CIF_INST/reg_bit_count(2):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D Delay (ns): 7.134 Slack (ns): 10.616 Arrival (ns): 11.954 Required (ns): 22.570 Setup (ns): 0.428 Minimum Period (ns): 7.566 Path 4 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(9):D Delay (ns): 6.943 Slack (ns): 10.826 Arrival (ns): 11.788 Required (ns): 22.614 Setup (ns): 0.402 Minimum Period (ns): 7.356 Path 5 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(18):D Delay (ns): 6.857 Slack (ns): 10.878 Arrival (ns): 11.702 Required (ns): 22.580 Setup (ns): 0.428 Minimum Period (ns): 7.304 Path 6 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(11):D Delay (ns): 6.845 Slack (ns): 10.904 Arrival (ns): 11.690 Required (ns): 22.594 Setup (ns): 0.428 Minimum Period (ns): 7.278 Path 7 From: i_SIU/reg_blink_timer(2):CLK To: i_SIU/reg_blink_timer(9):D Delay (ns): 6.856 Slack (ns): 10.913 Arrival (ns): 11.701 Required (ns): 22.614 Setup (ns): 0.402 Minimum Period (ns): 7.269 Path 8 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(20):D Delay (ns): 6.802 Slack (ns): 10.933 Arrival (ns): 11.647 Required (ns): 22.580 Setup (ns): 0.428 Minimum Period (ns): 7.249 Path 9 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(22):D Delay (ns): 6.797 Slack (ns): 10.938 Arrival (ns): 11.642 Required (ns): 22.580 Setup (ns): 0.428 Minimum Period (ns): 7.244 Path 10 From: i_SIU/reg_blink_timer(0):CLK To: i_SIU/reg_blink_timer(9):D Delay (ns): 6.811 Slack (ns): 10.958 Arrival (ns): 11.656 Required (ns): 22.614 Setup (ns): 0.402 Minimum Period (ns): 7.224 Expanded Path 1 From: i_SIU/I2CIF_INST/reg_bit_count(0):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D data required time 22.596 data arrival time - 12.957 slack 9.639 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.838 net: i_SIU/tx_clk_2b 4.834 i_SIU/I2CIF_INST/reg_bit_count(0):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.384 i_SIU/I2CIF_INST/reg_bit_count(0):Q (f) + 1.615 net: i_SIU/I2CIF_INST/bit_count_0_ 6.999 i_SIU/I2CIF_INST/ix7293z14911:S (f) + 0.358 cell: ADLIB:MX2 7.357 i_SIU/I2CIF_INST/ix7293z14911:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx7293z16 7.606 i_SIU/I2CIF_INST/ix7293z14909:B (r) + 0.437 cell: ADLIB:MX2 8.043 i_SIU/I2CIF_INST/ix7293z14909:Y (r) + 1.346 net: i_SIU/I2CIF_INST/nx7293z14 9.389 i_SIU/I2CIF_INST/ix7293z50942:C (r) + 0.466 cell: ADLIB:NAND3A 9.855 i_SIU/I2CIF_INST/ix7293z50942:Y (f) + 0.230 net: i_SIU/I2CIF_INST/nx7293z13 10.085 i_SIU/I2CIF_INST/ix7293z50934:B (f) + 0.269 cell: ADLIB:NAND3A 10.354 i_SIU/I2CIF_INST/ix7293z50934:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx7293z5 10.603 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:B (r) + 0.453 cell: ADLIB:NAND3B 11.056 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:Y (r) + 1.155 net: i_SIU/I2CIF_INST/s_sda_out_3n41ss1 12.211 i_SIU/I2CIF_INST/ix33626z14896:A (r) + 0.497 cell: ADLIB:MX2 12.708 i_SIU/I2CIF_INST/ix33626z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx33626z1 12.957 i_SIU/I2CIF_INST/reg_s_sda_out:D (r) 12.957 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.820 net: i_SIU/tx_clk_2b 22.998 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 22.596 i_SIU/I2CIF_INST/reg_s_sda_out:D 22.596 data required time Expanded Path 2 From: i_SIU/I2CIF_INST/reg_bit_count(1):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D data required time 22.570 data arrival time - 12.195 slack 10.375 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.811 net: i_SIU/tx_clk_2b 4.807 i_SIU/I2CIF_INST/reg_bit_count(1):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.357 i_SIU/I2CIF_INST/reg_bit_count(1):Q (f) + 0.579 net: i_SIU/I2CIF_INST/bit_count_1_ 5.936 i_SIU/I2CIF_INST/ix9993z24342:B (f) + 0.469 cell: ADLIB:NAND2 6.405 i_SIU/I2CIF_INST/ix9993z24342:Y (r) + 1.250 net: i_SIU/I2CIF_INST/nx9993z4 7.655 i_SIU/I2CIF_INST/ix7293z50938:A (r) + 0.509 cell: ADLIB:NAND3A 8.164 i_SIU/I2CIF_INST/ix7293z50938:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx7293z9 8.413 i_SIU/I2CIF_INST/ix7293z24342:B (r) + 0.535 cell: ADLIB:NAND3 8.948 i_SIU/I2CIF_INST/ix7293z24342:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx7293z6 9.187 i_SIU/I2CIF_INST/ix7293z50934:A (f) + 0.497 cell: ADLIB:NAND3A 9.684 i_SIU/I2CIF_INST/ix7293z50934:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z5 9.925 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:B (f) + 0.466 cell: ADLIB:NAND3B 10.391 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:Y (f) + 1.103 net: i_SIU/I2CIF_INST/s_sda_out_3n41ss1 11.494 i_SIU/I2CIF_INST/ix33626z14896:A (f) + 0.462 cell: ADLIB:MX2 11.956 i_SIU/I2CIF_INST/ix33626z14896:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx33626z1 12.195 i_SIU/I2CIF_INST/reg_s_sda_out:D (f) 12.195 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.820 net: i_SIU/tx_clk_2b 22.998 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.570 i_SIU/I2CIF_INST/reg_s_sda_out:D 22.570 data required time Expanded Path 3 From: i_SIU/I2CIF_INST/reg_bit_count(2):CLK To: i_SIU/I2CIF_INST/reg_s_sda_out:D data required time 22.570 data arrival time - 11.954 slack 10.616 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b 4.820 i_SIU/I2CIF_INST/reg_bit_count(2):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.370 i_SIU/I2CIF_INST/reg_bit_count(2):Q (f) + 0.410 net: i_SIU/I2CIF_INST/bit_count_2_ 5.780 i_SIU/I2CIF_INST/ix9993z24342:A (f) + 0.384 cell: ADLIB:NAND2 6.164 i_SIU/I2CIF_INST/ix9993z24342:Y (r) + 1.250 net: i_SIU/I2CIF_INST/nx9993z4 7.414 i_SIU/I2CIF_INST/ix7293z50938:A (r) + 0.509 cell: ADLIB:NAND3A 7.923 i_SIU/I2CIF_INST/ix7293z50938:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx7293z9 8.172 i_SIU/I2CIF_INST/ix7293z24342:B (r) + 0.535 cell: ADLIB:NAND3 8.707 i_SIU/I2CIF_INST/ix7293z24342:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx7293z6 8.946 i_SIU/I2CIF_INST/ix7293z50934:A (f) + 0.497 cell: ADLIB:NAND3A 9.443 i_SIU/I2CIF_INST/ix7293z50934:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx7293z5 9.684 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:B (f) + 0.466 cell: ADLIB:NAND3B 10.150 i_SIU/I2CIF_INST/s_sda_out_3n41ss1:Y (f) + 1.103 net: i_SIU/I2CIF_INST/s_sda_out_3n41ss1 11.253 i_SIU/I2CIF_INST/ix33626z14896:A (f) + 0.462 cell: ADLIB:MX2 11.715 i_SIU/I2CIF_INST/ix33626z14896:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx33626z1 11.954 i_SIU/I2CIF_INST/reg_s_sda_out:D (f) 11.954 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.820 net: i_SIU/tx_clk_2b 22.998 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.570 i_SIU/I2CIF_INST/reg_s_sda_out:D 22.570 data required time Expanded Path 4 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(9):D data required time 22.614 data arrival time - 11.788 slack 10.826 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(1):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.395 i_SIU/reg_blink_timer(1):Q (f) + 0.365 net: i_SIU/blink_timer_1_ 5.760 i_SIU/modgen_dec_1052_ix49941z50935:B (f) + 0.534 cell: ADLIB:NAND3C 6.294 i_SIU/modgen_dec_1052_ix49941z50935:Y (f) + 1.075 net: i_SIU/nx49941z4 7.369 i_SIU/modgen_dec_1052_ix49941z50934:A (f) + 0.392 cell: ADLIB:NAND3C 7.761 i_SIU/modgen_dec_1052_ix49941z50934:Y (f) + 1.818 net: i_SIU/nx49941z3 9.579 i_SIU/modgen_dec_1052_ix58157z49936:A (f) + 0.401 cell: ADLIB:NAND2B 9.980 i_SIU/modgen_dec_1052_ix58157z49936:Y (f) + 0.321 net: i_SIU/nx58157z3 10.301 i_SIU/modgen_dec_1052_ix58157z50933:A (f) + 0.392 cell: ADLIB:NAND3C 10.693 i_SIU/modgen_dec_1052_ix58157z50933:Y (f) + 0.239 net: i_SIU/nx58157z2 10.932 i_SIU/ix58157z43526:B (f) + 0.615 cell: ADLIB:XO1A 11.547 i_SIU/ix58157z43526:Y (f) + 0.241 net: i_SIU/nx58157z1 11.788 i_SIU/reg_blink_timer(9):D (f) 11.788 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.838 net: i_SIU/tx_clk_2b 23.016 i_SIU/reg_blink_timer(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 22.614 i_SIU/reg_blink_timer(9):D 22.614 data required time Expanded Path 5 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(18):D data required time 22.580 data arrival time - 11.702 slack 10.878 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(1):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.395 i_SIU/reg_blink_timer(1):Q (f) + 0.365 net: i_SIU/blink_timer_1_ 5.760 i_SIU/modgen_dec_1052_ix49941z50935:B (f) + 0.534 cell: ADLIB:NAND3C 6.294 i_SIU/modgen_dec_1052_ix49941z50935:Y (f) + 1.075 net: i_SIU/nx49941z4 7.369 i_SIU/modgen_dec_1052_ix49941z50934:A (f) + 0.392 cell: ADLIB:NAND3C 7.761 i_SIU/modgen_dec_1052_ix49941z50934:Y (f) + 1.023 net: i_SIU/nx49941z3 8.784 i_SIU/modgen_dec_1052_ix49941z50933:A (f) + 0.392 cell: ADLIB:NAND3C 9.176 i_SIU/modgen_dec_1052_ix49941z50933:Y (f) + 1.056 net: i_SIU/nx49941z2 10.232 i_SIU/modgen_dec_1052_ix55925z49935:A (f) + 0.401 cell: ADLIB:NAND2B 10.633 i_SIU/modgen_dec_1052_ix55925z49935:Y (f) + 0.239 net: i_SIU/nx55925z2 10.872 i_SIU/ix55925z21034:A (f) + 0.591 cell: ADLIB:XA1C 11.463 i_SIU/ix55925z21034:Y (f) + 0.239 net: i_SIU/nx55925z1 11.702 i_SIU/reg_blink_timer(18):D (f) 11.702 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.830 net: i_SIU/tx_clk_2b 23.008 i_SIU/reg_blink_timer(18):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 22.580 i_SIU/reg_blink_timer(18):D 22.580 data required time Expanded Path 6 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(11):D data required time 22.594 data arrival time - 11.690 slack 10.904 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.279 i_SIU/reg_blink_timer(1):Q (r) + 0.390 net: i_SIU/blink_timer_1_ 5.669 i_SIU/modgen_dec_1052_ix49941z50935:B (r) + 0.479 cell: ADLIB:NAND3C 6.148 i_SIU/modgen_dec_1052_ix49941z50935:Y (r) + 1.178 net: i_SIU/nx49941z4 7.326 i_SIU/modgen_dec_1052_ix49941z50934:A (r) + 0.347 cell: ADLIB:NAND3C 7.673 i_SIU/modgen_dec_1052_ix49941z50934:Y (r) + 1.944 net: i_SIU/nx49941z3 9.617 i_SIU/modgen_dec_1052_ix58157z49936:A (r) + 0.348 cell: ADLIB:NAND2B 9.965 i_SIU/modgen_dec_1052_ix58157z49936:Y (r) + 0.345 net: i_SIU/nx58157z3 10.310 i_SIU/modgen_dec_1052_ix62904z50933:A (r) + 0.347 cell: ADLIB:NAND3C 10.657 i_SIU/modgen_dec_1052_ix62904z50933:Y (r) + 0.249 net: i_SIU/nx62904z2 10.906 i_SIU/ix62904z43526:A (r) + 0.535 cell: ADLIB:XO1A 11.441 i_SIU/ix62904z43526:Y (r) + 0.249 net: i_SIU/nx62904z1 11.690 i_SIU/reg_blink_timer(11):D (r) 11.690 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.844 net: i_SIU/tx_clk_2b 23.022 i_SIU/reg_blink_timer(11):CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.594 i_SIU/reg_blink_timer(11):D 22.594 data required time Expanded Path 7 From: i_SIU/reg_blink_timer(2):CLK To: i_SIU/reg_blink_timer(9):D data required time 22.614 data arrival time - 11.701 slack 10.913 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(2):CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.395 i_SIU/reg_blink_timer(2):Q (f) + 0.316 net: i_SIU/blink_timer_2_ 5.711 i_SIU/modgen_dec_1052_ix49941z50935:C (f) + 0.496 cell: ADLIB:NAND3C 6.207 i_SIU/modgen_dec_1052_ix49941z50935:Y (f) + 1.075 net: i_SIU/nx49941z4 7.282 i_SIU/modgen_dec_1052_ix49941z50934:A (f) + 0.392 cell: ADLIB:NAND3C 7.674 i_SIU/modgen_dec_1052_ix49941z50934:Y (f) + 1.818 net: i_SIU/nx49941z3 9.492 i_SIU/modgen_dec_1052_ix58157z49936:A (f) + 0.401 cell: ADLIB:NAND2B 9.893 i_SIU/modgen_dec_1052_ix58157z49936:Y (f) + 0.321 net: i_SIU/nx58157z3 10.214 i_SIU/modgen_dec_1052_ix58157z50933:A (f) + 0.392 cell: ADLIB:NAND3C 10.606 i_SIU/modgen_dec_1052_ix58157z50933:Y (f) + 0.239 net: i_SIU/nx58157z2 10.845 i_SIU/ix58157z43526:B (f) + 0.615 cell: ADLIB:XO1A 11.460 i_SIU/ix58157z43526:Y (f) + 0.241 net: i_SIU/nx58157z1 11.701 i_SIU/reg_blink_timer(9):D (f) 11.701 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.838 net: i_SIU/tx_clk_2b 23.016 i_SIU/reg_blink_timer(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 22.614 i_SIU/reg_blink_timer(9):D 22.614 data required time Expanded Path 8 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(20):D data required time 22.580 data arrival time - 11.647 slack 10.933 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.279 i_SIU/reg_blink_timer(1):Q (r) + 0.390 net: i_SIU/blink_timer_1_ 5.669 i_SIU/modgen_dec_1052_ix49941z50935:B (r) + 0.479 cell: ADLIB:NAND3C 6.148 i_SIU/modgen_dec_1052_ix49941z50935:Y (r) + 1.178 net: i_SIU/nx49941z4 7.326 i_SIU/modgen_dec_1052_ix49941z50934:A (r) + 0.347 cell: ADLIB:NAND3C 7.673 i_SIU/modgen_dec_1052_ix49941z50934:Y (r) + 1.121 net: i_SIU/nx49941z3 8.794 i_SIU/modgen_dec_1052_ix61907z50933:A (r) + 0.347 cell: ADLIB:NAND3C 9.141 i_SIU/modgen_dec_1052_ix61907z50933:Y (r) + 1.105 net: i_SIU/nx61907z2 10.246 i_SIU/modgen_dec_1052_ix52932z50933:A (r) + 0.347 cell: ADLIB:NAND3C 10.593 i_SIU/modgen_dec_1052_ix52932z50933:Y (r) + 0.270 net: i_SIU/nx52932z2 10.863 i_SIU/ix52932z43526:A (r) + 0.535 cell: ADLIB:XO1A 11.398 i_SIU/ix52932z43526:Y (r) + 0.249 net: i_SIU/nx52932z1 11.647 i_SIU/reg_blink_timer(20):D (r) 11.647 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.830 net: i_SIU/tx_clk_2b 23.008 i_SIU/reg_blink_timer(20):CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.580 i_SIU/reg_blink_timer(20):D 22.580 data required time Expanded Path 9 From: i_SIU/reg_blink_timer(1):CLK To: i_SIU/reg_blink_timer(22):D data required time 22.580 data arrival time - 11.642 slack 10.938 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(1):CLK (r) + 0.434 cell: ADLIB:DFN1C0 5.279 i_SIU/reg_blink_timer(1):Q (r) + 0.390 net: i_SIU/blink_timer_1_ 5.669 i_SIU/modgen_dec_1052_ix49941z50935:B (r) + 0.479 cell: ADLIB:NAND3C 6.148 i_SIU/modgen_dec_1052_ix49941z50935:Y (r) + 1.178 net: i_SIU/nx49941z4 7.326 i_SIU/modgen_dec_1052_ix49941z50934:A (r) + 0.347 cell: ADLIB:NAND3C 7.673 i_SIU/modgen_dec_1052_ix49941z50934:Y (r) + 1.121 net: i_SIU/nx49941z3 8.794 i_SIU/modgen_dec_1052_ix61907z50933:A (r) + 0.347 cell: ADLIB:NAND3C 9.141 i_SIU/modgen_dec_1052_ix61907z50933:Y (r) + 1.121 net: i_SIU/nx61907z2 10.262 i_SIU/NOT_modgen_dec_1052_ix50938z50933:A (r) + 0.347 cell: ADLIB:NAND3C 10.609 i_SIU/NOT_modgen_dec_1052_ix50938z50933:Y (r) + 0.249 net: i_SIU/nx50938z2 10.858 i_SIU/ix50938z43526:A (r) + 0.535 cell: ADLIB:XO1A 11.393 i_SIU/ix50938z43526:Y (r) + 0.249 net: i_SIU/nx50938z1 11.642 i_SIU/reg_blink_timer(22):D (r) 11.642 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.830 net: i_SIU/tx_clk_2b 23.008 i_SIU/reg_blink_timer(22):CLK (r) - 0.428 Library setup time: ADLIB:DFN1P0 22.580 i_SIU/reg_blink_timer(22):D 22.580 data required time Expanded Path 10 From: i_SIU/reg_blink_timer(0):CLK To: i_SIU/reg_blink_timer(9):D data required time 22.614 data arrival time - 11.656 slack 10.958 ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.849 net: i_SIU/tx_clk_2b 4.845 i_SIU/reg_blink_timer(0):CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.395 i_SIU/reg_blink_timer(0):Q (f) + 0.402 net: i_SIU/blink_timer_0_ 5.797 i_SIU/modgen_dec_1052_ix49941z50935:A (f) + 0.365 cell: ADLIB:NAND3C 6.162 i_SIU/modgen_dec_1052_ix49941z50935:Y (f) + 1.075 net: i_SIU/nx49941z4 7.237 i_SIU/modgen_dec_1052_ix49941z50934:A (f) + 0.392 cell: ADLIB:NAND3C 7.629 i_SIU/modgen_dec_1052_ix49941z50934:Y (f) + 1.818 net: i_SIU/nx49941z3 9.447 i_SIU/modgen_dec_1052_ix58157z49936:A (f) + 0.401 cell: ADLIB:NAND2B 9.848 i_SIU/modgen_dec_1052_ix58157z49936:Y (f) + 0.321 net: i_SIU/nx58157z3 10.169 i_SIU/modgen_dec_1052_ix58157z50933:A (f) + 0.392 cell: ADLIB:NAND3C 10.561 i_SIU/modgen_dec_1052_ix58157z50933:Y (f) + 0.239 net: i_SIU/nx58157z2 10.800 i_SIU/ix58157z43526:B (f) + 0.615 cell: ADLIB:XO1A 11.415 i_SIU/ix58157z43526:Y (f) + 0.241 net: i_SIU/nx58157z1 11.656 i_SIU/reg_blink_timer(9):D (f) 11.656 data arrival time ________________________________________________________ Data required time calculation 18.182 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 18.182 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 21.642 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 22.178 i_SIU/cbuf_tx_clk_2:Y (r) + 0.838 net: i_SIU/tx_clk_2b 23.016 i_SIU/reg_blink_timer(9):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 22.614 i_SIU/reg_blink_timer(9):D 22.614 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(5):D Delay (ns): 6.563 Slack (ns): Arrival (ns): 6.563 Required (ns): Setup (ns): 0.402 External Setup (ns): 2.145 Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Delay (ns): 6.382 Slack (ns): Arrival (ns): 6.382 Required (ns): Setup (ns): 0.402 External Setup (ns): 1.964 Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(3):D Delay (ns): 6.367 Slack (ns): Arrival (ns): 6.367 Required (ns): Setup (ns): 0.402 External Setup (ns): 1.935 Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Delay (ns): 6.199 Slack (ns): Arrival (ns): 6.199 Required (ns): Setup (ns): 0.402 External Setup (ns): 1.781 Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Delay (ns): 6.199 Slack (ns): Arrival (ns): 6.199 Required (ns): Setup (ns): 0.402 External Setup (ns): 1.781 Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Delay (ns): 6.163 Slack (ns): Arrival (ns): 6.163 Required (ns): Setup (ns): 0.402 External Setup (ns): 1.745 Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(1):D Delay (ns): 5.378 Slack (ns): Arrival (ns): 5.378 Required (ns): Setup (ns): 0.428 External Setup (ns): 0.999 Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Delay (ns): 5.369 Slack (ns): Arrival (ns): 5.369 Required (ns): Setup (ns): 0.402 External Setup (ns): 0.951 Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Delay (ns): 5.220 Slack (ns): Arrival (ns): 5.220 Required (ns): Setup (ns): 0.402 External Setup (ns): 0.788 Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D Delay (ns): 5.097 Slack (ns): Arrival (ns): 5.097 Required (ns): Setup (ns): 0.402 External Setup (ns): 0.690 Expanded Path 1 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(5):D data required time N/C data arrival time - 6.563 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 3.130 net: SDA_ID_i 4.331 i_SIU/I2CIF_INST/ix29577z26293:A (r) + 0.497 cell: ADLIB:MX2C 4.828 i_SIU/I2CIF_INST/ix29577z26293:Y (f) + 0.285 net: i_SIU/I2CIF_INST/nx29577z3 5.113 i_SIU/I2CIF_INST/ix27583z24339:B (f) + 0.471 cell: ADLIB:NAND2 5.584 i_SIU/I2CIF_INST/ix27583z24339:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx27583z2 5.833 i_SIU/I2CIF_INST/ix27583z40557:C (r) + 0.489 cell: ADLIB:AO1C 6.322 i_SIU/I2CIF_INST/ix27583z40557:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx27583z1 6.563 i_SIU/I2CIF_INST/reg_i2c_present(5):D (f) 6.563 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(5):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(5):D Expanded Path 2 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(6):D data required time N/C data arrival time - 6.382 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 4.435 net: SDA_ID_i 5.636 i_SIU/I2CIF_INST/ix14517z14896:A (r) + 0.497 cell: ADLIB:MX2 6.133 i_SIU/I2CIF_INST/ix14517z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx14517z1 6.382 i_SIU/I2CIF_INST/reg_i2c_rddata(6):D (r) 6.382 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(6):D Expanded Path 3 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(3):D data required time N/C data arrival time - 6.367 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 3.130 net: SDA_ID_i 4.331 i_SIU/I2CIF_INST/ix29577z26293:A (r) + 0.497 cell: ADLIB:MX2C 4.828 i_SIU/I2CIF_INST/ix29577z26293:Y (f) + 0.274 net: i_SIU/I2CIF_INST/nx29577z3 5.102 i_SIU/I2CIF_INST/ix29577z24339:A (f) + 0.288 cell: ADLIB:NAND2 5.390 i_SIU/I2CIF_INST/ix29577z24339:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx29577z2 5.639 i_SIU/I2CIF_INST/ix29577z40557:C (r) + 0.489 cell: ADLIB:AO1C 6.128 i_SIU/I2CIF_INST/ix29577z40557:Y (f) + 0.239 net: i_SIU/I2CIF_INST/nx29577z1 6.367 i_SIU/I2CIF_INST/reg_i2c_present(3):D (f) 6.367 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.838 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(3):CLK (r) - 0.402 Library setup time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(3):D Expanded Path 4 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(5):D data required time N/C data arrival time - 6.199 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 4.252 net: SDA_ID_i 5.453 i_SIU/I2CIF_INST/ix13520z14896:A (r) + 0.497 cell: ADLIB:MX2 5.950 i_SIU/I2CIF_INST/ix13520z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx13520z1 6.199 i_SIU/I2CIF_INST/reg_i2c_rddata(5):D (r) 6.199 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(5):D Expanded Path 5 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(4):D data required time N/C data arrival time - 6.199 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 4.252 net: SDA_ID_i 5.453 i_SIU/I2CIF_INST/ix12523z14896:A (r) + 0.497 cell: ADLIB:MX2 5.950 i_SIU/I2CIF_INST/ix12523z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx12523z1 6.199 i_SIU/I2CIF_INST/reg_i2c_rddata(4):D (r) 6.199 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(4):D Expanded Path 6 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(7):D data required time N/C data arrival time - 6.163 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 4.216 net: SDA_ID_i 5.417 i_SIU/I2CIF_INST/ix15514z14896:A (r) + 0.497 cell: ADLIB:MX2 5.914 i_SIU/I2CIF_INST/ix15514z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx15514z1 6.163 i_SIU/I2CIF_INST/reg_i2c_rddata(7):D (r) 6.163 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(7):D Expanded Path 7 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_present(1):D data required time N/C data arrival time - 5.378 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 2.843 net: SDA_ID_i 4.044 i_SIU/I2CIF_INST/ix31571z50932:B (r) + 0.365 cell: ADLIB:NAND3A 4.409 i_SIU/I2CIF_INST/ix31571z50932:Y (f) + 0.241 net: i_SIU/I2CIF_INST/nx31571z3 4.650 i_SIU/I2CIF_INST/ix31571z24337:B (f) + 0.479 cell: ADLIB:NAND3 5.129 i_SIU/I2CIF_INST/ix31571z24337:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx31571z1 5.378 i_SIU/I2CIF_INST/reg_i2c_present(1):D (r) 5.378 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.811 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_present(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C0 N/C i_SIU/I2CIF_INST/reg_i2c_present(1):D Expanded Path 8 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(0):D data required time N/C data arrival time - 5.369 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 3.422 net: SDA_ID_i 4.623 i_SIU/I2CIF_INST/ix8535z14896:A (r) + 0.497 cell: ADLIB:MX2 5.120 i_SIU/I2CIF_INST/ix8535z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx8535z1 5.369 i_SIU/I2CIF_INST/reg_i2c_rddata(0):D (r) 5.369 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.824 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(0):D Expanded Path 9 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(2):D data required time N/C data arrival time - 5.220 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 3.273 net: SDA_ID_i 4.474 i_SIU/I2CIF_INST/ix10529z14896:A (r) + 0.497 cell: ADLIB:MX2 4.971 i_SIU/I2CIF_INST/ix10529z14896:Y (r) + 0.249 net: i_SIU/I2CIF_INST/nx10529z1 5.220 i_SIU/I2CIF_INST/reg_i2c_rddata(2):D (r) 5.220 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.838 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(2):D Expanded Path 10 From: SDA_ID To: i_SIU/I2CIF_INST/reg_i2c_rddata(3):D data required time N/C data arrival time - 5.097 slack N/C ________________________________________________________ Data arrival time calculation 0.000 SDA_ID (r) + 0.000 net: SDA_ID 0.000 bbuf_SDA_ID/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_SDA_ID/U0/U0:Y (r) + 0.000 net: bbuf_SDA_ID/U0/NET3 1.169 bbuf_SDA_ID/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_SDA_ID/U0/U1:Y (r) + 3.147 net: SDA_ID_i 4.348 i_SIU/I2CIF_INST/ix11526z14896:A (r) + 0.497 cell: ADLIB:MX2 4.845 i_SIU/I2CIF_INST/ix11526z14896:Y (r) + 0.252 net: i_SIU/I2CIF_INST/nx11526z1 5.097 i_SIU/I2CIF_INST/reg_i2c_rddata(3):D (r) 5.097 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 N/C i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT N/C i_SIU/cbuf_tx_clk_2:Y (r) + 0.813 net: i_SIU/tx_clk_2b N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):CLK (r) - 0.402 Library setup time: ADLIB:DFN1P0 N/C i_SIU/I2CIF_INST/reg_i2c_rddata(3):D END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_SIU/reg_led4:CLK To: LED_SIU(4) Delay (ns): 8.555 Slack (ns): Arrival (ns): 13.371 Required (ns): Clock to Out (ns): 13.371 Path 2 From: i_SIU/reg_led3:CLK To: LED_SIU(3) Delay (ns): 8.538 Slack (ns): Arrival (ns): 13.339 Required (ns): Clock to Out (ns): 13.339 Path 3 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID Delay (ns): 7.847 Slack (ns): Arrival (ns): 12.664 Required (ns): Clock to Out (ns): 12.664 Path 4 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID Delay (ns): 7.771 Slack (ns): Arrival (ns): 12.583 Required (ns): Clock to Out (ns): 12.583 Path 5 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID Delay (ns): 7.637 Slack (ns): Arrival (ns): 12.453 Required (ns): Clock to Out (ns): 12.453 Expanded Path 1 From: i_SIU/reg_led4:CLK To: LED_SIU(4) data required time N/C data arrival time - 13.371 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.820 net: i_SIU/tx_clk_2b 4.816 i_SIU/reg_led4:CLK (r) + 0.550 cell: ADLIB:DFN1C0 5.366 i_SIU/reg_led4:Q (f) + 2.455 net: LED_SIU_i_4_ 7.821 genblk5[4].leds_siu_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 8.313 genblk5[4].leds_siu_U1/U0/U1:DOUT (f) + 0.000 net: genblk5[4]_leds_siu_U1/U0/NET1 8.313 genblk5[4].leds_siu_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 13.371 genblk5[4].leds_siu_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_4_ 13.371 LED_SIU(4) (f) 13.371 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(4) (f) Expanded Path 2 From: i_SIU/reg_led3:CLK To: LED_SIU(3) data required time N/C data arrival time - 13.339 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.805 net: i_SIU/tx_clk_2b 4.801 i_SIU/reg_led3:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.351 i_SIU/reg_led3:Q (f) + 2.495 net: LED_SIU_i_3_ 7.846 genblk5[3].leds_siu_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 8.281 genblk5[3].leds_siu_U1/U0/U1:DOUT (f) + 0.000 net: genblk5[3]_leds_siu_U1/U0/NET1 8.281 genblk5[3].leds_siu_U1/U0/U0:D (f) + 5.058 cell: ADLIB:IOPAD_TRI 13.339 genblk5[3].leds_siu_U1/U0/U0:PAD (f) + 0.000 net: LED_SIU_3_ 13.339 LED_SIU(3) (f) 13.339 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C LED_SIU(3) (f) Expanded Path 3 From: i_SIU/I2CIF_INST/reg_i2c_scl:CLK To: SCL_ID data required time N/C data arrival time - 12.664 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.821 net: i_SIU/tx_clk_2b 4.817 i_SIU/I2CIF_INST/reg_i2c_scl:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.367 i_SIU/I2CIF_INST/reg_i2c_scl:Q (f) + 2.363 net: SCL_ID_i 7.730 obuf_SCL_ID_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 8.165 obuf_SCL_ID_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SCL_ID_U1/U0/NET1 8.165 obuf_SCL_ID_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 12.664 obuf_SCL_ID_U1/U0/U0:PAD (f) + 0.000 net: SCL_ID 12.664 SCL_ID (f) 12.664 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SCL_ID (f) Expanded Path 4 From: i_SIU/I2CIF_INST/reg_s_sda_ena:CLK To: SDA_ID data required time N/C data arrival time - 12.583 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.816 net: i_SIU/tx_clk_2b 4.812 i_SIU/I2CIF_INST/reg_s_sda_ena:CLK (r) + 0.434 cell: ADLIB:DFN1P0 5.246 i_SIU/I2CIF_INST/reg_s_sda_ena:Q (r) + 2.435 net: SDA_ID_e 7.681 bbuf_SDA_ID/U0/U1:E (r) + 0.319 cell: ADLIB:IOBI_IB_OB_EB 8.000 bbuf_SDA_ID/U0/U1:EOUT (r) + 0.000 net: bbuf_SDA_ID/U0/NET2 8.000 bbuf_SDA_ID/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 12.583 bbuf_SDA_ID/U0/U0:PAD (f) + 0.000 net: SDA_ID 12.583 SDA_ID (f) 12.583 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (f) Expanded Path 5 From: i_SIU/I2CIF_INST/reg_s_sda_out:CLK To: SDA_ID data required time N/C data arrival time - 12.453 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_SIU/reg_tx_clk_2:Q + 0.000 Clock source 0.000 i_SIU/reg_tx_clk_2:Q (r) + 3.460 net: i_SIU/tx_clk_2 3.460 i_SIU/cbuf_tx_clk_2:A (r) + 0.536 cell: ADLIB:CLKINT 3.996 i_SIU/cbuf_tx_clk_2:Y (r) + 0.820 net: i_SIU/tx_clk_2b 4.816 i_SIU/I2CIF_INST/reg_s_sda_out:CLK (r) + 0.550 cell: ADLIB:DFN1P0 5.366 i_SIU/I2CIF_INST/reg_s_sda_out:Q (f) + 2.153 net: SDA_ID_o 7.519 bbuf_SDA_ID/U0/U1:D (f) + 0.435 cell: ADLIB:IOBI_IB_OB_EB 7.954 bbuf_SDA_ID/U0/U1:DOUT (f) + 0.000 net: bbuf_SDA_ID/U0/NET1 7.954 bbuf_SDA_ID/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_BI 12.453 bbuf_SDA_ID/U0/U0:PAD (f) + 0.000 net: SDA_ID 12.453 SDA_ID (f) 12.453 data arrival time ________________________________________________________ Data required time calculation N/C i_SIU/reg_tx_clk_2:Q + 0.000 Clock source N/C i_SIU/reg_tx_clk_2:Q (r) N/C SDA_ID (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_adc/cdiv_reg_q:Q SET Register to Register Path 1 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(3)(1):E Delay (ns): 13.536 Slack (ns): 86.014 Arrival (ns): 16.327 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.986 Path 2 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(3)(4):E Delay (ns): 13.464 Slack (ns): 86.086 Arrival (ns): 16.255 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.914 Path 3 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(3)(6):E Delay (ns): 13.448 Slack (ns): 86.107 Arrival (ns): 16.239 Required (ns): 102.346 Setup (ns): 0.454 Minimum Period (ns): 13.893 Path 4 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK To: i_adc/ds_tsens/reg_read_reg(3)(1):E Delay (ns): 13.102 Slack (ns): 86.441 Arrival (ns): 15.900 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.559 Path 5 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK To: i_adc/ds_tsens/reg_read_reg(3)(4):E Delay (ns): 13.030 Slack (ns): 86.513 Arrival (ns): 15.828 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.487 Path 6 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK To: i_adc/ds_tsens/reg_read_reg(3)(6):E Delay (ns): 13.014 Slack (ns): 86.534 Arrival (ns): 15.812 Required (ns): 102.346 Setup (ns): 0.454 Minimum Period (ns): 13.466 Path 7 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(1)(5):E Delay (ns): 13.000 Slack (ns): 86.546 Arrival (ns): 15.791 Required (ns): 102.337 Setup (ns): 0.454 Minimum Period (ns): 13.454 Path 8 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(1)(6):E Delay (ns): 12.976 Slack (ns): 86.574 Arrival (ns): 15.767 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.426 Path 9 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(3)(1):E Delay (ns): 12.931 Slack (ns): 86.589 Arrival (ns): 15.752 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.411 Path 10 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(3)(4):E Delay (ns): 12.859 Slack (ns): 86.661 Arrival (ns): 15.680 Required (ns): 102.341 Setup (ns): 0.454 Minimum Period (ns): 13.339 Expanded Path 1 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(3)(1):E data required time 102.341 data arrival time - 16.327 slack 86.014 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 2.791 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.225 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 1.863 net: i_adc/ds_tsens/paddr_0_ 5.088 i_adc/ds_tsens/prg/NOT_ix33154z50932:A (r) + 0.509 cell: ADLIB:NAND3A 5.597 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.654 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 7.226 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 8.042 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.539 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.781 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 9.173 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.982 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.461 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 13.480 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.827 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.500 net: i_adc/ds_tsens/nx44898z1 16.327 i_adc/ds_tsens/reg_read_reg(3)(1):E (f) 16.327 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(3)(1):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(3)(1):E 102.341 data required time Expanded Path 2 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(3)(4):E data required time 102.341 data arrival time - 16.255 slack 86.086 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 2.791 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.225 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 1.863 net: i_adc/ds_tsens/paddr_0_ 5.088 i_adc/ds_tsens/prg/NOT_ix33154z50932:A (r) + 0.509 cell: ADLIB:NAND3A 5.597 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.654 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 7.226 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 8.042 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.539 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.781 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 9.173 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.982 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.461 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 13.480 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.827 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.428 net: i_adc/ds_tsens/nx44898z1 16.255 i_adc/ds_tsens/reg_read_reg(3)(4):E (f) 16.255 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(3)(4):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(3)(4):E 102.341 data required time Expanded Path 3 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(3)(6):E data required time 102.346 data arrival time - 16.239 slack 86.107 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 2.791 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.225 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 1.863 net: i_adc/ds_tsens/paddr_0_ 5.088 i_adc/ds_tsens/prg/NOT_ix33154z50932:A (r) + 0.509 cell: ADLIB:NAND3A 5.597 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.654 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 7.226 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 8.042 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.539 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.781 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 9.173 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.982 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.461 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 13.480 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.827 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.412 net: i_adc/ds_tsens/nx44898z1 16.239 i_adc/ds_tsens/reg_read_reg(3)(6):E (f) 16.239 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.821 net: i_adc/clk1MHz_b 102.800 i_adc/ds_tsens/reg_read_reg(3)(6):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.346 i_adc/ds_tsens/reg_read_reg(3)(6):E 102.346 data required time Expanded Path 4 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK To: i_adc/ds_tsens/reg_read_reg(3)(1):E data required time 102.341 data arrival time - 15.900 slack 86.441 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.819 net: i_adc/clk1MHz_b 2.798 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.348 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):Q (f) + 1.475 net: i_adc/ds_tsens/paddr_1_ 4.823 i_adc/ds_tsens/prg/NOT_ix33154z50932:B (f) + 0.347 cell: ADLIB:NAND3A 5.170 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.227 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 6.799 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 7.615 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.112 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.354 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 8.746 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.555 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.034 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 13.053 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.400 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.500 net: i_adc/ds_tsens/nx44898z1 15.900 i_adc/ds_tsens/reg_read_reg(3)(1):E (f) 15.900 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(3)(1):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(3)(1):E 102.341 data required time Expanded Path 5 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK To: i_adc/ds_tsens/reg_read_reg(3)(4):E data required time 102.341 data arrival time - 15.828 slack 86.513 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.819 net: i_adc/clk1MHz_b 2.798 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.348 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):Q (f) + 1.475 net: i_adc/ds_tsens/paddr_1_ 4.823 i_adc/ds_tsens/prg/NOT_ix33154z50932:B (f) + 0.347 cell: ADLIB:NAND3A 5.170 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.227 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 6.799 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 7.615 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.112 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.354 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 8.746 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.555 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.034 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 13.053 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.400 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.428 net: i_adc/ds_tsens/nx44898z1 15.828 i_adc/ds_tsens/reg_read_reg(3)(4):E (f) 15.828 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(3)(4):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(3)(4):E 102.341 data required time Expanded Path 6 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK To: i_adc/ds_tsens/reg_read_reg(3)(6):E data required time 102.346 data arrival time - 15.812 slack 86.534 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.819 net: i_adc/clk1MHz_b 2.798 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.348 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):Q (f) + 1.475 net: i_adc/ds_tsens/paddr_1_ 4.823 i_adc/ds_tsens/prg/NOT_ix33154z50932:B (f) + 0.347 cell: ADLIB:NAND3A 5.170 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.227 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 6.799 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 7.615 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.112 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.354 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 8.746 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.555 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.034 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 13.053 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.400 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.412 net: i_adc/ds_tsens/nx44898z1 15.812 i_adc/ds_tsens/reg_read_reg(3)(6):E (f) 15.812 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.821 net: i_adc/clk1MHz_b 102.800 i_adc/ds_tsens/reg_read_reg(3)(6):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.346 i_adc/ds_tsens/reg_read_reg(3)(6):E 102.346 data required time Expanded Path 7 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(1)(5):E data required time 102.337 data arrival time - 15.791 slack 86.546 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 2.791 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.225 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 1.863 net: i_adc/ds_tsens/paddr_0_ 5.088 i_adc/ds_tsens/prg/NOT_ix33154z50932:A (r) + 0.509 cell: ADLIB:NAND3A 5.597 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.654 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 7.226 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 8.042 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.539 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.781 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 9.173 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.982 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.461 i_adc/ds_tsens/ix60303z50932:Y (r) + 2.230 net: i_adc/ds_tsens/nx60303z2 12.691 i_adc/ds_tsens/ix55168z2957:A (r) + 0.347 cell: ADLIB:AND3B 13.038 i_adc/ds_tsens/ix55168z2957:Y (f) + 2.753 net: i_adc/ds_tsens/nx55168z1 15.791 i_adc/ds_tsens/reg_read_reg(1)(5):E (f) 15.791 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 102.791 i_adc/ds_tsens/reg_read_reg(1)(5):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.337 i_adc/ds_tsens/reg_read_reg(1)(5):E 102.337 data required time Expanded Path 8 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK To: i_adc/ds_tsens/reg_read_reg(1)(6):E data required time 102.341 data arrival time - 15.767 slack 86.574 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 2.791 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.225 i_adc/ds_tsens/modgen_counter_paddr_reg_q(0):Q (r) + 1.863 net: i_adc/ds_tsens/paddr_0_ 5.088 i_adc/ds_tsens/prg/NOT_ix33154z50932:A (r) + 0.509 cell: ADLIB:NAND3A 5.597 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.654 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 7.226 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 8.042 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 8.539 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.781 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 9.173 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.982 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 10.461 i_adc/ds_tsens/ix60303z50932:Y (r) + 2.230 net: i_adc/ds_tsens/nx60303z2 12.691 i_adc/ds_tsens/ix55168z2957:A (r) + 0.347 cell: ADLIB:AND3B 13.038 i_adc/ds_tsens/ix55168z2957:Y (f) + 2.729 net: i_adc/ds_tsens/nx55168z1 15.767 i_adc/ds_tsens/reg_read_reg(1)(6):E (f) 15.767 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(1)(6):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(1)(6):E 102.341 data required time Expanded Path 9 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(3)(1):E data required time 102.341 data arrival time - 15.752 slack 86.589 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.842 net: i_adc/clk1MHz_b 2.821 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.371 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):Q (f) + 1.198 net: i_adc/ds_tsens/paddr_3_ 4.569 i_adc/ds_tsens/prg/NOT_ix33154z50932:C (f) + 0.453 cell: ADLIB:NAND3A 5.022 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.079 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 6.651 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 7.467 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.964 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.206 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 8.598 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.407 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 9.886 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 12.905 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.252 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.500 net: i_adc/ds_tsens/nx44898z1 15.752 i_adc/ds_tsens/reg_read_reg(3)(1):E (f) 15.752 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(3)(1):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(3)(1):E 102.341 data required time Expanded Path 10 From: i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK To: i_adc/ds_tsens/reg_read_reg(3)(4):E data required time 102.341 data arrival time - 15.680 slack 86.661 ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.842 net: i_adc/clk1MHz_b 2.821 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):CLK (r) + 0.550 cell: ADLIB:DFN1C1 3.371 i_adc/ds_tsens/modgen_counter_paddr_reg_q(3):Q (f) + 1.198 net: i_adc/ds_tsens/paddr_3_ 4.569 i_adc/ds_tsens/prg/NOT_ix33154z50932:C (f) + 0.453 cell: ADLIB:NAND3A 5.022 i_adc/ds_tsens/prg/NOT_ix33154z50932:Y (r) + 1.057 net: i_adc/ds_tsens/prg/nx33154z3 6.079 i_adc/ds_tsens/prg/ix26175z40558:C (r) + 0.572 cell: ADLIB:AO1C 6.651 i_adc/ds_tsens/prg/ix26175z40558:Y (f) + 0.816 net: i_adc/ds_tsens/prg/nx26175z2 7.467 i_adc/ds_tsens/prg/ix26175z50930:A (f) + 0.497 cell: ADLIB:NAND3A 7.964 i_adc/ds_tsens/prg/ix26175z50930:Y (f) + 0.242 net: i_adc/ds_tsens/prg/nx26175z1 8.206 i_adc/ds_tsens/prg/rdata(2):A (f) + 0.392 cell: ADLIB:AND3A 8.598 i_adc/ds_tsens/prg/rdata(2):Y (r) + 0.809 net: i_adc/ds_tsens/pdata_2_ 9.407 i_adc/ds_tsens/ix60303z50932:B (r) + 0.479 cell: ADLIB:NAND3B 9.886 i_adc/ds_tsens/ix60303z50932:Y (r) + 3.019 net: i_adc/ds_tsens/nx60303z2 12.905 i_adc/ds_tsens/ix44898z2956:A (r) + 0.347 cell: ADLIB:AND3A 13.252 i_adc/ds_tsens/ix44898z2956:Y (f) + 2.428 net: i_adc/ds_tsens/nx44898z1 15.680 i_adc/ds_tsens/reg_read_reg(3)(4):E (f) 15.680 data arrival time ________________________________________________________ Data required time calculation 100.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 100.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 101.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 101.979 i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b 102.795 i_adc/ds_tsens/reg_read_reg(3)(4):CLK (r) - 0.454 Library setup time: ADLIB:DFN1E1 102.341 i_adc/ds_tsens/reg_read_reg(3)(4):E 102.341 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D Delay (ns): 4.270 Slack (ns): Arrival (ns): 4.270 Required (ns): Setup (ns): 0.402 External Setup (ns): 1.881 Expanded Path 1 From: TSENS To: i_adc/ds_tsens/bsl/ts/reg_retbit:D data required time N/C data arrival time - 4.270 slack N/C ________________________________________________________ Data arrival time calculation 0.000 TSENS (r) + 0.000 net: TSENS 0.000 bbuf_TSENS/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_BI 1.169 bbuf_TSENS/U0/U0:Y (r) + 0.000 net: bbuf_TSENS/U0/NET3 1.169 bbuf_TSENS/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOBI_IB_OB_EB 1.201 bbuf_TSENS/U0/U1:Y (r) + 2.314 net: TSENS_i 3.515 i_adc/ds_tsens/bsl/ts/ix5225z14896:B (r) + 0.506 cell: ADLIB:MX2 4.021 i_adc/ds_tsens/bsl/ts/ix5225z14896:Y (r) + 0.249 net: i_adc/ds_tsens/bsl/ts/nx5225z1 4.270 i_adc/ds_tsens/bsl/ts/reg_retbit:D (r) 4.270 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_retbit:CLK (r) - 0.402 Library setup time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_retbit:D END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS Delay (ns): 7.386 Slack (ns): Arrival (ns): 10.207 Required (ns): Clock to Out (ns): 10.207 Path 2 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS Delay (ns): 7.319 Slack (ns): Arrival (ns): 10.110 Required (ns): Clock to Out (ns): 10.110 Expanded Path 1 From: i_adc/ds_tsens/bsl/reg_hold_high:CLK To: TSENS data required time N/C data arrival time - 10.207 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.842 net: i_adc/clk1MHz_b 2.821 i_adc/ds_tsens/bsl/reg_hold_high:CLK (r) + 0.434 cell: ADLIB:DFN1C1 3.255 i_adc/ds_tsens/bsl/reg_hold_high:Q (r) + 1.541 net: TSENS_o 4.796 i_adc/ds_tsens/bsl/oe:A (r) + 0.271 cell: ADLIB:NAND2B 5.067 i_adc/ds_tsens/bsl/oe:Y (r) + 0.238 net: TSENS_e 5.305 bbuf_TSENS/U0/U1:E (r) + 0.319 cell: ADLIB:IOBI_IB_OB_EB 5.624 bbuf_TSENS/U0/U1:EOUT (r) + 0.000 net: bbuf_TSENS/U0/NET2 5.624 bbuf_TSENS/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 10.207 bbuf_TSENS/U0/U0:PAD (f) + 0.000 net: TSENS 10.207 TSENS (f) 10.207 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (f) Expanded Path 2 From: i_adc/ds_tsens/bsl/ts/reg_oe:CLK To: TSENS data required time N/C data arrival time - 10.110 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_adc/cdiv_reg_q:Q + 0.000 Clock source 0.000 i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz 1.421 i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT 1.979 i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b 2.791 i_adc/ds_tsens/bsl/ts/reg_oe:CLK (r) + 0.434 cell: ADLIB:DFN1 3.225 i_adc/ds_tsens/bsl/ts/reg_oe:Q (r) + 1.304 net: i_adc/ds_tsens/bsl/oe_i 4.529 i_adc/ds_tsens/bsl/oe:B (r) + 0.441 cell: ADLIB:NAND2B 4.970 i_adc/ds_tsens/bsl/oe:Y (r) + 0.238 net: TSENS_e 5.208 bbuf_TSENS/U0/U1:E (r) + 0.319 cell: ADLIB:IOBI_IB_OB_EB 5.527 bbuf_TSENS/U0/U1:EOUT (r) + 0.000 net: bbuf_TSENS/U0/NET2 5.527 bbuf_TSENS/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 10.110 bbuf_TSENS/U0/U0:PAD (f) + 0.000 net: TSENS 10.110 TSENS (f) 10.110 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) N/C TSENS (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: i_adc/ds_tsens/reg_q(6):CLR Delay (ns): 10.696 Slack (ns): Arrival (ns): 10.696 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.123 Path 2 From: PUSHB To: i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR Delay (ns): 10.678 Slack (ns): Arrival (ns): 10.678 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.109 Path 3 From: PUSHB To: i_adc/ds_tsens/reg_q(5):CLR Delay (ns): 10.618 Slack (ns): Arrival (ns): 10.618 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 8.049 Path 4 From: RST_n To: i_adc/ds_tsens/reg_q(6):CLR Delay (ns): 10.502 Slack (ns): Arrival (ns): 10.502 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.929 Path 5 From: RST_n To: i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR Delay (ns): 10.484 Slack (ns): Arrival (ns): 10.484 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.915 Path 6 From: PUSHB To: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR Delay (ns): 10.479 Slack (ns): Arrival (ns): 10.479 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.903 Path 7 From: RST_n To: i_adc/ds_tsens/reg_q(5):CLR Delay (ns): 10.424 Slack (ns): Arrival (ns): 10.424 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.855 Path 8 From: PUSHB To: i_adc/ds_tsens/reg_q(13):CLR Delay (ns): 10.399 Slack (ns): Arrival (ns): 10.399 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.809 Path 9 From: RST_n To: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR Delay (ns): 10.285 Slack (ns): Arrival (ns): 10.285 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.709 Path 10 From: RST_n To: i_adc/ds_tsens/reg_q(13):CLR Delay (ns): 10.205 Slack (ns): Arrival (ns): 10.205 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 7.615 Expanded Path 1 From: PUSHB To: i_adc/ds_tsens/reg_q(6):CLR data required time N/C data arrival time - 10.696 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 5.143 net: not_rst_n 10.696 i_adc/ds_tsens/reg_q(6):CLR (f) 10.696 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(6):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(6):CLR Expanded Path 2 From: PUSHB To: i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR data required time N/C data arrival time - 10.678 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 5.125 net: not_rst_n 10.678 i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR (f) 10.678 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_counter(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR Expanded Path 3 From: PUSHB To: i_adc/ds_tsens/reg_q(5):CLR data required time N/C data arrival time - 10.618 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 5.065 net: not_rst_n 10.618 i_adc/ds_tsens/reg_q(5):CLR (f) 10.618 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(5):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(5):CLR Expanded Path 4 From: RST_n To: i_adc/ds_tsens/reg_q(6):CLR data required time N/C data arrival time - 10.502 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 5.143 net: not_rst_n 10.502 i_adc/ds_tsens/reg_q(6):CLR (f) 10.502 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.816 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(6):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(6):CLR Expanded Path 5 From: RST_n To: i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR data required time N/C data arrival time - 10.484 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 5.125 net: not_rst_n 10.484 i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR (f) 10.484 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/bsl/ts/reg_counter(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/bsl/ts/reg_counter(0):CLR Expanded Path 6 From: PUSHB To: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR data required time N/C data arrival time - 10.479 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 4.926 net: not_rst_n 10.479 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR (f) 10.479 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.819 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR Expanded Path 7 From: RST_n To: i_adc/ds_tsens/reg_q(5):CLR data required time N/C data arrival time - 10.424 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 5.065 net: not_rst_n 10.424 i_adc/ds_tsens/reg_q(5):CLR (f) 10.424 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.812 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(5):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(5):CLR Expanded Path 8 From: PUSHB To: i_adc/ds_tsens/reg_q(13):CLR data required time N/C data arrival time - 10.399 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 4.846 net: not_rst_n 10.399 i_adc/ds_tsens/reg_q(13):CLR (f) 10.399 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.833 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(13):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(13):CLR Expanded Path 9 From: RST_n To: i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR data required time N/C data arrival time - 10.285 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 4.926 net: not_rst_n 10.285 i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR (f) 10.285 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.819 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/modgen_counter_paddr_reg_q(1):CLR Expanded Path 10 From: RST_n To: i_adc/ds_tsens/reg_q(13):CLR data required time N/C data arrival time - 10.205 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 4.846 net: not_rst_n 10.205 i_adc/ds_tsens/reg_q(13):CLR (f) 10.205 data arrival time ________________________________________________________ Data required time calculation N/C i_adc/cdiv_reg_q:Q + 0.000 Clock source N/C i_adc/cdiv_reg_q:Q (r) + 1.421 net: i_adc/clk1MHz N/C i_adc/cbuf_1MHz:A (r) + 0.558 cell: ADLIB:CLKINT N/C i_adc/cbuf_1MHz:Y (r) + 0.833 net: i_adc/clk1MHz_b N/C i_adc/ds_tsens/reg_q(13):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/ds_tsens/reg_q(13):CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLA SET Register to Register Path 1 From: i_cbb/ram_cnt_inst/reg_req_addr(0):CLK To: i_cbb/ram_cnt_inst/reg_scsn_dout(22):D Delay (ns): 18.714 Slack (ns): 5.841 Arrival (ns): 26.500 Required (ns): 32.341 Setup (ns): 0.402 Minimum Period (ns): 19.159 Path 2 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D Delay (ns): 18.426 Slack (ns): 6.145 Arrival (ns): 26.138 Required (ns): 32.283 Setup (ns): 0.428 Minimum Period (ns): 18.855 Path 3 From: i_cbb/ram_cnt_inst/gen_cnt_fast_2_cnt_i/reg_cout_hold:CLK To: i_cbb/ram_cnt_inst/reg_scsn_dout(22):D Delay (ns): 18.297 Slack (ns): 6.286 Arrival (ns): 26.055 Required (ns): 32.341 Setup (ns): 0.402 Minimum Period (ns): 18.714 Path 4 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D Delay (ns): 18.229 Slack (ns): 6.343 Arrival (ns): 25.941 Required (ns): 32.284 Setup (ns): 0.428 Minimum Period (ns): 18.657 Path 5 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D Delay (ns): 18.089 Slack (ns): 6.459 Arrival (ns): 25.825 Required (ns): 32.284 Setup (ns): 0.428 Minimum Period (ns): 18.541 Path 6 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D Delay (ns): 18.084 Slack (ns): 6.463 Arrival (ns): 25.820 Required (ns): 32.283 Setup (ns): 0.428 Minimum Period (ns): 18.537 Path 7 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D Delay (ns): 18.083 Slack (ns): 6.464 Arrival (ns): 25.819 Required (ns): 32.283 Setup (ns): 0.428 Minimum Period (ns): 18.536 Path 8 From: i_cbb/ram_cnt_inst/gen_cnt_fast_1_cnt_i_reg_cout_hold:CLK To: i_cbb/ram_cnt_inst/reg_scsn_dout(22):D Delay (ns): 18.114 Slack (ns): 6.469 Arrival (ns): 25.872 Required (ns): 32.341 Setup (ns): 0.402 Minimum Period (ns): 18.531 Path 9 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(1):D Delay (ns): 18.070 Slack (ns): 6.477 Arrival (ns): 25.806 Required (ns): 32.283 Setup (ns): 0.428 Minimum Period (ns): 18.523 Path 10 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D Delay (ns): 18.041 Slack (ns): 6.507 Arrival (ns): 25.777 Required (ns): 32.284 Setup (ns): 0.428 Minimum Period (ns): 18.493 Expanded Path 1 From: i_cbb/ram_cnt_inst/reg_req_addr(0):CLK To: i_cbb/ram_cnt_inst/reg_scsn_dout(22):D data required time 32.341 data arrival time - 26.500 slack 5.841 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.897 net: CLK40out 7.786 i_cbb/ram_cnt_inst/reg_req_addr(0):CLK (r) + 0.434 cell: ADLIB:DFN1C1 8.220 i_cbb/ram_cnt_inst/reg_req_addr(0):Q (r) + 3.350 net: i_cbb/ram_cnt_inst/req_addr_0_ 11.570 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14941:S (r) + 0.273 cell: ADLIB:MX2 11.843 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14941:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z45 12.092 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14939:B (r) + 0.437 cell: ADLIB:MX2 12.529 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14939:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z43 12.778 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14938:A (r) + 0.424 cell: ADLIB:MX2 13.202 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14938:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z42 13.451 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14930:B (r) + 0.437 cell: ADLIB:MX2 13.888 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14930:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z34 14.137 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14929:A (r) + 0.424 cell: ADLIB:MX2 14.561 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14929:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z33 14.810 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14897:B (r) + 0.437 cell: ADLIB:MX2 15.247 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14897:Y (r) + 1.820 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z1 17.067 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14896:A (r) + 0.424 cell: ADLIB:MX2 17.491 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14896:Y (r) + 2.483 net: i_cbb/ram_cnt_inst/dout_scsn_capt_138n1s11 19.974 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z24353:A (r) + 0.365 cell: ADLIB:NAND2 20.339 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z24353:Y (f) + 0.287 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx42135z14 20.626 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z50944:A (f) + 0.561 cell: ADLIB:NAND3A 21.187 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z50944:Y (f) + 0.897 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx42135z13 22.084 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix13116z50932:C (f) + 0.496 cell: ADLIB:NAND3C 22.580 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix13116z50932:Y (f) + 0.370 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx13116z1 22.950 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a(0)_dup_3093:A (f) + 0.401 cell: ADLIB:NAND2B 23.351 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a(0)_dup_3093:Y (f) + 0.286 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a_0__dup_3093 23.637 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_modgen_and_768_ix37148z50934:C (f) + 0.496 cell: ADLIB:NAND3C 24.133 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_modgen_and_768_ix37148z50934:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx37148z2 24.374 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/ix37148z8205:B (f) + 0.505 cell: ADLIB:AX1B 24.879 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/ix37148z8205:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/scsn_dout_i_138n1s1_47_ 25.128 i_cbb/ram_cnt_inst/ix52445z14897:B (r) + 0.437 cell: ADLIB:MX2 25.565 i_cbb/ram_cnt_inst/ix52445z14897:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/nx52445z2 25.814 i_cbb/ram_cnt_inst/scsn_dout_i(22):B (r) + 0.437 cell: ADLIB:MX2 26.251 i_cbb/ram_cnt_inst/scsn_dout_i(22):Y (r) + 0.249 net: i_cbb/ram_cnt_inst/scsn_dout_i_22_ 26.500 i_cbb/ram_cnt_inst/reg_scsn_dout(22):D (r) 26.500 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.854 net: CLK40out 32.743 i_cbb/ram_cnt_inst/reg_scsn_dout(22):CLK (r) - 0.402 Library setup time: ADLIB:DFN1 32.341 i_cbb/ram_cnt_inst/reg_scsn_dout(22):D 32.341 data required time Expanded Path 2 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D data required time 32.283 data arrival time - 26.138 slack 6.145 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.823 net: CLK40out 7.712 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.262 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):Q (f) + 1.312 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_out_0_ 9.574 i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom(0):C (f) + 0.562 cell: ADLIB:XNOR3 10.136 i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom(0):Y (r) + 1.120 net: i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom_0_ 11.256 i_cbb/scsn_inst_nw_nwl/sl1/current_state(1):A (r) + 0.705 cell: ADLIB:AX1B 11.961 i_cbb/scsn_inst_nw_nwl/sl1/current_state(1):Y (r) + 0.831 net: i_cbb/scsn_inst_nw_nwl/sl1/current_state_1_ 12.792 i_cbb/scsn_inst_nw_nwl/sl1/NOT_ix56755z24338:B (r) + 0.466 cell: ADLIB:NAND3 13.258 i_cbb/scsn_inst_nw_nwl/sl1/NOT_ix56755z24338:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/sl1/nx56755z2 13.488 i_cbb/scsn_inst_nw_nwl/sl1/request_valid:A (f) + 0.365 cell: ADLIB:AND2A 13.853 i_cbb/scsn_inst_nw_nwl/sl1/request_valid:Y (r) + 1.235 net: i_cbb/scsn_inst_nw_nwl/rq1_valid 15.088 i_cbb/scsn_inst_nw_nwl/ix4416z40556:C (r) + 0.572 cell: ADLIB:AO1B 15.660 i_cbb/scsn_inst_nw_nwl/ix4416z40556:Y (f) + 0.251 net: i_cbb/scsn_inst_nw_nwl/nx4416z1 15.911 i_cbb/scsn_inst_nw_nwl/request_valid:C (f) + 0.527 cell: ADLIB:AO1B 16.438 i_cbb/scsn_inst_nw_nwl/request_valid:Y (r) + 0.248 net: i_cbb/scsn_inst_rq_valid 16.686 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (r) + 0.365 cell: ADLIB:XAI1 17.051 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (f) + 0.250 net: i_cbb/scsn_inst_nw_apl/nx4795z6 17.301 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (f) + 0.496 cell: ADLIB:NAND3C 17.797 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (f) + 0.729 net: i_cbb/nx16212z3 18.526 i_cbb/scsn_inst_nw_apl/bridge_alter:A (f) + 0.365 cell: ADLIB:AND2A 18.891 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (r) + 0.482 net: i_cbb/scsn_inst_b_alter 19.373 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (r) + 0.491 cell: ADLIB:MX2B 19.864 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 20.105 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (f) + 0.453 cell: ADLIB:NAND3A 20.558 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.807 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (r) + 0.572 cell: ADLIB:AO1E 21.379 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (f) + 1.058 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.437 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (f) + 0.269 cell: ADLIB:NAND3B 22.706 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (r) + 0.287 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.993 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:A (r) + 0.375 cell: ADLIB:AO1C 23.368 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z5 23.598 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:A (f) + 0.388 cell: ADLIB:AO1A 23.986 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:Y (r) + 0.256 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z4 24.242 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):B (r) + 0.674 cell: ADLIB:OA1A 24.916 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):Y (r) + 0.520 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_1_ 25.436 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(3):B (r) + 0.463 cell: ADLIB:XOR3 25.899 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(3):Y (f) + 0.239 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_3_ 26.138 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D (f) 26.138 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.822 net: CLK40out 32.711 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.283 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D 32.283 data required time Expanded Path 3 From: i_cbb/ram_cnt_inst/gen_cnt_fast_2_cnt_i/reg_cout_hold:CLK To: i_cbb/ram_cnt_inst/reg_scsn_dout(22):D data required time 32.341 data arrival time - 26.055 slack 6.286 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.869 net: CLK40out 7.758 i_cbb/ram_cnt_inst/gen_cnt_fast_2_cnt_i/reg_cout_hold:CLK (r) + 0.434 cell: ADLIB:DFN1E1 8.192 i_cbb/ram_cnt_inst/gen_cnt_fast_2_cnt_i/reg_cout_hold:Q (r) + 1.355 net: i_cbb/ram_cnt_inst/cnt_fast_r_2__7_ 9.547 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14903:A (r) + 0.497 cell: ADLIB:MX2 10.044 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14903:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z7 10.293 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14901:B (r) + 0.437 cell: ADLIB:MX2 10.730 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14901:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z5 10.979 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14900:A (r) + 0.424 cell: ADLIB:MX2 11.403 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14900:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z4 11.652 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14899:A (r) + 0.424 cell: ADLIB:MX2 12.076 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14899:Y (r) + 0.754 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z3 12.830 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14898:A (r) + 0.424 cell: ADLIB:MX2 13.254 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14898:Y (r) + 1.124 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z2 14.378 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14897:A (r) + 0.424 cell: ADLIB:MX2 14.802 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14897:Y (r) + 1.820 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z1 16.622 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14896:A (r) + 0.424 cell: ADLIB:MX2 17.046 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14896:Y (r) + 2.483 net: i_cbb/ram_cnt_inst/dout_scsn_capt_138n1s11 19.529 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z24353:A (r) + 0.365 cell: ADLIB:NAND2 19.894 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z24353:Y (f) + 0.287 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx42135z14 20.181 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z50944:A (f) + 0.561 cell: ADLIB:NAND3A 20.742 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z50944:Y (f) + 0.897 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx42135z13 21.639 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix13116z50932:C (f) + 0.496 cell: ADLIB:NAND3C 22.135 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix13116z50932:Y (f) + 0.370 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx13116z1 22.505 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a(0)_dup_3093:A (f) + 0.401 cell: ADLIB:NAND2B 22.906 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a(0)_dup_3093:Y (f) + 0.286 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a_0__dup_3093 23.192 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_modgen_and_768_ix37148z50934:C (f) + 0.496 cell: ADLIB:NAND3C 23.688 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_modgen_and_768_ix37148z50934:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx37148z2 23.929 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/ix37148z8205:B (f) + 0.505 cell: ADLIB:AX1B 24.434 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/ix37148z8205:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/scsn_dout_i_138n1s1_47_ 24.683 i_cbb/ram_cnt_inst/ix52445z14897:B (r) + 0.437 cell: ADLIB:MX2 25.120 i_cbb/ram_cnt_inst/ix52445z14897:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/nx52445z2 25.369 i_cbb/ram_cnt_inst/scsn_dout_i(22):B (r) + 0.437 cell: ADLIB:MX2 25.806 i_cbb/ram_cnt_inst/scsn_dout_i(22):Y (r) + 0.249 net: i_cbb/ram_cnt_inst/scsn_dout_i_22_ 26.055 i_cbb/ram_cnt_inst/reg_scsn_dout(22):D (r) 26.055 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.854 net: CLK40out 32.743 i_cbb/ram_cnt_inst/reg_scsn_dout(22):CLK (r) - 0.402 Library setup time: ADLIB:DFN1 32.341 i_cbb/ram_cnt_inst/reg_scsn_dout(22):D 32.341 data required time Expanded Path 4 From: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D data required time 32.284 data arrival time - 25.941 slack 6.343 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.823 net: CLK40out 7.712 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.262 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(0):Q (f) + 1.312 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_out_0_ 9.574 i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom(0):C (f) + 0.562 cell: ADLIB:XNOR3 10.136 i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom(0):Y (r) + 1.120 net: i_cbb/scsn_inst_nw_nwl/sl1/NOT_h1_b0_h2_syndrom_0_ 11.256 i_cbb/scsn_inst_nw_nwl/sl1/current_state(1):A (r) + 0.705 cell: ADLIB:AX1B 11.961 i_cbb/scsn_inst_nw_nwl/sl1/current_state(1):Y (r) + 0.831 net: i_cbb/scsn_inst_nw_nwl/sl1/current_state_1_ 12.792 i_cbb/scsn_inst_nw_nwl/sl1/NOT_ix56755z24338:B (r) + 0.466 cell: ADLIB:NAND3 13.258 i_cbb/scsn_inst_nw_nwl/sl1/NOT_ix56755z24338:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/sl1/nx56755z2 13.488 i_cbb/scsn_inst_nw_nwl/sl1/request_valid:A (f) + 0.365 cell: ADLIB:AND2A 13.853 i_cbb/scsn_inst_nw_nwl/sl1/request_valid:Y (r) + 1.235 net: i_cbb/scsn_inst_nw_nwl/rq1_valid 15.088 i_cbb/scsn_inst_nw_nwl/ix4416z40556:C (r) + 0.572 cell: ADLIB:AO1B 15.660 i_cbb/scsn_inst_nw_nwl/ix4416z40556:Y (f) + 0.251 net: i_cbb/scsn_inst_nw_nwl/nx4416z1 15.911 i_cbb/scsn_inst_nw_nwl/request_valid:C (f) + 0.527 cell: ADLIB:AO1B 16.438 i_cbb/scsn_inst_nw_nwl/request_valid:Y (r) + 0.248 net: i_cbb/scsn_inst_rq_valid 16.686 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (r) + 0.365 cell: ADLIB:XAI1 17.051 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (f) + 0.250 net: i_cbb/scsn_inst_nw_apl/nx4795z6 17.301 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (f) + 0.496 cell: ADLIB:NAND3C 17.797 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (f) + 0.729 net: i_cbb/nx16212z3 18.526 i_cbb/scsn_inst_nw_apl/bridge_alter:A (f) + 0.365 cell: ADLIB:AND2A 18.891 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (r) + 0.482 net: i_cbb/scsn_inst_b_alter 19.373 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (r) + 0.491 cell: ADLIB:MX2B 19.864 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 20.105 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (f) + 0.453 cell: ADLIB:NAND3A 20.558 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.807 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (r) + 0.572 cell: ADLIB:AO1E 21.379 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (f) + 1.058 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.437 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (f) + 0.269 cell: ADLIB:NAND3B 22.706 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (r) + 0.287 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.993 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:A (r) + 0.375 cell: ADLIB:AO1C 23.368 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z5 23.598 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:A (f) + 0.388 cell: ADLIB:AO1A 23.986 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:Y (r) + 0.256 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z4 24.242 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):B (r) + 0.674 cell: ADLIB:OA1A 24.916 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):Y (r) + 0.314 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_1_ 25.230 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):B (r) + 0.463 cell: ADLIB:XOR3 25.693 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):Y (f) + 0.248 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_7_ 25.941 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D (f) 25.941 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.823 net: CLK40out 32.712 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.284 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D 32.284 data required time Expanded Path 5 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D data required time 32.284 data arrival time - 25.825 slack 6.459 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.847 net: CLK40out 7.736 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.286 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):Q (f) + 0.722 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_hm_state_out_5_ 9.008 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:A (f) + 0.365 cell: ADLIB:XOR2 9.373 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:Y (r) + 0.365 net: i_cbb/scsn_inst_nw_nwl/sl0/nx25804z1 9.738 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):B (r) + 0.463 cell: ADLIB:XOR3 10.201 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):Y (f) + 0.779 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom_1_ 10.980 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:B (f) + 0.469 cell: ADLIB:NAND2 11.449 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:Y (r) + 0.315 net: i_cbb/scsn_inst_nw_nwl/sl0/nx10686z1 11.764 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):B (r) + 0.741 cell: ADLIB:AX1D 12.505 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):Y (f) + 0.621 net: i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state_3_ 13.126 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:C (f) + 0.509 cell: ADLIB:NAND3 13.635 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:Y (r) + 0.238 net: i_cbb/scsn_inst_nw_nwl/nx44400z5 13.873 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:A (r) + 0.384 cell: ADLIB:AND2A 14.257 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:Y (f) + 1.538 net: i_cbb/scsn_inst_nw_nwl/rq0_valid 15.795 i_cbb/scsn_inst_nw_nwl/request_valid:B (f) + 0.454 cell: ADLIB:AO1B 16.249 i_cbb/scsn_inst_nw_nwl/request_valid:Y (f) + 0.243 net: i_cbb/scsn_inst_rq_valid 16.492 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (f) + 0.251 cell: ADLIB:XAI1 16.743 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (r) + 0.261 net: i_cbb/scsn_inst_nw_apl/nx4795z6 17.004 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (r) + 0.479 cell: ADLIB:NAND3C 17.483 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (r) + 0.777 net: i_cbb/nx16212z3 18.260 i_cbb/scsn_inst_nw_apl/bridge_alter:A (r) + 0.384 cell: ADLIB:AND2A 18.644 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (f) + 0.441 net: i_cbb/scsn_inst_b_alter 19.085 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (f) + 0.496 cell: ADLIB:MX2B 19.581 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 19.830 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (r) + 0.466 cell: ADLIB:NAND3A 20.296 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.537 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (f) + 0.526 cell: ADLIB:AO1E 21.063 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (r) + 1.101 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.164 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (r) + 0.365 cell: ADLIB:NAND3B 22.529 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (f) + 0.281 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.810 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z43529:C (f) + 0.393 cell: ADLIB:XO1A 23.203 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z43529:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z4 23.444 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z40556:B (f) + 0.454 cell: ADLIB:AO1B 23.898 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z40556:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z1 24.139 i_cbb/scsn_inst_nw_nwl/sl1/next_state(2):A (f) + 0.735 cell: ADLIB:OA1A 24.874 i_cbb/scsn_inst_nw_nwl/sl1/next_state(2):Y (r) + 0.406 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_2_ 25.280 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):A (r) + 0.297 cell: ADLIB:XOR3 25.577 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):Y (f) + 0.248 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_7_ 25.825 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D (f) 25.825 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.823 net: CLK40out 32.712 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.284 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D 32.284 data required time Expanded Path 6 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D data required time 32.283 data arrival time - 25.820 slack 6.463 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.847 net: CLK40out 7.736 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.286 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):Q (f) + 0.722 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_hm_state_out_5_ 9.008 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:A (f) + 0.365 cell: ADLIB:XOR2 9.373 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:Y (r) + 0.365 net: i_cbb/scsn_inst_nw_nwl/sl0/nx25804z1 9.738 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):B (r) + 0.463 cell: ADLIB:XOR3 10.201 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):Y (f) + 0.779 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom_1_ 10.980 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:B (f) + 0.469 cell: ADLIB:NAND2 11.449 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:Y (r) + 0.315 net: i_cbb/scsn_inst_nw_nwl/sl0/nx10686z1 11.764 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):B (r) + 0.482 cell: ADLIB:AX1D 12.246 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):Y (r) + 0.670 net: i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state_3_ 12.916 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:C (r) + 0.561 cell: ADLIB:NAND3 13.477 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/nx44400z5 13.707 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:A (f) + 0.365 cell: ADLIB:AND2A 14.072 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:Y (r) + 1.634 net: i_cbb/scsn_inst_nw_nwl/rq0_valid 15.706 i_cbb/scsn_inst_nw_nwl/request_valid:B (r) + 0.414 cell: ADLIB:AO1B 16.120 i_cbb/scsn_inst_nw_nwl/request_valid:Y (r) + 0.248 net: i_cbb/scsn_inst_rq_valid 16.368 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (r) + 0.365 cell: ADLIB:XAI1 16.733 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (f) + 0.250 net: i_cbb/scsn_inst_nw_apl/nx4795z6 16.983 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (f) + 0.496 cell: ADLIB:NAND3C 17.479 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (f) + 0.729 net: i_cbb/nx16212z3 18.208 i_cbb/scsn_inst_nw_apl/bridge_alter:A (f) + 0.365 cell: ADLIB:AND2A 18.573 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (r) + 0.482 net: i_cbb/scsn_inst_b_alter 19.055 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (r) + 0.491 cell: ADLIB:MX2B 19.546 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 19.787 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (f) + 0.453 cell: ADLIB:NAND3A 20.240 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.489 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (r) + 0.572 cell: ADLIB:AO1E 21.061 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (f) + 1.058 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.119 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (f) + 0.269 cell: ADLIB:NAND3B 22.388 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (r) + 0.287 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.675 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:A (r) + 0.375 cell: ADLIB:AO1C 23.050 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z5 23.280 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:A (f) + 0.388 cell: ADLIB:AO1A 23.668 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:Y (r) + 0.256 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z4 23.924 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):B (r) + 0.674 cell: ADLIB:OA1A 24.598 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):Y (r) + 0.520 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_1_ 25.118 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(3):B (r) + 0.463 cell: ADLIB:XOR3 25.581 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(3):Y (f) + 0.239 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_3_ 25.820 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D (f) 25.820 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.822 net: CLK40out 32.711 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.283 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D 32.283 data required time Expanded Path 7 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D data required time 32.283 data arrival time - 25.819 slack 6.464 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.847 net: CLK40out 7.736 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.286 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):Q (f) + 0.342 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_hm_state_out_6_ 8.628 i_cbb/scsn_inst_nw_nwl/sl0/ix25761z10876:B (f) + 0.700 cell: ADLIB:XOR2 9.328 i_cbb/scsn_inst_nw_nwl/sl0/ix25761z10876:Y (r) + 0.238 net: i_cbb/scsn_inst_nw_nwl/sl0/nx25761z1 9.566 i_cbb/scsn_inst_nw_nwl/sl0/NOT_h1_b0_h2_syndrom(0):A (r) + 0.257 cell: ADLIB:XNOR3 9.823 i_cbb/scsn_inst_nw_nwl/sl0/NOT_h1_b0_h2_syndrom(0):Y (r) + 1.228 net: i_cbb/scsn_inst_nw_nwl/sl0/NOT_h1_b0_h2_syndrom_0_ 11.051 i_cbb/scsn_inst_nw_nwl/sl0/current_state(1):A (r) + 0.705 cell: ADLIB:AX1B 11.756 i_cbb/scsn_inst_nw_nwl/sl0/current_state(1):Y (r) + 1.254 net: i_cbb/scsn_inst_nw_nwl/sl0/current_state_1_ 13.010 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:B (r) + 0.466 cell: ADLIB:NAND3 13.476 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/nx44400z5 13.706 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:A (f) + 0.365 cell: ADLIB:AND2A 14.071 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:Y (r) + 1.634 net: i_cbb/scsn_inst_nw_nwl/rq0_valid 15.705 i_cbb/scsn_inst_nw_nwl/request_valid:B (r) + 0.414 cell: ADLIB:AO1B 16.119 i_cbb/scsn_inst_nw_nwl/request_valid:Y (r) + 0.248 net: i_cbb/scsn_inst_rq_valid 16.367 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (r) + 0.365 cell: ADLIB:XAI1 16.732 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (f) + 0.250 net: i_cbb/scsn_inst_nw_apl/nx4795z6 16.982 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (f) + 0.496 cell: ADLIB:NAND3C 17.478 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (f) + 0.729 net: i_cbb/nx16212z3 18.207 i_cbb/scsn_inst_nw_apl/bridge_alter:A (f) + 0.365 cell: ADLIB:AND2A 18.572 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (r) + 0.482 net: i_cbb/scsn_inst_b_alter 19.054 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (r) + 0.491 cell: ADLIB:MX2B 19.545 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 19.786 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (f) + 0.453 cell: ADLIB:NAND3A 20.239 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.488 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (r) + 0.572 cell: ADLIB:AO1E 21.060 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (f) + 1.058 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.118 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (f) + 0.269 cell: ADLIB:NAND3B 22.387 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (r) + 0.287 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.674 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:A (r) + 0.375 cell: ADLIB:AO1C 23.049 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40562:Y (f) + 0.230 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z5 23.279 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:A (f) + 0.388 cell: ADLIB:AO1A 23.667 i_cbb/scsn_inst_nw_nwl/sl1/ix4795z40559:Y (r) + 0.256 net: i_cbb/scsn_inst_nw_nwl/sl1/nx4795z4 23.923 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):B (r) + 0.674 cell: ADLIB:OA1A 24.597 i_cbb/scsn_inst_nw_nwl/sl1/next_state(1):Y (r) + 0.520 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_1_ 25.117 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(3):B (r) + 0.463 cell: ADLIB:XOR3 25.580 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(3):Y (f) + 0.239 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_3_ 25.819 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D (f) 25.819 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.822 net: CLK40out 32.711 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.283 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(3):D 32.283 data required time Expanded Path 8 From: i_cbb/ram_cnt_inst/gen_cnt_fast_1_cnt_i_reg_cout_hold:CLK To: i_cbb/ram_cnt_inst/reg_scsn_dout(22):D data required time 32.341 data arrival time - 25.872 slack 6.469 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.869 net: CLK40out 7.758 i_cbb/ram_cnt_inst/gen_cnt_fast_1_cnt_i_reg_cout_hold:CLK (r) + 0.434 cell: ADLIB:DFN1E1 8.192 i_cbb/ram_cnt_inst/gen_cnt_fast_1_cnt_i_reg_cout_hold:Q (r) + 1.176 net: i_cbb/ram_cnt_inst/cnt_fast_r_1__7_ 9.368 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14902:B (r) + 0.506 cell: ADLIB:MX2 9.874 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14902:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z6 10.123 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14901:A (r) + 0.424 cell: ADLIB:MX2 10.547 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14901:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z5 10.796 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14900:A (r) + 0.424 cell: ADLIB:MX2 11.220 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14900:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z4 11.469 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14899:A (r) + 0.424 cell: ADLIB:MX2 11.893 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14899:Y (r) + 0.754 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z3 12.647 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14898:A (r) + 0.424 cell: ADLIB:MX2 13.071 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14898:Y (r) + 1.124 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z2 14.195 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14897:A (r) + 0.424 cell: ADLIB:MX2 14.619 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14897:Y (r) + 1.820 net: i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/nx100z1 16.439 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14896:A (r) + 0.424 cell: ADLIB:MX2 16.863 i_cbb/ram_cnt_inst/dout_scsn_capt_mux_138i1/ix100z14896:Y (r) + 2.483 net: i_cbb/ram_cnt_inst/dout_scsn_capt_138n1s11 19.346 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z24353:A (r) + 0.365 cell: ADLIB:NAND2 19.711 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z24353:Y (f) + 0.287 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx42135z14 19.998 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z50944:A (f) + 0.561 cell: ADLIB:NAND3A 20.559 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix42135z50944:Y (f) + 0.897 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx42135z13 21.456 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix13116z50932:C (f) + 0.496 cell: ADLIB:NAND3C 21.952 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_ix13116z50932:Y (f) + 0.370 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx13116z1 22.322 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a(0)_dup_3093:A (f) + 0.401 cell: ADLIB:NAND2B 22.723 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a(0)_dup_3093:Y (f) + 0.286 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_a_0__dup_3093 23.009 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_modgen_and_768_ix37148z50934:C (f) + 0.496 cell: ADLIB:NAND3C 23.505 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/NOT_modgen_and_768_ix37148z50934:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/nx37148z2 23.746 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/ix37148z8205:B (f) + 0.505 cell: ADLIB:AX1B 24.251 i_cbb/ram_cnt_inst/scsn_dout_i_inc54_138i2/ix37148z8205:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/scsn_dout_i_138n1s1_47_ 24.500 i_cbb/ram_cnt_inst/ix52445z14897:B (r) + 0.437 cell: ADLIB:MX2 24.937 i_cbb/ram_cnt_inst/ix52445z14897:Y (r) + 0.249 net: i_cbb/ram_cnt_inst/nx52445z2 25.186 i_cbb/ram_cnt_inst/scsn_dout_i(22):B (r) + 0.437 cell: ADLIB:MX2 25.623 i_cbb/ram_cnt_inst/scsn_dout_i(22):Y (r) + 0.249 net: i_cbb/ram_cnt_inst/scsn_dout_i_22_ 25.872 i_cbb/ram_cnt_inst/reg_scsn_dout(22):D (r) 25.872 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.854 net: CLK40out 32.743 i_cbb/ram_cnt_inst/reg_scsn_dout(22):CLK (r) - 0.402 Library setup time: ADLIB:DFN1 32.341 i_cbb/ram_cnt_inst/reg_scsn_dout(22):D 32.341 data required time Expanded Path 9 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(1):D data required time 32.283 data arrival time - 25.806 slack 6.477 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.847 net: CLK40out 7.736 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.286 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(5):Q (f) + 0.722 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_hm_state_out_5_ 9.008 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:A (f) + 0.365 cell: ADLIB:XOR2 9.373 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:Y (r) + 0.365 net: i_cbb/scsn_inst_nw_nwl/sl0/nx25804z1 9.738 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):B (r) + 0.463 cell: ADLIB:XOR3 10.201 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):Y (f) + 0.779 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom_1_ 10.980 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:B (f) + 0.469 cell: ADLIB:NAND2 11.449 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:Y (r) + 0.315 net: i_cbb/scsn_inst_nw_nwl/sl0/nx10686z1 11.764 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):B (r) + 0.741 cell: ADLIB:AX1D 12.505 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):Y (f) + 0.621 net: i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state_3_ 13.126 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:C (f) + 0.509 cell: ADLIB:NAND3 13.635 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:Y (r) + 0.238 net: i_cbb/scsn_inst_nw_nwl/nx44400z5 13.873 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:A (r) + 0.384 cell: ADLIB:AND2A 14.257 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:Y (f) + 1.538 net: i_cbb/scsn_inst_nw_nwl/rq0_valid 15.795 i_cbb/scsn_inst_nw_nwl/request_valid:B (f) + 0.454 cell: ADLIB:AO1B 16.249 i_cbb/scsn_inst_nw_nwl/request_valid:Y (f) + 0.243 net: i_cbb/scsn_inst_rq_valid 16.492 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (f) + 0.251 cell: ADLIB:XAI1 16.743 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (r) + 0.261 net: i_cbb/scsn_inst_nw_apl/nx4795z6 17.004 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (r) + 0.479 cell: ADLIB:NAND3C 17.483 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (r) + 0.777 net: i_cbb/nx16212z3 18.260 i_cbb/scsn_inst_nw_apl/bridge_alter:A (r) + 0.384 cell: ADLIB:AND2A 18.644 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (f) + 0.441 net: i_cbb/scsn_inst_b_alter 19.085 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (f) + 0.496 cell: ADLIB:MX2B 19.581 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 19.830 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (r) + 0.466 cell: ADLIB:NAND3A 20.296 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.537 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (f) + 0.526 cell: ADLIB:AO1E 21.063 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (r) + 1.101 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.164 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (r) + 0.365 cell: ADLIB:NAND3B 22.529 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (f) + 0.281 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.810 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z43529:C (f) + 0.393 cell: ADLIB:XO1A 23.203 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z43529:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z4 23.444 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z40556:B (f) + 0.454 cell: ADLIB:AO1B 23.898 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z40556:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z1 24.139 i_cbb/scsn_inst_nw_nwl/sl1/next_state(2):A (f) + 0.735 cell: ADLIB:OA1A 24.874 i_cbb/scsn_inst_nw_nwl/sl1/next_state(2):Y (r) + 0.394 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_2_ 25.268 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(1):A (r) + 0.297 cell: ADLIB:XOR3 25.565 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(1):Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_1_ 25.806 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(1):D (f) 25.806 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.822 net: CLK40out 32.711 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.283 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(1):D 32.283 data required time Expanded Path 10 From: i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):CLK To: i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D data required time 32.284 data arrival time - 25.777 slack 6.507 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.847 net: CLK40out 7.736 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.286 i_cbb/scsn_inst_nw_nwl/sl0/h1_reg_hm_state_out(6):Q (f) + 0.339 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_hm_state_out_6_ 8.625 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:B (f) + 0.700 cell: ADLIB:XOR2 9.325 i_cbb/scsn_inst_nw_nwl/sl0/ix25804z10876:Y (r) + 0.365 net: i_cbb/scsn_inst_nw_nwl/sl0/nx25804z1 9.690 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):B (r) + 0.463 cell: ADLIB:XOR3 10.153 i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom(1):Y (f) + 0.779 net: i_cbb/scsn_inst_nw_nwl/sl0/h1_b0_h2_syndrom_1_ 10.932 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:B (f) + 0.469 cell: ADLIB:NAND2 11.401 i_cbb/scsn_inst_nw_nwl/sl0/ix10686z24338:Y (r) + 0.315 net: i_cbb/scsn_inst_nw_nwl/sl0/nx10686z1 11.716 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):B (r) + 0.741 cell: ADLIB:AX1D 12.457 i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state(3):Y (f) + 0.621 net: i_cbb/scsn_inst_nw_nwl/sl0/NOT_current_state_3_ 13.078 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:C (f) + 0.509 cell: ADLIB:NAND3 13.587 i_cbb/scsn_inst_nw_nwl/sl0/NOT_ix56755z24338:Y (r) + 0.238 net: i_cbb/scsn_inst_nw_nwl/nx44400z5 13.825 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:A (r) + 0.384 cell: ADLIB:AND2A 14.209 i_cbb/scsn_inst_nw_nwl/sl0/request_valid:Y (f) + 1.538 net: i_cbb/scsn_inst_nw_nwl/rq0_valid 15.747 i_cbb/scsn_inst_nw_nwl/request_valid:B (f) + 0.454 cell: ADLIB:AO1B 16.201 i_cbb/scsn_inst_nw_nwl/request_valid:Y (f) + 0.243 net: i_cbb/scsn_inst_rq_valid 16.444 i_cbb/scsn_inst_nw_apl/ix4795z44949:C (f) + 0.251 cell: ADLIB:XAI1 16.695 i_cbb/scsn_inst_nw_apl/ix4795z44949:Y (r) + 0.261 net: i_cbb/scsn_inst_nw_apl/nx4795z6 16.956 i_cbb/scsn_inst_nw_apl/ix4795z50946:C (r) + 0.479 cell: ADLIB:NAND3C 17.435 i_cbb/scsn_inst_nw_apl/ix4795z50946:Y (r) + 0.777 net: i_cbb/nx16212z3 18.212 i_cbb/scsn_inst_nw_apl/bridge_alter:A (r) + 0.384 cell: ADLIB:AND2A 18.596 i_cbb/scsn_inst_nw_apl/bridge_alter:Y (f) + 0.441 net: i_cbb/scsn_inst_b_alter 19.037 i_cbb/scsn_inst_nw_nwl/ix51108z26295:B (f) + 0.496 cell: ADLIB:MX2B 19.533 i_cbb/scsn_inst_nw_nwl/ix51108z26295:Y (r) + 0.249 net: i_cbb/scsn_inst_nw_nwl/nx51108z4 19.782 i_cbb/scsn_inst_nw_nwl/ix51108z50932:C (r) + 0.466 cell: ADLIB:NAND3A 20.248 i_cbb/scsn_inst_nw_nwl/ix51108z50932:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/nx51108z3 20.489 i_cbb/scsn_inst_nw_nwl/reply1_valid:C (f) + 0.526 cell: ADLIB:AO1E 21.015 i_cbb/scsn_inst_nw_nwl/reply1_valid:Y (r) + 1.101 net: i_cbb/scsn_inst_nw_nwl/reply1_valid 22.116 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:C (r) + 0.365 cell: ADLIB:NAND3B 22.481 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z50935:Y (f) + 0.281 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z5 22.762 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z43529:C (f) + 0.393 cell: ADLIB:XO1A 23.155 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z43529:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z4 23.396 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z40556:B (f) + 0.454 cell: ADLIB:AO1B 23.850 i_cbb/scsn_inst_nw_nwl/sl1/ix3798z40556:Y (f) + 0.241 net: i_cbb/scsn_inst_nw_nwl/sl1/nx3798z1 24.091 i_cbb/scsn_inst_nw_nwl/sl1/next_state(2):A (f) + 0.735 cell: ADLIB:OA1A 24.826 i_cbb/scsn_inst_nw_nwl/sl1/next_state(2):Y (r) + 0.406 net: i_cbb/scsn_inst_nw_nwl/sl1/next_state_2_ 25.232 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):A (r) + 0.297 cell: ADLIB:XOR3 25.529 i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in(7):Y (f) + 0.248 net: i_cbb/scsn_inst_nw_nwl/sl1/h1_hm_state_in_7_ 25.777 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D (f) 25.777 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.823 net: CLK40out 32.712 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 32.284 i_cbb/scsn_inst_nw_nwl/sl1/h1_reg_hm_state_out(7):D 32.284 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_hold(4):D Delay (ns): 12.089 Slack (ns): Arrival (ns): 12.089 Required (ns): Setup (ns): 0.402 External Setup (ns): 4.729 Path 2 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_curr_i(4):D Delay (ns): 11.127 Slack (ns): Arrival (ns): 11.127 Required (ns): Setup (ns): 0.428 External Setup (ns): 3.823 Path 3 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_hold:D Delay (ns): 10.997 Slack (ns): Arrival (ns): 10.997 Required (ns): Setup (ns): 0.402 External Setup (ns): 3.641 Path 4 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_i:D Delay (ns): 10.737 Slack (ns): Arrival (ns): 10.737 Required (ns): Setup (ns): 0.402 External Setup (ns): 3.371 Path 5 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D Delay (ns): 10.664 Slack (ns): Arrival (ns): 10.664 Required (ns): Setup (ns): 0.428 External Setup (ns): 3.330 Path 6 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D Delay (ns): 10.663 Slack (ns): Arrival (ns): 10.663 Required (ns): Setup (ns): 0.428 External Setup (ns): 3.329 Path 7 From: L1ACCEPTp To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D Delay (ns): 10.635 Slack (ns): Arrival (ns): 10.635 Required (ns): Setup (ns): 0.428 External Setup (ns): 3.301 Path 8 From: L1ACCEPTp To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D Delay (ns): 10.634 Slack (ns): Arrival (ns): 10.634 Required (ns): Setup (ns): 0.428 External Setup (ns): 3.300 Path 9 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(3):D Delay (ns): 10.051 Slack (ns): Arrival (ns): 10.051 Required (ns): Setup (ns): 0.402 External Setup (ns): 2.715 Path 10 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(3):D Delay (ns): 10.053 Slack (ns): Arrival (ns): 10.053 Required (ns): Setup (ns): 0.402 External Setup (ns): 2.691 Expanded Path 1 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_hold(4):D data required time N/C data arrival time - 12.089 slack N/C ________________________________________________________ Data arrival time calculation 0.000 B_Channel (r) + 0.000 net: B_Channel 0.000 ibuf_b_channel_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_b_channel_ib/U0/U0:Y (r) + 0.000 net: ibuf_b_channel_ib/U0/NET1 0.898 ibuf_b_channel_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_b_channel_ib/U0/U1:Y (r) + 7.138 net: B_Channel_i 8.068 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z50933:C (r) + 0.534 cell: ADLIB:NAND3A 8.602 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z50933:Y (f) + 0.239 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/nx19627z4 8.841 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z40558:C (f) + 0.527 cell: ADLIB:AO1D 9.368 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z40558:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/nx19627z1 9.609 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_2n1ss1(4):A (f) + 0.535 cell: ADLIB:AX1 10.144 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_2n1ss1(4):Y (r) + 0.249 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_2n1ss1_4_ 10.393 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix64606z2957:C (r) + 0.496 cell: ADLIB:AND3B 10.889 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix64606z2957:Y (r) + 1.200 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_4_ 12.089 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_hold(4):D (r) 12.089 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.873 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_hold(4):CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_hold(4):D Expanded Path 2 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_curr_i(4):D data required time N/C data arrival time - 11.127 slack N/C ________________________________________________________ Data arrival time calculation 0.000 B_Channel (r) + 0.000 net: B_Channel 0.000 ibuf_b_channel_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_b_channel_ib/U0/U0:Y (r) + 0.000 net: ibuf_b_channel_ib/U0/NET1 0.898 ibuf_b_channel_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_b_channel_ib/U0/U1:Y (r) + 7.138 net: B_Channel_i 8.068 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z50933:C (r) + 0.534 cell: ADLIB:NAND3A 8.602 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z50933:Y (f) + 0.239 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/nx19627z4 8.841 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z40558:C (f) + 0.527 cell: ADLIB:AO1D 9.368 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix19627z40558:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/nx19627z1 9.609 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_2n1ss1(4):A (f) + 0.559 cell: ADLIB:AX1 10.168 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_2n1ss1(4):Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_2n1ss1_4_ 10.409 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix64606z2957:C (f) + 0.479 cell: ADLIB:AND3B 10.888 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix64606z2957:Y (f) + 0.239 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/q_next_4_ 11.127 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_curr_i(4):D (f) 11.127 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.843 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_curr_i(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_q_curr_i(4):D Expanded Path 3 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_hold:D data required time N/C data arrival time - 10.997 slack N/C ________________________________________________________ Data arrival time calculation 0.000 B_Channel (r) + 0.000 net: B_Channel 0.000 ibuf_b_channel_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_b_channel_ib/U0/U0:Y (r) + 0.000 net: ibuf_b_channel_ib/U0/NET1 0.898 ibuf_b_channel_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_b_channel_ib/U0/U1:Y (r) + 7.149 net: B_Channel_i 8.079 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix6763z50930:C (r) + 0.534 cell: ADLIB:NAND3A 8.613 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix6763z50930:Y (f) + 0.244 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/nx6763z1 8.857 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/cout_next:A (f) + 0.672 cell: ADLIB:AOI1 9.529 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/cout_next:Y (r) + 1.468 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/cout_next 10.997 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_hold:D (r) 10.997 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.869 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_hold:CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_hold:D Expanded Path 4 From: B_Channel To: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_i:D data required time N/C data arrival time - 10.737 slack N/C ________________________________________________________ Data arrival time calculation 0.000 B_Channel (r) + 0.000 net: B_Channel 0.000 ibuf_b_channel_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_b_channel_ib/U0/U0:Y (r) + 0.000 net: ibuf_b_channel_ib/U0/NET1 0.898 ibuf_b_channel_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_b_channel_ib/U0/U1:Y (r) + 7.149 net: B_Channel_i 8.079 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix6763z50930:C (r) + 0.534 cell: ADLIB:NAND3A 8.613 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/ix6763z50930:Y (f) + 0.244 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/nx6763z1 8.857 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/cout_next:A (f) + 0.672 cell: ADLIB:AOI1 9.529 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/cout_next:Y (r) + 1.208 net: i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/cout_next 10.737 i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_i:D (r) 10.737 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.879 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_i:CLK (r) - 0.402 Library setup time: ADLIB:DFN1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_7_cnt_i/reg_cout_i:D Expanded Path 5 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D data required time N/C data arrival time - 10.664 slack N/C ________________________________________________________ Data arrival time calculation 0.000 L1ACCEPTn (r) + 0.000 net: L1ACCEPTn 0.000 lvds_L1A_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_L1A_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_L1A_U1/U0/U2_N2P 0.000 lvds_L1A_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_L1A_U1/U0/U0:Y (r) + 0.000 net: lvds_L1A_U1/U0/NET1 1.421 lvds_L1A_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_L1A_U1/U0/U1:Y (r) + 6.103 net: L1ACCEPT_i 7.556 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:C (r) + 0.534 cell: ADLIB:NAND3A 8.090 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z4 8.331 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:C (f) + 0.527 cell: ADLIB:AO1D 8.858 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z1 9.099 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):A (f) + 0.559 cell: ADLIB:AX1 9.658 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1_4_ 9.899 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:C (f) + 0.479 cell: ADLIB:AND3B 10.378 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:Y (f) + 0.286 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_4_ 10.664 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D (f) 10.664 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.873 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D Expanded Path 6 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D data required time N/C data arrival time - 10.663 slack N/C ________________________________________________________ Data arrival time calculation 0.000 L1ACCEPTn (r) + 0.000 net: L1ACCEPTn 0.000 lvds_L1A_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_L1A_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_L1A_U1/U0/U2_N2P 0.000 lvds_L1A_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_L1A_U1/U0/U0:Y (r) + 0.000 net: lvds_L1A_U1/U0/NET1 1.421 lvds_L1A_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_L1A_U1/U0/U1:Y (r) + 6.103 net: L1ACCEPT_i 7.556 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:C (r) + 0.534 cell: ADLIB:NAND3A 8.090 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z4 8.331 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:C (f) + 0.527 cell: ADLIB:AO1D 8.858 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z1 9.099 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):A (f) + 0.559 cell: ADLIB:AX1 9.658 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1_4_ 9.899 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:C (f) + 0.479 cell: ADLIB:AND3B 10.378 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:Y (f) + 0.285 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_4_ 10.663 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D (f) 10.663 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.873 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1E1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D Expanded Path 7 From: L1ACCEPTp To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D data required time N/C data arrival time - 10.635 slack N/C ________________________________________________________ Data arrival time calculation 0.000 L1ACCEPTp (r) + 0.000 net: L1ACCEPTp 0.000 lvds_L1A_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_L1A_U1/U0/U0:Y (r) + 0.000 net: lvds_L1A_U1/U0/NET1 1.392 lvds_L1A_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_L1A_U1/U0/U1:Y (r) + 6.103 net: L1ACCEPT_i 7.527 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:C (r) + 0.534 cell: ADLIB:NAND3A 8.061 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z4 8.302 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:C (f) + 0.527 cell: ADLIB:AO1D 8.829 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z1 9.070 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):A (f) + 0.559 cell: ADLIB:AX1 9.629 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1_4_ 9.870 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:C (f) + 0.479 cell: ADLIB:AND3B 10.349 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:Y (f) + 0.286 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_4_ 10.635 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D (f) 10.635 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.873 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(4):D Expanded Path 8 From: L1ACCEPTp To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D data required time N/C data arrival time - 10.634 slack N/C ________________________________________________________ Data arrival time calculation 0.000 L1ACCEPTp (r) + 0.000 net: L1ACCEPTp 0.000 lvds_L1A_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_L1A_U1/U0/U0:Y (r) + 0.000 net: lvds_L1A_U1/U0/NET1 1.392 lvds_L1A_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_L1A_U1/U0/U1:Y (r) + 6.103 net: L1ACCEPT_i 7.527 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:C (r) + 0.534 cell: ADLIB:NAND3A 8.061 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z50933:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z4 8.302 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:C (f) + 0.527 cell: ADLIB:AO1D 8.829 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix19627z40558:Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx19627z1 9.070 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):A (f) + 0.559 cell: ADLIB:AX1 9.629 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1(4):Y (f) + 0.241 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_2n1ss1_4_ 9.870 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:C (f) + 0.479 cell: ADLIB:AND3B 10.349 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix64606z2957:Y (f) + 0.285 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/q_next_4_ 10.634 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D (f) 10.634 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.873 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1E1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(4):D Expanded Path 9 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(3):D data required time N/C data arrival time - 10.051 slack N/C ________________________________________________________ Data arrival time calculation 0.000 L1ACCEPTn (r) + 0.000 net: L1ACCEPTn 0.000 lvds_L1A_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_L1A_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_L1A_U1/U0/U2_N2P 0.000 lvds_L1A_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_L1A_U1/U0/U0:Y (r) + 0.000 net: lvds_L1A_U1/U0/NET1 1.421 lvds_L1A_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_L1A_U1/U0/U1:Y (r) + 5.712 net: L1ACCEPT_i 7.165 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix52494z24339:A (r) + 0.304 cell: ADLIB:NAND2 7.469 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix52494z24339:Y (f) + 1.024 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx52494z2 8.493 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z50932:B (f) + 0.534 cell: ADLIB:NAND3B 9.027 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z50932:Y (f) + 0.244 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx67z2 9.271 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z21034:B (f) + 0.476 cell: ADLIB:XA1C 9.747 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z21034:Y (r) + 0.304 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx67z1 10.051 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(3):D (r) 10.051 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.849 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(3):CLK (r) - 0.402 Library setup time: ADLIB:DFN1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_curr_i(3):D Expanded Path 10 From: L1ACCEPTn To: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(3):D data required time N/C data arrival time - 10.053 slack N/C ________________________________________________________ Data arrival time calculation 0.000 L1ACCEPTn (r) + 0.000 net: L1ACCEPTn 0.000 lvds_L1A_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 lvds_L1A_U1/U0/U2:N2POUT (r) + 0.000 net: lvds_L1A_U1/U0/U2_N2P 0.000 lvds_L1A_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 lvds_L1A_U1/U0/U0:Y (r) + 0.000 net: lvds_L1A_U1/U0/NET1 1.421 lvds_L1A_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 lvds_L1A_U1/U0/U1:Y (r) + 5.712 net: L1ACCEPT_i 7.165 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix52494z24339:A (r) + 0.304 cell: ADLIB:NAND2 7.469 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix52494z24339:Y (f) + 1.024 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx52494z2 8.493 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z50932:B (f) + 0.534 cell: ADLIB:NAND3B 9.027 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z50932:Y (f) + 0.244 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx67z2 9.271 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z21034:B (f) + 0.476 cell: ADLIB:XA1C 9.747 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/ix67z21034:Y (r) + 0.306 net: i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/nx67z1 10.053 i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(3):D (r) 10.053 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.875 net: CLK40out N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(3):CLK (r) - 0.402 Library setup time: ADLIB:DFN1E1 N/C i_cbb/ram_cnt_inst/gen_cnt_fast_6_cnt_i/reg_q_hold(3):D END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: RESET_TOFFPGA Delay (ns): 11.809 Slack (ns): Arrival (ns): 19.544 Required (ns): Clock to Out (ns): 19.544 Path 2 From: i_cbb/sys_config0/reg_cbb_ctrl_i(1):CLK To: RESET_TOFFPGA Delay (ns): 10.669 Slack (ns): Arrival (ns): 18.416 Required (ns): Clock to Out (ns): 18.416 Path 3 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: CNRRL Delay (ns): 8.699 Slack (ns): Arrival (ns): 16.446 Required (ns): Clock to Out (ns): 16.446 Path 4 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA Delay (ns): 8.632 Slack (ns): Arrival (ns): 16.381 Required (ns): Clock to Out (ns): 16.381 Path 5 From: i_adc/sfp_rd_reg_SFP_SDA_o_i:CLK To: SIU_SDA Delay (ns): 8.379 Slack (ns): Arrival (ns): 16.128 Required (ns): Clock to Out (ns): 16.128 Path 6 From: i_adc/sfp_rd_reg_SFP_SCL_i:CLK To: SIU_SCL Delay (ns): 8.360 Slack (ns): Arrival (ns): 16.094 Required (ns): Clock to Out (ns): 16.094 Path 7 From: i_adc/adc/adci/reg_addr(4):CLK To: ADC_SDI Delay (ns): 8.142 Slack (ns): Arrival (ns): 15.889 Required (ns): Clock to Out (ns): 15.889 Path 8 From: i_adc/scsn_slv_nw_nwl/reg_bridged:CLK To: SCSNOUTn Delay (ns): 7.821 Slack (ns): Arrival (ns): 15.519 Required (ns): Clock to Out (ns): 15.519 Path 9 From: i_adc/scsn_slv_nw_nwl/reg_bridged:CLK To: SCSNOUTp Delay (ns): 7.821 Slack (ns): Arrival (ns): 15.519 Required (ns): Clock to Out (ns): 15.519 Path 10 From: i_cbb/ttcex_out_inst_reg_a_channel_out:CLK To: A_ECL Delay (ns): 7.149 Slack (ns): Arrival (ns): 14.864 Required (ns): Clock to Out (ns): 14.864 Expanded Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: RESET_TOFFPGA data required time N/C data arrival time - 19.544 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 4.061 net: i_cbb/rst_scsn 12.346 i_cbb/ix26613z10876:B (f) + 0.737 cell: ADLIB:XOR2 13.083 i_cbb/ix26613z10876:Y (f) + 1.470 net: RST2FPGA_i 14.553 obuf_RST2FPGA_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 15.045 obuf_RST2FPGA_U1/U0/U1:DOUT (f) + 0.000 net: obuf_RST2FPGA_U1/U0/NET1 15.045 obuf_RST2FPGA_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 19.544 obuf_RST2FPGA_U1/U0/U0:PAD (f) + 0.000 net: RESET_TOFFPGA 19.544 RESET_TOFFPGA (f) 19.544 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C RESET_TOFFPGA (f) Expanded Path 2 From: i_cbb/sys_config0/reg_cbb_ctrl_i(1):CLK To: RESET_TOFFPGA data required time N/C data arrival time - 18.416 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.858 net: CLK40out 7.747 i_cbb/sys_config0/reg_cbb_ctrl_i(1):CLK (r) + 0.550 cell: ADLIB:DFN1E1 8.297 i_cbb/sys_config0/reg_cbb_ctrl_i(1):Q (f) + 3.267 net: i_cbb/cbb_ctrl_1_ 11.564 i_cbb/ix26613z10876:A (f) + 0.391 cell: ADLIB:XOR2 11.955 i_cbb/ix26613z10876:Y (f) + 1.470 net: RST2FPGA_i 13.425 obuf_RST2FPGA_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 13.917 obuf_RST2FPGA_U1/U0/U1:DOUT (f) + 0.000 net: obuf_RST2FPGA_U1/U0/NET1 13.917 obuf_RST2FPGA_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 18.416 obuf_RST2FPGA_U1/U0/U0:PAD (f) + 0.000 net: RESET_TOFFPGA 18.416 RESET_TOFFPGA (f) 18.416 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C RESET_TOFFPGA (f) Expanded Path 3 From: i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK To: CNRRL data required time N/C data arrival time - 16.446 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.858 net: CLK40out 7.747 i_cbb/sys_config0/reg_cbb_ctrl_i(0):CLK (r) + 0.550 cell: ADLIB:DFN1E1 8.297 i_cbb/sys_config0/reg_cbb_ctrl_i(0):Q (f) + 3.215 net: CNRRL_i 11.512 obuf_CNRRL_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 11.947 obuf_CNRRL_U1/U0/U1:DOUT (f) + 0.000 net: obuf_CNRRL_U1/U0/NET1 11.947 obuf_CNRRL_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 16.446 obuf_CNRRL_U1/U0/U0:PAD (f) + 0.000 net: CNRRL 16.446 CNRRL (f) 16.446 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C CNRRL (f) Expanded Path 4 From: i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK To: SIU_SDA data required time N/C data arrival time - 16.381 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.860 net: CLK40out 7.749 i_adc/sfp_rd_reg_SFP_SDA_e_i:CLK (r) + 0.434 cell: ADLIB:DFN1C1 8.183 i_adc/sfp_rd_reg_SFP_SDA_e_i:Q (r) + 3.266 net: SIU_SDA_e 11.449 bbuf_SIU_SDA/U0/U1:E (r) + 0.349 cell: ADLIB:IOBI_IB_OB_EB 11.798 bbuf_SIU_SDA/U0/U1:EOUT (r) + 0.000 net: bbuf_SIU_SDA/U0/NET2 11.798 bbuf_SIU_SDA/U0/U0:E (r) + 4.583 cell: ADLIB:IOPAD_BI 16.381 bbuf_SIU_SDA/U0/U0:PAD (f) + 0.000 net: SIU_SDA 16.381 SIU_SDA (f) 16.381 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C SIU_SDA (f) Expanded Path 5 From: i_adc/sfp_rd_reg_SFP_SDA_o_i:CLK To: SIU_SDA data required time N/C data arrival time - 16.128 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.860 net: CLK40out 7.749 i_adc/sfp_rd_reg_SFP_SDA_o_i:CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.299 i_adc/sfp_rd_reg_SFP_SDA_o_i:Q (f) + 2.838 net: SIU_SDA_o 11.137 bbuf_SIU_SDA/U0/U1:D (f) + 0.492 cell: ADLIB:IOBI_IB_OB_EB 11.629 bbuf_SIU_SDA/U0/U1:DOUT (f) + 0.000 net: bbuf_SIU_SDA/U0/NET1 11.629 bbuf_SIU_SDA/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_BI 16.128 bbuf_SIU_SDA/U0/U0:PAD (f) + 0.000 net: SIU_SDA 16.128 SIU_SDA (f) 16.128 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C SIU_SDA (f) Expanded Path 6 From: i_adc/sfp_rd_reg_SFP_SCL_i:CLK To: SIU_SCL data required time N/C data arrival time - 16.094 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.845 net: CLK40out 7.734 i_adc/sfp_rd_reg_SFP_SCL_i:CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.284 i_adc/sfp_rd_reg_SFP_SCL_i:Q (f) + 2.819 net: SIU_SCL_i 11.103 obuf_SIU_SCL_U1/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 11.595 obuf_SIU_SCL_U1/U0/U1:DOUT (f) + 0.000 net: obuf_SIU_SCL_U1/U0/NET1 11.595 obuf_SIU_SCL_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 16.094 obuf_SIU_SCL_U1/U0/U0:PAD (f) + 0.000 net: SIU_SCL 16.094 SIU_SCL (f) 16.094 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C SIU_SCL (f) Expanded Path 7 From: i_adc/adc/adci/reg_addr(4):CLK To: ADC_SDI data required time N/C data arrival time - 15.889 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.858 net: CLK40out 7.747 i_adc/adc/adci/reg_addr(4):CLK (r) + 0.550 cell: ADLIB:DFN1E1 8.297 i_adc/adc/adci/reg_addr(4):Q (f) + 2.658 net: ADC_SDI_i 10.955 obuf_ADC_SDI_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 11.390 obuf_ADC_SDI_U1/U0/U1:DOUT (f) + 0.000 net: obuf_ADC_SDI_U1/U0/NET1 11.390 obuf_ADC_SDI_U1/U0/U0:D (f) + 4.499 cell: ADLIB:IOPAD_TRI 15.889 obuf_ADC_SDI_U1/U0/U0:PAD (f) + 0.000 net: ADC_SDI 15.889 ADC_SDI (f) 15.889 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C ADC_SDI (f) Expanded Path 8 From: i_adc/scsn_slv_nw_nwl/reg_bridged:CLK To: SCSNOUTn data required time N/C data arrival time - 15.519 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.809 net: CLK40out 7.698 i_adc/scsn_slv_nw_nwl/reg_bridged:CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.248 i_adc/scsn_slv_nw_nwl/reg_bridged:Q (f) + 1.579 net: i_adc/scsn_slv_bridge 9.827 i_adc/SCSNOUT:S (f) + 0.358 cell: ADLIB:MX2 10.185 i_adc/SCSNOUT:Y (r) + 3.433 net: SCSNOUT2_i 13.618 lvds_SCSNOUT_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 14.105 lvds_SCSNOUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 14.105 lvds_SCSNOUT_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 15.519 lvds_SCSNOUT_iob/U0/U2:PAD (f) + 0.000 net: SCSNOUTn 15.519 SCSNOUTn (f) 15.519 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C SCSNOUTn (f) Expanded Path 9 From: i_adc/scsn_slv_nw_nwl/reg_bridged:CLK To: SCSNOUTp data required time N/C data arrival time - 15.519 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.809 net: CLK40out 7.698 i_adc/scsn_slv_nw_nwl/reg_bridged:CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.248 i_adc/scsn_slv_nw_nwl/reg_bridged:Q (f) + 1.579 net: i_adc/scsn_slv_bridge 9.827 i_adc/SCSNOUT:S (f) + 0.358 cell: ADLIB:MX2 10.185 i_adc/SCSNOUT:Y (r) + 3.433 net: SCSNOUT2_i 13.618 lvds_SCSNOUT_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 14.105 lvds_SCSNOUT_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SCSNOUT_iob/U0/NET1 14.105 lvds_SCSNOUT_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 15.519 lvds_SCSNOUT_iob/U0/U0:PAD (r) + 0.000 net: SCSNOUTp 15.519 SCSNOUTp (r) 15.519 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C SCSNOUTp (r) Expanded Path 10 From: i_cbb/ttcex_out_inst_reg_a_channel_out:CLK To: A_ECL data required time N/C data arrival time - 14.864 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.826 net: CLK40out 7.715 i_cbb/ttcex_out_inst_reg_a_channel_out:CLK (r) + 0.550 cell: ADLIB:DFN1 8.265 i_cbb/ttcex_out_inst_reg_a_channel_out:Q (f) + 3.425 net: A_ECL_i 11.690 obuf_A_ECL_U1/U0/U1:D (f) + 0.435 cell: ADLIB:IOTRI_OB_EB 12.125 obuf_A_ECL_U1/U0/U1:DOUT (f) + 0.000 net: obuf_A_ECL_U1/U0/NET1 12.125 obuf_A_ECL_U1/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 14.864 obuf_A_ECL_U1/U0/U0:PAD (f) + 0.000 net: A_ECL 14.864 A_ECL (f) 14.864 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C N/C A_ECL (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(48):CLR Delay (ns): 8.787 Slack (ns): 16.004 Arrival (ns): 16.522 Required (ns): 32.526 Recovery (ns): 0.222 Minimum Period (ns): 8.996 Skew (ns): -0.013 Path 2 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(40):CLR Delay (ns): 8.787 Slack (ns): 16.004 Arrival (ns): 16.522 Required (ns): 32.526 Recovery (ns): 0.222 Minimum Period (ns): 8.996 Skew (ns): -0.013 Path 3 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(24):CLR Delay (ns): 8.800 Slack (ns): 16.008 Arrival (ns): 16.535 Required (ns): 32.543 Recovery (ns): 0.222 Minimum Period (ns): 8.992 Skew (ns): -0.030 Path 4 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(32):CLR Delay (ns): 8.800 Slack (ns): 16.008 Arrival (ns): 16.535 Required (ns): 32.543 Recovery (ns): 0.222 Minimum Period (ns): 8.992 Skew (ns): -0.030 Path 5 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(16):CLR Delay (ns): 8.716 Slack (ns): 16.085 Arrival (ns): 16.451 Required (ns): 32.536 Recovery (ns): 0.222 Minimum Period (ns): 8.915 Skew (ns): -0.023 Path 6 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_din_syn(3):PRE Delay (ns): 8.518 Slack (ns): 16.235 Arrival (ns): 16.253 Required (ns): 32.488 Recovery (ns): 0.222 Minimum Period (ns): 8.765 Skew (ns): 0.025 Path 7 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_din_del1(3):PRE Delay (ns): 8.113 Slack (ns): 16.640 Arrival (ns): 15.848 Required (ns): 32.488 Recovery (ns): 0.222 Minimum Period (ns): 8.360 Skew (ns): 0.025 Path 8 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(6):CLR Delay (ns): 8.062 Slack (ns): 16.739 Arrival (ns): 15.797 Required (ns): 32.536 Recovery (ns): 0.222 Minimum Period (ns): 8.261 Skew (ns): -0.023 Path 9 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(3):CLR Delay (ns): 7.969 Slack (ns): 16.785 Arrival (ns): 15.704 Required (ns): 32.489 Recovery (ns): 0.222 Minimum Period (ns): 8.215 Skew (ns): 0.024 Path 10 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_din_del1(7):PRE Delay (ns): 7.836 Slack (ns): 16.935 Arrival (ns): 15.571 Required (ns): 32.506 Recovery (ns): 0.222 Minimum Period (ns): 8.065 Skew (ns): 0.007 Expanded Path 1 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(48):CLR data required time 32.526 data arrival time - 16.522 slack 16.004 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 8.237 net: i_cbb/rst_scsn 16.522 i_cbb/ram_cnt_inst/reg_cnt_new(48):CLR (f) 16.522 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.859 net: CLK40out 32.748 i_cbb/ram_cnt_inst/reg_cnt_new(48):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.526 i_cbb/ram_cnt_inst/reg_cnt_new(48):CLR 32.526 data required time Expanded Path 2 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(40):CLR data required time 32.526 data arrival time - 16.522 slack 16.004 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 8.237 net: i_cbb/rst_scsn 16.522 i_cbb/ram_cnt_inst/reg_cnt_new(40):CLR (f) 16.522 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.859 net: CLK40out 32.748 i_cbb/ram_cnt_inst/reg_cnt_new(40):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.526 i_cbb/ram_cnt_inst/reg_cnt_new(40):CLR 32.526 data required time Expanded Path 3 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(24):CLR data required time 32.543 data arrival time - 16.535 slack 16.008 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 8.250 net: i_cbb/rst_scsn 16.535 i_cbb/ram_cnt_inst/reg_cnt_new(24):CLR (f) 16.535 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.876 net: CLK40out 32.765 i_cbb/ram_cnt_inst/reg_cnt_new(24):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.543 i_cbb/ram_cnt_inst/reg_cnt_new(24):CLR 32.543 data required time Expanded Path 4 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(32):CLR data required time 32.543 data arrival time - 16.535 slack 16.008 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 8.250 net: i_cbb/rst_scsn 16.535 i_cbb/ram_cnt_inst/reg_cnt_new(32):CLR (f) 16.535 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.876 net: CLK40out 32.765 i_cbb/ram_cnt_inst/reg_cnt_new(32):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.543 i_cbb/ram_cnt_inst/reg_cnt_new(32):CLR 32.543 data required time Expanded Path 5 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(16):CLR data required time 32.536 data arrival time - 16.451 slack 16.085 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 8.166 net: i_cbb/rst_scsn 16.451 i_cbb/ram_cnt_inst/reg_cnt_new(16):CLR (f) 16.451 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.869 net: CLK40out 32.758 i_cbb/ram_cnt_inst/reg_cnt_new(16):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.536 i_cbb/ram_cnt_inst/reg_cnt_new(16):CLR 32.536 data required time Expanded Path 6 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_din_syn(3):PRE data required time 32.488 data arrival time - 16.253 slack 16.235 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 7.968 net: i_cbb/rst_scsn 16.253 i_cbb/cbbr_top_1/reg_din_syn(3):PRE (f) 16.253 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.821 net: CLK40out 32.710 i_cbb/cbbr_top_1/reg_din_syn(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1P1 32.488 i_cbb/cbbr_top_1/reg_din_syn(3):PRE 32.488 data required time Expanded Path 7 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_din_del1(3):PRE data required time 32.488 data arrival time - 15.848 slack 16.640 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 7.563 net: i_cbb/rst_scsn 15.848 i_cbb/cbbr_top_1/reg_din_del1(3):PRE (f) 15.848 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.821 net: CLK40out 32.710 i_cbb/cbbr_top_1/reg_din_del1(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1P1 32.488 i_cbb/cbbr_top_1/reg_din_del1(3):PRE 32.488 data required time Expanded Path 8 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(6):CLR data required time 32.536 data arrival time - 15.797 slack 16.739 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 7.512 net: i_cbb/rst_scsn 15.797 i_cbb/ram_cnt_inst/reg_cnt_new(6):CLR (f) 15.797 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.869 net: CLK40out 32.758 i_cbb/ram_cnt_inst/reg_cnt_new(6):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.536 i_cbb/ram_cnt_inst/reg_cnt_new(6):CLR 32.536 data required time Expanded Path 9 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/ram_cnt_inst/reg_cnt_new(3):CLR data required time 32.489 data arrival time - 15.704 slack 16.785 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 7.419 net: i_cbb/rst_scsn 15.704 i_cbb/ram_cnt_inst/reg_cnt_new(3):CLR (f) 15.704 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.822 net: CLK40out 32.711 i_cbb/ram_cnt_inst/reg_cnt_new(3):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 32.489 i_cbb/ram_cnt_inst/reg_cnt_new(3):CLR 32.489 data required time Expanded Path 10 From: i_cbb/clock_generation_reg_rst_master:CLK To: i_cbb/cbbr_top_1/reg_din_del1(7):PRE data required time 32.506 data arrival time - 15.571 slack 16.935 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 6.889 + 0.846 net: CLK40out 7.735 i_cbb/clock_generation_reg_rst_master:CLK (r) + 0.550 cell: ADLIB:DFN1P1 8.285 i_cbb/clock_generation_reg_rst_master:Q (f) + 7.286 net: i_cbb/rst_scsn 15.571 i_cbb/cbbr_top_1/reg_din_del1(7):PRE (f) 15.571 data arrival time ________________________________________________________ Data required time calculation 25.000 i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source 25.000 i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation 31.889 + 0.839 net: CLK40out 32.728 i_cbb/cbbr_top_1/reg_din_del1(7):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1P1 32.506 i_cbb/cbbr_top_1/reg_din_del1(7):PRE 32.506 data required time END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery Path 1 From: PUSHB To: i_adc/siu_i/reg_fbDin_i(23):CLR Delay (ns): 13.867 Slack (ns): Arrival (ns): 13.867 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.351 Path 2 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR Delay (ns): 13.740 Slack (ns): Arrival (ns): 13.740 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.248 Path 3 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR Delay (ns): 13.740 Slack (ns): Arrival (ns): 13.740 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.248 Path 4 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(44):CLR Delay (ns): 13.740 Slack (ns): Arrival (ns): 13.740 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.248 Path 5 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(0):CLR Delay (ns): 13.727 Slack (ns): Arrival (ns): 13.727 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.243 Path 6 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(35):CLR Delay (ns): 13.740 Slack (ns): Arrival (ns): 13.740 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.243 Path 7 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(4):CLR Delay (ns): 13.697 Slack (ns): Arrival (ns): 13.697 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.213 Path 8 From: RST_n To: i_adc/siu_i/reg_fbDin_i(23):CLR Delay (ns): 13.673 Slack (ns): Arrival (ns): 13.673 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.157 Path 9 From: RST_n To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR Delay (ns): 13.546 Slack (ns): Arrival (ns): 13.546 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.054 Path 10 From: RST_n To: i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR Delay (ns): 13.546 Slack (ns): Arrival (ns): 13.546 Required (ns): Recovery (ns): 0.222 External Recovery (ns): 6.054 Expanded Path 1 From: PUSHB To: i_adc/siu_i/reg_fbDin_i(23):CLR data required time N/C data arrival time - 13.867 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.314 net: not_rst_n 13.867 i_adc/siu_i/reg_fbDin_i(23):CLR (f) 13.867 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.849 net: CLK40out N/C i_adc/siu_i/reg_fbDin_i(23):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/siu_i/reg_fbDin_i(23):CLR Expanded Path 2 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR data required time N/C data arrival time - 13.740 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.187 net: not_rst_n 13.740 i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR (f) 13.740 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.825 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR Expanded Path 3 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR data required time N/C data arrival time - 13.740 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.187 net: not_rst_n 13.740 i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR (f) 13.740 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.825 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR Expanded Path 4 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(44):CLR data required time N/C data arrival time - 13.740 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.187 net: not_rst_n 13.740 i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(44):CLR (f) 13.740 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.825 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(44):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(44):CLR Expanded Path 5 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(0):CLR data required time N/C data arrival time - 13.727 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.174 net: not_rst_n 13.727 i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(0):CLR (f) 13.727 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.817 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(0):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(0):CLR Expanded Path 6 From: PUSHB To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(35):CLR data required time N/C data arrival time - 13.740 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.187 net: not_rst_n 13.740 i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(35):CLR (f) 13.740 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.830 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(35):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(35):CLR Expanded Path 7 From: PUSHB To: i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(4):CLR data required time N/C data arrival time - 13.697 slack N/C ________________________________________________________ Data arrival time calculation 0.000 PUSHB (r) + 0.000 net: PUSHB 0.000 ibuf_PUSHB_ib/U0/U0:PAD (r) + 1.078 cell: ADLIB:IOPAD_IN 1.078 ibuf_PUSHB_ib/U0/U0:Y (r) + 0.000 net: ibuf_PUSHB_ib/U0/NET1 1.078 ibuf_PUSHB_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.110 ibuf_PUSHB_ib/U0/U1:Y (r) + 4.002 net: PUSHB_i 5.112 i_adc/adc/ix4491z24338:B (r) + 0.441 cell: ADLIB:NAND2 5.553 i_adc/adc/ix4491z24338:Y (f) + 8.144 net: not_rst_n 13.697 i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(4):CLR (f) 13.697 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.817 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(4):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ib1/modgen_counter_bitcounter_reg_q(4):CLR Expanded Path 8 From: RST_n To: i_adc/siu_i/reg_fbDin_i(23):CLR data required time N/C data arrival time - 13.673 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 8.314 net: not_rst_n 13.673 i_adc/siu_i/reg_fbDin_i(23):CLR (f) 13.673 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.849 net: CLK40out N/C i_adc/siu_i/reg_fbDin_i(23):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/siu_i/reg_fbDin_i(23):CLR Expanded Path 9 From: RST_n To: i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR data required time N/C data arrival time - 13.546 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 8.187 net: not_rst_n 13.546 i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR (f) 13.546 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.825 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ob0/reg_ob_data(37):CLR Expanded Path 10 From: RST_n To: i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR data required time N/C data arrival time - 13.546 slack N/C ________________________________________________________ Data arrival time calculation 0.000 RST_n (r) + 0.000 net: RST_n 0.000 ibuf_RST_n_ib/U0/U0:PAD (r) + 1.169 cell: ADLIB:IOPAD_IN 1.169 ibuf_RST_n_ib/U0/U0:Y (r) + 0.000 net: ibuf_RST_n_ib/U0/NET1 1.169 ibuf_RST_n_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.201 ibuf_RST_n_ib/U0/U1:Y (r) + 3.854 net: RST_n_i 5.055 i_adc/adc/ix4491z24338:A (r) + 0.304 cell: ADLIB:NAND2 5.359 i_adc/adc/ix4491z24338:Y (f) + 8.187 net: not_rst_n 13.546 i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR (f) 13.546 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLA + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLA (r) + 6.889 Clock generation N/C + 0.825 net: CLK40out N/C i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLK (r) - 0.222 Library recovery time: ADLIB:DFN1C1 N/C i_adc/scsn_slv_nw_dll_ib1/reg_b_data(36):CLR END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLB Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin oddr_BC_ECL_ob/U0/U1:OCLK SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Setup No Path END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) Delay (ns): 3.440 Slack (ns): Arrival (ns): 14.272 Required (ns): Clock to Out (ns): 14.272 Path 2 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) Delay (ns): 3.440 Slack (ns): Arrival (ns): 14.270 Required (ns): Clock to Out (ns): 14.270 Path 3 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL Delay (ns): 3.440 Slack (ns): Arrival (ns): 14.270 Required (ns): Clock to Out (ns): 14.270 Expanded Path 1 From: oddr_PIMLINK_2_ob/U0/U1:OCLK To: PIMLINK(2) data required time N/C data arrival time - 14.272 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 10.014 Clock generation 10.014 + 0.818 net: CLK40out_90 10.832 oddr_PIMLINK_2_ob/U0/U1:OCLK (r) + 0.701 cell: ADLIB:IOTRI_OD_EB 11.533 oddr_PIMLINK_2_ob/U0/U1:DOUT (f) + 0.000 net: oddr_PIMLINK_2_ob/U0/NET1 11.533 oddr_PIMLINK_2_ob/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 14.272 oddr_PIMLINK_2_ob/U0/U0:PAD (f) + 0.000 net: PIMLINK_2_ 14.272 PIMLINK(2) (f) 14.272 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.014 Clock generation N/C N/C PIMLINK(2) (f) Expanded Path 2 From: oddr_PIMLINK_1_ob/U0/U1:OCLK To: PIMLINK(1) data required time N/C data arrival time - 14.270 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 10.014 Clock generation 10.014 + 0.816 net: CLK40out_90 10.830 oddr_PIMLINK_1_ob/U0/U1:OCLK (r) + 0.701 cell: ADLIB:IOTRI_OD_EB 11.531 oddr_PIMLINK_1_ob/U0/U1:DOUT (f) + 0.000 net: oddr_PIMLINK_1_ob/U0/NET1 11.531 oddr_PIMLINK_1_ob/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 14.270 oddr_PIMLINK_1_ob/U0/U0:PAD (f) + 0.000 net: PIMLINK_1_ 14.270 PIMLINK(1) (f) 14.270 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.014 Clock generation N/C N/C PIMLINK(1) (f) Expanded Path 3 From: oddr_BC_ECL_ob/U0/U1:OCLK To: BC_ECL data required time N/C data arrival time - 14.270 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLB (r) + 10.014 Clock generation 10.014 + 0.816 net: CLK40out_90 10.830 oddr_BC_ECL_ob/U0/U1:OCLK (r) + 0.701 cell: ADLIB:IOTRI_OD_EB 11.531 oddr_BC_ECL_ob/U0/U1:DOUT (f) + 0.000 net: oddr_BC_ECL_ob/U0/NET1 11.531 oddr_BC_ECL_ob/U0/U0:D (f) + 2.739 cell: ADLIB:IOPAD_TRI 14.270 oddr_BC_ECL_ob/U0/U0:PAD (f) + 0.000 net: BC_ECL 14.270 BC_ECL (f) 14.270 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLB + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLB (r) + 10.014 Clock generation N/C N/C BC_ECL (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain i_cbb/clock_generation_ipll_Core:GLC SET Register to Register Path 1 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(0):D Delay (ns): 3.954 Slack (ns): 8.050 Arrival (ns): 11.724 Required (ns): 19.774 Setup (ns): 0.428 Minimum Period (ns): 4.450 Path 2 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(0):D Delay (ns): 3.096 Slack (ns): 8.912 Arrival (ns): 10.866 Required (ns): 19.778 Setup (ns): 0.428 Minimum Period (ns): 3.588 Path 3 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D Delay (ns): 2.556 Slack (ns): 9.442 Arrival (ns): 10.326 Required (ns): 19.768 Setup (ns): 0.428 Minimum Period (ns): 3.058 Path 4 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D Delay (ns): 2.316 Slack (ns): 9.761 Arrival (ns): 10.013 Required (ns): 19.774 Setup (ns): 0.428 Minimum Period (ns): 2.739 Path 5 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D Delay (ns): 2.078 Slack (ns): 9.921 Arrival (ns): 9.848 Required (ns): 19.769 Setup (ns): 0.428 Minimum Period (ns): 2.579 Path 6 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D Delay (ns): 2.126 Slack (ns): 9.947 Arrival (ns): 9.822 Required (ns): 19.769 Setup (ns): 0.428 Minimum Period (ns): 2.553 Path 7 From: i_cbb/cba_sample_reg_cb_par(2):CLK To: i_cbb/cba_sample_reg_cb_par(4):D Delay (ns): 0.836 Slack (ns): 11.231 Arrival (ns): 8.538 Required (ns): 19.769 Setup (ns): 0.428 Minimum Period (ns): 1.269 Path 8 From: i_cbb/cbc_sample_reg_cb_par(3):CLK To: i_cbb/cbc_sample_reg_cb_par(5):D Delay (ns): 0.837 Slack (ns): 11.235 Arrival (ns): 8.539 Required (ns): 19.774 Setup (ns): 0.428 Minimum Period (ns): 1.265 Path 9 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D Delay (ns): 0.837 Slack (ns): 11.235 Arrival (ns): 8.539 Required (ns): 19.774 Setup (ns): 0.428 Minimum Period (ns): 1.265 Path 10 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D Delay (ns): 0.837 Slack (ns): 11.235 Arrival (ns): 8.543 Required (ns): 19.778 Setup (ns): 0.428 Minimum Period (ns): 1.265 Expanded Path 1 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(0):D data required time 19.774 data arrival time - 11.724 slack 8.050 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.881 net: CLK80out 7.770 iddr_CB_A_ib/U0/U1:ICLK (r) + 0.367 cell: ADLIB:IOIN_ID 8.137 iddr_CB_A_ib/U0/U1:YR (r) + 3.587 net: CB_A_i_0_ 11.724 i_cbb/cba_sample_reg_cb_par(0):D (r) 11.724 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.813 net: CLK80out 20.202 i_cbb/cba_sample_reg_cb_par(0):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.774 i_cbb/cba_sample_reg_cb_par(0):D 19.774 data required time Expanded Path 2 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(0):D data required time 19.778 data arrival time - 10.866 slack 8.912 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.881 net: CLK80out 7.770 iddr_CB_C_ib/U0/U1:ICLK (r) + 0.367 cell: ADLIB:IOIN_ID 8.137 iddr_CB_C_ib/U0/U1:YR (r) + 2.729 net: CB_C_i_0_ 10.866 i_cbb/cbc_sample_reg_cb_par(0):D (r) 10.866 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.817 net: CLK80out 20.206 i_cbb/cbc_sample_reg_cb_par(0):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.778 i_cbb/cbc_sample_reg_cb_par(0):D 19.778 data required time Expanded Path 3 From: iddr_CB_A_ib/U0/U1:ICLK To: i_cbb/cba_sample_reg_cb_par(1):D data required time 19.768 data arrival time - 10.326 slack 9.442 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.881 net: CLK80out 7.770 iddr_CB_A_ib/U0/U1:ICLK (r) + 0.260 cell: ADLIB:IOIN_ID 8.030 iddr_CB_A_ib/U0/U1:YF (r) + 2.296 net: CB_A_i_1_ 10.326 i_cbb/cba_sample_reg_cb_par(1):D (r) 10.326 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.807 net: CLK80out 20.196 i_cbb/cba_sample_reg_cb_par(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.768 i_cbb/cba_sample_reg_cb_par(1):D 19.768 data required time Expanded Path 4 From: i_cbb/cbc_sample_reg_cb_par(1):CLK To: i_cbb/cbc_sample_reg_cb_par(3):D data required time 19.774 data arrival time - 10.013 slack 9.761 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.808 net: CLK80out 7.697 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.247 i_cbb/cbc_sample_reg_cb_par(1):Q (f) + 1.766 net: i_cbb/cbc_sample_cb_par_1_ 10.013 i_cbb/cbc_sample_reg_cb_par(3):D (f) 10.013 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.813 net: CLK80out 20.202 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.774 i_cbb/cbc_sample_reg_cb_par(3):D 19.774 data required time Expanded Path 5 From: iddr_CB_C_ib/U0/U1:ICLK To: i_cbb/cbc_sample_reg_cb_par(1):D data required time 19.769 data arrival time - 9.848 slack 9.921 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.881 net: CLK80out 7.770 iddr_CB_C_ib/U0/U1:ICLK (r) + 0.260 cell: ADLIB:IOIN_ID 8.030 iddr_CB_C_ib/U0/U1:YF (r) + 1.818 net: CB_C_i_1_ 9.848 i_cbb/cbc_sample_reg_cb_par(1):D (r) 9.848 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.808 net: CLK80out 20.197 i_cbb/cbc_sample_reg_cb_par(1):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.769 i_cbb/cbc_sample_reg_cb_par(1):D 19.769 data required time Expanded Path 6 From: i_cbb/cba_sample_reg_cb_par(1):CLK To: i_cbb/cba_sample_reg_cb_par(3):D data required time 19.769 data arrival time - 9.822 slack 9.947 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.807 net: CLK80out 7.696 i_cbb/cba_sample_reg_cb_par(1):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.246 i_cbb/cba_sample_reg_cb_par(1):Q (f) + 1.576 net: i_cbb/cba_sample_cb_par_1_ 9.822 i_cbb/cba_sample_reg_cb_par(3):D (f) 9.822 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.808 net: CLK80out 20.197 i_cbb/cba_sample_reg_cb_par(3):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.769 i_cbb/cba_sample_reg_cb_par(3):D 19.769 data required time Expanded Path 7 From: i_cbb/cba_sample_reg_cb_par(2):CLK To: i_cbb/cba_sample_reg_cb_par(4):D data required time 19.769 data arrival time - 8.538 slack 11.231 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.813 net: CLK80out 7.702 i_cbb/cba_sample_reg_cb_par(2):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.252 i_cbb/cba_sample_reg_cb_par(2):Q (f) + 0.286 net: i_cbb/cba_sample_cb_par_2_ 8.538 i_cbb/cba_sample_reg_cb_par(4):D (f) 8.538 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.808 net: CLK80out 20.197 i_cbb/cba_sample_reg_cb_par(4):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.769 i_cbb/cba_sample_reg_cb_par(4):D 19.769 data required time Expanded Path 8 From: i_cbb/cbc_sample_reg_cb_par(3):CLK To: i_cbb/cbc_sample_reg_cb_par(5):D data required time 19.774 data arrival time - 8.539 slack 11.235 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.813 net: CLK80out 7.702 i_cbb/cbc_sample_reg_cb_par(3):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.252 i_cbb/cbc_sample_reg_cb_par(3):Q (f) + 0.287 net: i_cbb/cbc_sample_cb_par_3_ 8.539 i_cbb/cbc_sample_reg_cb_par(5):D (f) 8.539 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.813 net: CLK80out 20.202 i_cbb/cbc_sample_reg_cb_par(5):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.774 i_cbb/cbc_sample_reg_cb_par(5):D 19.774 data required time Expanded Path 9 From: i_cbb/cba_sample_reg_cb_par(0):CLK To: i_cbb/cba_sample_reg_cb_par(2):D data required time 19.774 data arrival time - 8.539 slack 11.235 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.813 net: CLK80out 7.702 i_cbb/cba_sample_reg_cb_par(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.252 i_cbb/cba_sample_reg_cb_par(0):Q (f) + 0.287 net: i_cbb/cba_sample_cb_par_0_ 8.539 i_cbb/cba_sample_reg_cb_par(2):D (f) 8.539 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.813 net: CLK80out 20.202 i_cbb/cba_sample_reg_cb_par(2):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.774 i_cbb/cba_sample_reg_cb_par(2):D 19.774 data required time Expanded Path 10 From: i_cbb/cbc_sample_reg_cb_par(0):CLK To: i_cbb/cbc_sample_reg_cb_par(2):D data required time 19.778 data arrival time - 8.543 slack 11.235 ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.817 net: CLK80out 7.706 i_cbb/cbc_sample_reg_cb_par(0):CLK (r) + 0.550 cell: ADLIB:DFN1C1 8.256 i_cbb/cbc_sample_reg_cb_par(0):Q (f) + 0.287 net: i_cbb/cbc_sample_cb_par_0_ 8.543 i_cbb/cbc_sample_reg_cb_par(2):D (f) 8.543 data arrival time ________________________________________________________ Data required time calculation 12.500 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 12.500 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 19.389 + 0.817 net: CLK80out 20.206 i_cbb/cbc_sample_reg_cb_par(2):CLK (r) - 0.428 Library setup time: ADLIB:DFN1C1 19.778 i_cbb/cbc_sample_reg_cb_par(2):D 19.778 data required time END SET Register to Register ---------------------------------------------------- SET External Setup Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN Delay (ns): 0.898 Slack (ns): Arrival (ns): 0.898 Required (ns): Setup (ns): 0.245 External Setup (ns): -6.546 Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN Delay (ns): 0.898 Slack (ns): Arrival (ns): 0.898 Required (ns): Setup (ns): 0.245 External Setup (ns): -6.546 Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN Delay (ns): 0.898 Slack (ns): Arrival (ns): 0.898 Required (ns): Setup (ns): 0.245 External Setup (ns): -6.546 Expanded Path 1 From: CB_C To: iddr_CB_C_ib/U0/U1:YIN data required time N/C data arrival time - 0.898 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_C (r) + 0.000 net: CB_C 0.000 iddr_CB_C_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 iddr_CB_C_ib/U0/U0:Y (r) + 0.000 net: iddr_CB_C_ib/U0/NET1 0.898 iddr_CB_C_ib/U0/U1:YIN (r) 0.898 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (f) + 6.803 Clock generation N/C + 0.886 net: CLK80out N/C iddr_CB_C_ib/U0/U1:ICLK (f) - 0.245 Library setup time: ADLIB:IOIN_ID N/C iddr_CB_C_ib/U0/U1:YIN Expanded Path 2 From: BUSY To: iddr_busy_ib/U0/U1:YIN data required time N/C data arrival time - 0.898 slack N/C ________________________________________________________ Data arrival time calculation 0.000 BUSY (r) + 0.000 net: BUSY 0.000 iddr_busy_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 iddr_busy_ib/U0/U0:Y (r) + 0.000 net: iddr_busy_ib/U0/NET1 0.898 iddr_busy_ib/U0/U1:YIN (r) 0.898 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (f) + 6.803 Clock generation N/C + 0.886 net: CLK80out N/C iddr_busy_ib/U0/U1:ICLK (f) - 0.245 Library setup time: ADLIB:IOIN_ID N/C iddr_busy_ib/U0/U1:YIN Expanded Path 3 From: CB_A To: iddr_CB_A_ib/U0/U1:YIN data required time N/C data arrival time - 0.898 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CB_A (r) + 0.000 net: CB_A 0.000 iddr_CB_A_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 iddr_CB_A_ib/U0/U0:Y (r) + 0.000 net: iddr_CB_A_ib/U0/NET1 0.898 iddr_CB_A_ib/U0/U1:YIN (r) 0.898 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (f) + 6.803 Clock generation N/C + 0.886 net: CLK80out N/C iddr_CB_A_ib/U0/U1:ICLK (f) - 0.245 Library setup time: ADLIB:IOIN_ID N/C iddr_CB_A_ib/U0/U1:YIN END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p Delay (ns): 11.961 Slack (ns): Arrival (ns): 19.731 Required (ns): Clock to Out (ns): 19.731 Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n Delay (ns): 11.961 Slack (ns): Arrival (ns): 19.731 Required (ns): Clock to Out (ns): 19.731 Expanded Path 1 From: iddr_busy_ib/U0/U1:ICLK To: SPA_p data required time N/C data arrival time - 19.731 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.881 net: CLK80out 7.770 iddr_busy_ib/U0/U1:ICLK (r) + 0.367 cell: ADLIB:IOIN_ID 8.137 iddr_busy_ib/U0/U1:YR (r) + 4.879 net: BUSY_i_0_ 13.016 i_cbb/ix7212z10880:A (r) + 0.392 cell: ADLIB:XOR2 13.408 i_cbb/ix7212z10880:Y (r) + 2.014 net: i_cbb/nx7212z5 15.422 i_cbb/SPA:C (r) + 0.736 cell: ADLIB:XOR3 16.158 i_cbb/SPA:Y (f) + 1.645 net: SPA_i 17.803 lvds_SPA_iob/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 18.295 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 18.295 lvds_SPA_iob/U0/U0:D (f) + 1.436 cell: ADLIB:IOPADP_TRI 19.731 lvds_SPA_iob/U0/U0:PAD (f) + 0.000 net: SPA_p 19.731 SPA_p (f) 19.731 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation N/C N/C SPA_p (f) Expanded Path 2 From: iddr_busy_ib/U0/U1:ICLK To: SPA_n data required time N/C data arrival time - 19.731 slack N/C ________________________________________________________ Data arrival time calculation 0.000 i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source 0.000 i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation 6.889 + 0.881 net: CLK80out 7.770 iddr_busy_ib/U0/U1:ICLK (r) + 0.367 cell: ADLIB:IOIN_ID 8.137 iddr_busy_ib/U0/U1:YR (r) + 4.879 net: BUSY_i_0_ 13.016 i_cbb/ix7212z10880:A (r) + 0.392 cell: ADLIB:XOR2 13.408 i_cbb/ix7212z10880:Y (r) + 2.014 net: i_cbb/nx7212z5 15.422 i_cbb/SPA:C (r) + 0.736 cell: ADLIB:XOR3 16.158 i_cbb/SPA:Y (f) + 1.645 net: SPA_i 17.803 lvds_SPA_iob/U0/U1:D (f) + 0.492 cell: ADLIB:IOTRI_OB_EB 18.295 lvds_SPA_iob/U0/U1:DOUT (f) + 0.000 net: lvds_SPA_iob/U0/NET1 18.295 lvds_SPA_iob/U0/U2:DB (f) + 1.436 cell: ADLIB:IOPADN_OUT 19.731 lvds_SPA_iob/U0/U2:PAD (r) + 0.000 net: SPA_n 19.731 SPA_n (r) 19.731 data arrival time ________________________________________________________ Data required time calculation N/C i_cbb/clock_generation_ipll_Core:GLC + 0.000 Clock source N/C i_cbb/clock_generation_ipll_Core:GLC (r) + 6.889 Clock generation N/C N/C SPA_n (r) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Clock Domain CLK40p Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin lvds_clk40in_U1/U0/U0:PAD SET Register to Register No Path END SET Register to Register ---------------------------------------------------- SET External Setup No Path END SET External Setup ---------------------------------------------------- SET Clock to Output Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p Delay (ns): 4.814 Slack (ns): Arrival (ns): 9.703 Required (ns): Clock to Out (ns): 9.703 Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n Delay (ns): 4.814 Slack (ns): Arrival (ns): 9.703 Required (ns): Clock to Out (ns): 9.703 Expanded Path 1 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_p data required time N/C data arrival time - 9.703 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (r) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_clk40in_U1/U0/U0:Y (r) + 0.000 net: lvds_clk40in_U1/U0/NET1 1.392 lvds_clk40in_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_clk40in_U1/U0/U1:Y (r) + 3.465 net: CLK40_i 4.889 i_cbb/clock_generation_ipll_Core:CLKA (r) + 2.000 cell: ADLIB:PLL 6.889 i_cbb/clock_generation_ipll_Core:GLA (r) + 0.913 net: CLK40out 7.802 lvds_clk40out_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 8.289 lvds_clk40out_iob/U0/U1:DOUT (r) + 0.000 net: lvds_clk40out_iob/U0/NET1 8.289 lvds_clk40out_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 9.703 lvds_clk40out_iob/U0/U0:PAD (r) + 0.000 net: CLK40T_p 9.703 CLK40T_p (r) 9.703 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_p (r) Expanded Path 2 From: i_cbb/clock_generation_ipll_Core:CLKA To: CLK40T_n data required time N/C data arrival time - 9.703 slack N/C ________________________________________________________ Data arrival time calculation 0.000 CLK40p + 0.000 Clock source 0.000 CLK40p (r) + 0.000 net: CLK40p 0.000 lvds_clk40in_U1/U0/U0:PAD (r) + 1.392 cell: ADLIB:IOPADP_IN 1.392 lvds_clk40in_U1/U0/U0:Y (r) + 0.000 net: lvds_clk40in_U1/U0/NET1 1.392 lvds_clk40in_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.424 lvds_clk40in_U1/U0/U1:Y (r) + 3.465 net: CLK40_i 4.889 i_cbb/clock_generation_ipll_Core:CLKA (r) + 2.000 cell: ADLIB:PLL 6.889 i_cbb/clock_generation_ipll_Core:GLA (r) + 0.913 net: CLK40out 7.802 lvds_clk40out_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 8.289 lvds_clk40out_iob/U0/U1:DOUT (r) + 0.000 net: lvds_clk40out_iob/U0/NET1 8.289 lvds_clk40out_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 9.703 lvds_clk40out_iob/U0/U2:PAD (f) + 0.000 net: CLK40T_n 9.703 CLK40T_n (f) 9.703 data arrival time ________________________________________________________ Data required time calculation N/C CLK40p + 0.000 Clock source N/C CLK40p (r) N/C CLK40T_n (f) END SET Clock to Output ---------------------------------------------------- SET Register to Asynchronous No Path END SET Register to Asynchronous ---------------------------------------------------- SET External Recovery No Path END SET External Recovery ---------------------------------------------------- SET Asynchronous to Register No Path END SET Asynchronous to Register ---------------------------------------------------- Path set Pin to Pin SET Input to Output Path 1 From: IO_C(1) To: SPA_p Delay (ns): 13.313 Slack (ns): Arrival (ns): 13.313 Required (ns): Path 2 From: IO_C(1) To: SPA_n Delay (ns): 13.313 Slack (ns): Arrival (ns): 13.313 Required (ns): Path 3 From: IO_C(0) To: SPA_p Delay (ns): 12.634 Slack (ns): Arrival (ns): 12.634 Required (ns): Path 4 From: IO_C(0) To: SPA_n Delay (ns): 12.634 Slack (ns): Arrival (ns): 12.634 Required (ns): Path 5 From: S2_IN_p(1) To: SPA_p Delay (ns): 12.399 Slack (ns): Arrival (ns): 12.399 Required (ns): Path 6 From: S2_IN_p(1) To: SPA_n Delay (ns): 12.399 Slack (ns): Arrival (ns): 12.399 Required (ns): Path 7 From: S2_IN_n(1) To: SPA_p Delay (ns): 12.370 Slack (ns): Arrival (ns): 12.370 Required (ns): Path 8 From: S2_IN_n(1) To: SPA_n Delay (ns): 12.370 Slack (ns): Arrival (ns): 12.370 Required (ns): Path 9 From: S2_IN_n(0) To: SPA_p Delay (ns): 11.337 Slack (ns): Arrival (ns): 11.337 Required (ns): Path 10 From: S2_IN_n(0) To: SPA_n Delay (ns): 11.337 Slack (ns): Arrival (ns): 11.337 Required (ns): Expanded Path 1 From: IO_C(1) To: SPA_p data required time N/C data arrival time - 13.313 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(1) (r) + 0.000 net: IO_C_1_ 0.000 ibuf_IO_C1_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_IO_C1_ib/U0/U0:Y (r) + 0.000 net: ibuf_IO_C1_ib/U0/NET1 1.129 ibuf_IO_C1_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_IO_C1_ib/U0/U1:Y (r) + 4.173 net: IO_C_i_1_ 5.334 i_cbb/ix7212z10877:B (r) + 0.559 cell: ADLIB:XOR2 5.893 i_cbb/ix7212z10877:Y (f) + 0.230 net: i_cbb/nx7212z2 6.123 i_cbb/modgen_xor_1422_ix7212z10877:A (f) + 0.365 cell: ADLIB:XOR3 6.488 i_cbb/modgen_xor_1422_ix7212z10877:Y (r) + 2.945 net: i_cbb/nx7212z1 9.433 i_cbb/SPA:A (r) + 0.257 cell: ADLIB:XOR3 9.690 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 11.412 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 11.899 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 11.899 lvds_SPA_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 13.313 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 13.313 SPA_p (r) 13.313 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(1) (r) N/C SPA_p (r) N/C data required time Expanded Path 2 From: IO_C(1) To: SPA_n data required time N/C data arrival time - 13.313 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(1) (r) + 0.000 net: IO_C_1_ 0.000 ibuf_IO_C1_ib/U0/U0:PAD (r) + 1.129 cell: ADLIB:IOPAD_IN 1.129 ibuf_IO_C1_ib/U0/U0:Y (r) + 0.000 net: ibuf_IO_C1_ib/U0/NET1 1.129 ibuf_IO_C1_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.161 ibuf_IO_C1_ib/U0/U1:Y (r) + 4.173 net: IO_C_i_1_ 5.334 i_cbb/ix7212z10877:B (r) + 0.559 cell: ADLIB:XOR2 5.893 i_cbb/ix7212z10877:Y (f) + 0.230 net: i_cbb/nx7212z2 6.123 i_cbb/modgen_xor_1422_ix7212z10877:A (f) + 0.365 cell: ADLIB:XOR3 6.488 i_cbb/modgen_xor_1422_ix7212z10877:Y (r) + 2.945 net: i_cbb/nx7212z1 9.433 i_cbb/SPA:A (r) + 0.257 cell: ADLIB:XOR3 9.690 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 11.412 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 11.899 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 11.899 lvds_SPA_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 13.313 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 13.313 SPA_n (f) 13.313 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(1) (r) N/C SPA_n (f) N/C data required time Expanded Path 3 From: IO_C(0) To: SPA_p data required time N/C data arrival time - 12.634 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(0) (r) + 0.000 net: IO_C_0_ 0.000 ibuf_IO_C0_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_IO_C0_ib/U0/U0:Y (r) + 0.000 net: ibuf_IO_C0_ib/U0/NET1 0.898 ibuf_IO_C0_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_IO_C0_ib/U0/U1:Y (r) + 3.944 net: IO_C_i_0_ 4.874 i_cbb/ix7212z10877:A (r) + 0.340 cell: ADLIB:XOR2 5.214 i_cbb/ix7212z10877:Y (f) + 0.230 net: i_cbb/nx7212z2 5.444 i_cbb/modgen_xor_1422_ix7212z10877:A (f) + 0.365 cell: ADLIB:XOR3 5.809 i_cbb/modgen_xor_1422_ix7212z10877:Y (r) + 2.945 net: i_cbb/nx7212z1 8.754 i_cbb/SPA:A (r) + 0.257 cell: ADLIB:XOR3 9.011 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 10.733 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 11.220 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 11.220 lvds_SPA_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 12.634 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 12.634 SPA_p (r) 12.634 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(0) (r) N/C SPA_p (r) N/C data required time Expanded Path 4 From: IO_C(0) To: SPA_n data required time N/C data arrival time - 12.634 slack N/C ________________________________________________________ Data arrival time calculation 0.000 IO_C(0) (r) + 0.000 net: IO_C_0_ 0.000 ibuf_IO_C0_ib/U0/U0:PAD (r) + 0.898 cell: ADLIB:IOPAD_IN 0.898 ibuf_IO_C0_ib/U0/U0:Y (r) + 0.000 net: ibuf_IO_C0_ib/U0/NET1 0.898 ibuf_IO_C0_ib/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 0.930 ibuf_IO_C0_ib/U0/U1:Y (r) + 3.944 net: IO_C_i_0_ 4.874 i_cbb/ix7212z10877:A (r) + 0.340 cell: ADLIB:XOR2 5.214 i_cbb/ix7212z10877:Y (f) + 0.230 net: i_cbb/nx7212z2 5.444 i_cbb/modgen_xor_1422_ix7212z10877:A (f) + 0.365 cell: ADLIB:XOR3 5.809 i_cbb/modgen_xor_1422_ix7212z10877:Y (r) + 2.945 net: i_cbb/nx7212z1 8.754 i_cbb/SPA:A (r) + 0.257 cell: ADLIB:XOR3 9.011 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 10.733 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 11.220 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 11.220 lvds_SPA_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 12.634 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 12.634 SPA_n (f) 12.634 data arrival time ________________________________________________________ Data required time calculation N/C IO_C(0) (r) N/C SPA_n (f) N/C data required time Expanded Path 5 From: S2_IN_p(1) To: SPA_p data required time N/C data arrival time - 12.399 slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_p(1) (f) + 0.000 net: S2_IN_p_1_ 0.000 adds1s2[1].lvds_S2in_U1/U0/U0:PAD (f) + 1.395 cell: ADLIB:IOPADP_IN 1.395 adds1s2[1].lvds_S2in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S2in_U1/U0/NET1 1.395 adds1s2[1].lvds_S2in_U1/U0/U1:YIN (f) + 0.030 cell: ADLIB:IOIN_IB 1.425 adds1s2[1].lvds_S2in_U1/U0/U1:Y (f) + 1.726 net: S2_IN_i_1_ 3.151 i_cbb/ix7212z10879:B (f) + 0.737 cell: ADLIB:XOR2 3.888 i_cbb/ix7212z10879:Y (f) + 2.124 net: i_cbb/nx7212z4 6.012 i_cbb/modgen_xor_1422_ix7212z10879:A (f) + 0.365 cell: ADLIB:XOR3 6.377 i_cbb/modgen_xor_1422_ix7212z10879:Y (r) + 1.978 net: i_cbb/nx7212z3 8.355 i_cbb/SPA:B (r) + 0.421 cell: ADLIB:XOR3 8.776 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 10.498 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 10.985 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 10.985 lvds_SPA_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 12.399 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 12.399 SPA_p (r) 12.399 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_p(1) (f) N/C SPA_p (r) N/C data required time Expanded Path 6 From: S2_IN_p(1) To: SPA_n data required time N/C data arrival time - 12.399 slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_p(1) (f) + 0.000 net: S2_IN_p_1_ 0.000 adds1s2[1].lvds_S2in_U1/U0/U0:PAD (f) + 1.395 cell: ADLIB:IOPADP_IN 1.395 adds1s2[1].lvds_S2in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S2in_U1/U0/NET1 1.395 adds1s2[1].lvds_S2in_U1/U0/U1:YIN (f) + 0.030 cell: ADLIB:IOIN_IB 1.425 adds1s2[1].lvds_S2in_U1/U0/U1:Y (f) + 1.726 net: S2_IN_i_1_ 3.151 i_cbb/ix7212z10879:B (f) + 0.737 cell: ADLIB:XOR2 3.888 i_cbb/ix7212z10879:Y (f) + 2.124 net: i_cbb/nx7212z4 6.012 i_cbb/modgen_xor_1422_ix7212z10879:A (f) + 0.365 cell: ADLIB:XOR3 6.377 i_cbb/modgen_xor_1422_ix7212z10879:Y (r) + 1.978 net: i_cbb/nx7212z3 8.355 i_cbb/SPA:B (r) + 0.421 cell: ADLIB:XOR3 8.776 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 10.498 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 10.985 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 10.985 lvds_SPA_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 12.399 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 12.399 SPA_n (f) 12.399 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_p(1) (f) N/C SPA_n (f) N/C data required time Expanded Path 7 From: S2_IN_n(1) To: SPA_p data required time N/C data arrival time - 12.370 slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_n(1) (f) + 0.000 net: S2_IN_n_1_ 0.000 adds1s2[1].lvds_S2in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[1].lvds_S2in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[1]_lvds_S2in_U1/U0/U2_N2P 0.000 adds1s2[1].lvds_S2in_U1/U0/U0:N2PIN (f) + 1.366 cell: ADLIB:IOPADP_IN 1.366 adds1s2[1].lvds_S2in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S2in_U1/U0/NET1 1.366 adds1s2[1].lvds_S2in_U1/U0/U1:YIN (f) + 0.030 cell: ADLIB:IOIN_IB 1.396 adds1s2[1].lvds_S2in_U1/U0/U1:Y (f) + 1.726 net: S2_IN_i_1_ 3.122 i_cbb/ix7212z10879:B (f) + 0.737 cell: ADLIB:XOR2 3.859 i_cbb/ix7212z10879:Y (f) + 2.124 net: i_cbb/nx7212z4 5.983 i_cbb/modgen_xor_1422_ix7212z10879:A (f) + 0.365 cell: ADLIB:XOR3 6.348 i_cbb/modgen_xor_1422_ix7212z10879:Y (r) + 1.978 net: i_cbb/nx7212z3 8.326 i_cbb/SPA:B (r) + 0.421 cell: ADLIB:XOR3 8.747 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 10.469 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 10.956 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 10.956 lvds_SPA_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 12.370 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 12.370 SPA_p (r) 12.370 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_n(1) (f) N/C SPA_p (r) N/C data required time Expanded Path 8 From: S2_IN_n(1) To: SPA_n data required time N/C data arrival time - 12.370 slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_n(1) (f) + 0.000 net: S2_IN_n_1_ 0.000 adds1s2[1].lvds_S2in_U1/U0/U2:PAD (f) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[1].lvds_S2in_U1/U0/U2:N2POUT (f) + 0.000 net: adds1s2[1]_lvds_S2in_U1/U0/U2_N2P 0.000 adds1s2[1].lvds_S2in_U1/U0/U0:N2PIN (f) + 1.366 cell: ADLIB:IOPADP_IN 1.366 adds1s2[1].lvds_S2in_U1/U0/U0:Y (f) + 0.000 net: adds1s2[1]_lvds_S2in_U1/U0/NET1 1.366 adds1s2[1].lvds_S2in_U1/U0/U1:YIN (f) + 0.030 cell: ADLIB:IOIN_IB 1.396 adds1s2[1].lvds_S2in_U1/U0/U1:Y (f) + 1.726 net: S2_IN_i_1_ 3.122 i_cbb/ix7212z10879:B (f) + 0.737 cell: ADLIB:XOR2 3.859 i_cbb/ix7212z10879:Y (f) + 2.124 net: i_cbb/nx7212z4 5.983 i_cbb/modgen_xor_1422_ix7212z10879:A (f) + 0.365 cell: ADLIB:XOR3 6.348 i_cbb/modgen_xor_1422_ix7212z10879:Y (r) + 1.978 net: i_cbb/nx7212z3 8.326 i_cbb/SPA:B (r) + 0.421 cell: ADLIB:XOR3 8.747 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 10.469 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 10.956 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 10.956 lvds_SPA_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 12.370 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 12.370 SPA_n (f) 12.370 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_n(1) (f) N/C SPA_n (f) N/C data required time Expanded Path 9 From: S2_IN_n(0) To: SPA_p data required time N/C data arrival time - 11.337 slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_n(0) (r) + 0.000 net: S2_IN_n_0_ 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:N2POUT (r) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/U2_N2P 0.000 adds1s2[0].lvds_S2in_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 adds1s2[0].lvds_S2in_U1/U0/U0:Y (r) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/NET1 1.421 adds1s2[0].lvds_S2in_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 adds1s2[0].lvds_S2in_U1/U0/U1:Y (r) + 0.994 net: S2_IN_i_0_ 2.447 i_cbb/ix7212z10879:A (r) + 0.392 cell: ADLIB:XOR2 2.839 i_cbb/ix7212z10879:Y (r) + 2.191 net: i_cbb/nx7212z4 5.030 i_cbb/modgen_xor_1422_ix7212z10879:A (r) + 0.297 cell: ADLIB:XOR3 5.327 i_cbb/modgen_xor_1422_ix7212z10879:Y (f) + 1.912 net: i_cbb/nx7212z3 7.239 i_cbb/SPA:B (f) + 0.475 cell: ADLIB:XOR3 7.714 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 9.436 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 9.923 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 9.923 lvds_SPA_iob/U0/U0:D (r) + 1.414 cell: ADLIB:IOPADP_TRI 11.337 lvds_SPA_iob/U0/U0:PAD (r) + 0.000 net: SPA_p 11.337 SPA_p (r) 11.337 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_n(0) (r) N/C SPA_p (r) N/C data required time Expanded Path 10 From: S2_IN_n(0) To: SPA_n data required time N/C data arrival time - 11.337 slack N/C ________________________________________________________ Data arrival time calculation 0.000 S2_IN_n(0) (r) + 0.000 net: S2_IN_n_0_ 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:PAD (r) + 0.000 cell: ADLIB:IOPADN_IN 0.000 adds1s2[0].lvds_S2in_U1/U0/U2:N2POUT (r) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/U2_N2P 0.000 adds1s2[0].lvds_S2in_U1/U0/U0:N2PIN (r) + 1.421 cell: ADLIB:IOPADP_IN 1.421 adds1s2[0].lvds_S2in_U1/U0/U0:Y (r) + 0.000 net: adds1s2[0]_lvds_S2in_U1/U0/NET1 1.421 adds1s2[0].lvds_S2in_U1/U0/U1:YIN (r) + 0.032 cell: ADLIB:IOIN_IB 1.453 adds1s2[0].lvds_S2in_U1/U0/U1:Y (r) + 0.994 net: S2_IN_i_0_ 2.447 i_cbb/ix7212z10879:A (r) + 0.392 cell: ADLIB:XOR2 2.839 i_cbb/ix7212z10879:Y (r) + 2.191 net: i_cbb/nx7212z4 5.030 i_cbb/modgen_xor_1422_ix7212z10879:A (r) + 0.297 cell: ADLIB:XOR3 5.327 i_cbb/modgen_xor_1422_ix7212z10879:Y (f) + 1.912 net: i_cbb/nx7212z3 7.239 i_cbb/SPA:B (f) + 0.475 cell: ADLIB:XOR3 7.714 i_cbb/SPA:Y (r) + 1.722 net: SPA_i 9.436 lvds_SPA_iob/U0/U1:D (r) + 0.487 cell: ADLIB:IOTRI_OB_EB 9.923 lvds_SPA_iob/U0/U1:DOUT (r) + 0.000 net: lvds_SPA_iob/U0/NET1 9.923 lvds_SPA_iob/U0/U2:DB (r) + 1.414 cell: ADLIB:IOPADN_OUT 11.337 lvds_SPA_iob/U0/U2:PAD (f) + 0.000 net: SPA_n 11.337 SPA_n (f) 11.337 data arrival time ________________________________________________________ Data required time calculation N/C S2_IN_n(0) (r) N/C SPA_n (f) N/C data required time END SET Input to Output ---------------------------------------------------- Path set User Sets