***************************************************************************
                               Status Report
                          Tue Sep  6 16:49:30 2011 ***************************************************************************

Product: Designer
Release: v9.1 SP3
Version: 9.1.3.4
File Name: /home/tkrawuts/svn/vhdl_inbufs/PIMDDL/trunk/unsav
Design Name: actel_par_A3PE1500  Design State: layout
Last Saved:

***** Device Data **************************************************

Family: ProASIC3E  Die: A3PE1500  Package: 208 PQFP
Speed: -2  Voltage: 1.5

Restrict JTAG Pins: YES
Restrict Probe Pins: YES

Junction Temperature Range:   COM
Voltage Range:   COM

***** Import Variables *********************************************

Source File(s) Imported on Tue Sep  6 16:34:31 2011:
        /home/tkrawuts/svn/vhdl_inbufs/PIMDDL/trunk/NETLIST/top_A3PE1500.edf
        /home/tkrawuts/svn/vhdl_inbufs/PIMDDL/trunk/script/pinout.pdc
        /home/tkrawuts/svn/vhdl_inbufs/PIMDDL/trunk/script/io_par.pdc
        /home/tkrawuts/svn/vhdl_inbufs/PIMDDL/trunk/script/timing.sdc


***** CAE Variables ************************************************

Back Annotation File: N/A


***** Bitstream Variables ******************************************

Bitstream File: N/A
     Lock Mode: OFF


***** Compile Variables ********************************************

Netlist PIN properties overwrite existing properties: 0

Layout Output:
***** Layout Variables *********************************************

Mode: TIMING_DRIVEN
Power-driven Layout: OFF
Incremental Placement: OFF
Incremental Route: OFF
Sequential Optimization: ON


Info: I/O Bank Assigner detected (8) out of (8) I/O Bank(s) with locked I/O technologies.
Info: All I/O Banks have locked technologies. Skipping I/O Bank Assigner.

Planning global net placement...
Info: PLC007: Created quadrant global region Qclock_SIU_RXCLK_cb for global net SIU_RXCLK_cb.



Global net placement completed successfully.

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Timing-driven Placer Started: Tue Sep  6 16:35:16 2011

Placer Finished: Tue Sep  6 16:43:50 2011
Total Placer CPU Time:     00:08:34

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Timing-driven Router
Design: actel_par_A3PE1500              Started: Tue Sep  6 16:44:14 2011


Iterative improvement...

Timing-driven Router completed successfully.

Design: actel_par_A3PE1500
Finished: Tue Sep  6 16:47:26 2011
Total CPU Time:     00:03:11            Total Elapsed Time: 00:03:12
Total Memory Usage: 417.8 Mbytes
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