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                            Global Usage Report
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Product: Designer
Release: v9.1 SP3
Version: 9.1.3.4
Date: Thu Aug 11 22:22:21 2011
Design Name: actel_par_A3PE3000  Family: ProASIC3E  Die: A3PE3000  Package: 208 PQFP
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    15                Net   : CLK80out
                      Driver: i_cbb/clock_generation_ipll_Core/U_GLC
    4622              Net   : CLK40out
                      Driver: i_cbb/clock_generation_ipll_Core/U_PLL
    3                 Net   : CLK40out_90
                      Driver: i_cbb/clock_generation_ipll_Core/U_GLB
    682               Net   : SIU_TXCLK_cb
                      Driver: cbuf_SIU_TXCLK/U_GL
    82                Net   : i_SIU/tx_clk_2b
                      Driver: i_SIU/cbuf_tx_clk_2/U_GL
    112               Net   : i_adc/clk1MHz_b
                      Driver: i_adc/cbuf_1MHz/U_GL


The following nets have been routed to a quadrant global resource:

    Fanout            Name
    ----------------------
    316               Net   : SIU_RXCLK_cb
                      Driver: cbuf_SIU_RXCLK/U_GL
                      Region : quadrant_UL