********************************************************************
                            Global Net Report
********************************************************************
  
Product: Designer
Release: v9.1 SP3
Version: 9.1.3.4
Date: Tue Sep  6 16:50:02 2011
Design Name: actel_par_A3PE1500  Family: ProASIC3E  Die: A3PE1500  Package: 208 PQFP


Automatic Global Net Placement Result:
Status: Global net placement completed successfully


Global Nets Information:

        |-----------------------------------------------------|
        |Global Nets         |Loads                           |
        |-----------------------------------------------------|
        |Name                |Core      |IO        |RAM       |
        |-----------------------------------------------------|
        |CLK40out            |     4595 |       10 |      640 |
        |-----------------------------------------------------|
        |CLK40out_90         |        0 |        3 |        0 |
        |-----------------------------------------------------|
        |CLK80out            |       12 |        3 |        0 |
        |-----------------------------------------------------|
        |SIU_RXCLK_cb        |      296 |       18 |       64 |
        |-----------------------------------------------------|
        |SIU_TXCLK_cb        |      662 |       18 |       64 |
        |-----------------------------------------------------|
        |i_SIU/tx_clk_2b     |       82 |        0 |        0 |
        |-----------------------------------------------------|
        |i_adc/clk1MHz_b     |      112 |        0 |        0 |
        |-----------------------------------------------------|

Nets Sharing Loads:

        |-------------------------------------------|
        |Global Net          |Shares Loads With ... |
        |-------------------------------------------|
        |CLK40out            |SIU_RXCLK_cb          |
        |                    |SIU_TXCLK_cb          |
        |-------------------------------------------|
        |SIU_RXCLK_cb        |CLK40out              |
        |-------------------------------------------|
        |SIU_TXCLK_cb        |CLK40out              |
        |-------------------------------------------|

Summary of Global Net Placement:

        |------------------------------------------------------------------------|
        |Global Net          |Assignment          |Violation                     |
        |------------------------------------------------------------------------|
        |CLK40out            |MIDDLE_RIGHT        |                              |
        |------------------------------------------------------------------------|
        |CLK40out_90         |MIDDLE_RIGHT        |                              |
        |------------------------------------------------------------------------|
        |CLK80out            |MIDDLE_RIGHT        |                              |
        |------------------------------------------------------------------------|
        |SIU_RXCLK_cb        |UPPER_LEFT          |                              |
        |------------------------------------------------------------------------|
        |SIU_TXCLK_cb        |MIDDLE_LEFT         |                              |
        |------------------------------------------------------------------------|
        |i_SIU/tx_clk_2b     |MIDDLE_LEFT         |                              |
        |------------------------------------------------------------------------|
        |i_adc/clk1MHz_b     |MIDDLE_LEFT         |                              |
        |------------------------------------------------------------------------|