---------------------------------------------------------------------------------- -- Company: -- Engineer: Stefan Zimmer -- -- Create Date: 01:17:34 02/07/2008 -- Design Name: -- Module Name: PIMFPGA - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Decodes the Manchester encoded fiber signals from the CCB and forwards them as -- LVDS to the CTP. In addition it forwards the GTU busy signals as manchester encoded signal to -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity PIMFPGA is port ( BUSY_IN1 : in std_logic; -- bussy signal from the GTU --BUSY_IN2 : in std_logic; --BUSY_IN3 : in std_logic; --BUSY_IN4 : in std_logic; --CB_A_BUSY_backup : out std_logic; CB_A_BUSY_primary : out std_logic; --CB_A_PIMLINK0_backup : in std_logic; CB_A_PIMLINK0_primary : in std_logic; --CB_A_PIMLINK1_backup : in std_logic; CB_A_PIMLINK1_primary : in std_logic; --CB_A_PIMLINK2_backup : in std_logic; CB_A_PIMLINK2_primary : in std_logic; --CB_C_BUSY_backup : out std_logic; --CB_C_BUSY_primary : out std_logic; --CB_C_PIMLINK0_backup : in std_logic; --CB_C_PIMLINK0_primary : in std_logic; --CB_C_PIMLINK1_backup : in std_logic; --CB_C_PIMLINK1_primary : in std_logic; --CB_C_PIMLINK2_backup : in std_logic; --CB_C_PIMLINK2_primary : in std_logic; --CB_TOF_BUSY_backup : out std_logic; -- fiber output for busy to CBTOF CB_TOF_BUSY_primary : out std_logic; -- fiber output for busy to CBTOF --CB_TOF_PIMLINK0_backup : in std_logic; CB_TOF_PIMLINK0_primary : in std_logic; -- clk: will be delayed for xor decoding --CB_TOF_PIMLINK1_backup : in std_logic; CB_TOF_PIMLINK1_primary : in std_logic; --CB_TOF_PIMLINK2_backup : in std_logic; CB_TOF_PIMLINK2_primary : in std_logic; LED1 : out std_logic; LED2 : out std_logic; BUSY_OUT1 : out std_logic; -- L0 pre-trigger output BUSY_OUT2 : out std_logic; -- L0 UPC trigger output BUSY_OUT3 : out std_logic; -- L1 output UPC data BUSY_OUT4 : out std_logic; -- L1 output UPC data BUSY_OUT5 : out std_logic; -- L1 output UPC data BUSY_OUT6 : out std_logic; -- L1 output UPC data BUSY_OUT7 : out std_logic; BUSY_OUT8 : out std_logic ); end PIMFPGA; architecture BEHAVIORAL of PIMFPGA is COMPONENT clk_enable_logic PORT( clk40 : IN std_logic; clk160 : IN std_logic; reset : IN std_logic; en0deg : OUT std_logic; en90deg : OUT std_logic; en180deg : OUT std_logic; en270deg : OUT std_logic ); END COMPONENT; signal clk40, clk40_prebuf : std_logic; signal clk40_B, clk40_prebuf_B : std_logic; signal sig1, sig2, sig3, sig4 : std_logic; -- primary system begin DCM_inst1 : DCM generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 24.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 40, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE port map ( CLK0 => clk40_prebuf, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => LED1, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk40, -- DCM clock feedback CLKIN => CB_TOF_PIMLINK0_primary, --PIM0_signal_P, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); BUFG_inst_clk40 : BUFG port map ( O => clk40, -- Clock buffer output I => clk40_prebuf -- Clock buffer input ); sig1 <= CB_TOF_PIMLINK0_primary xor CB_TOF_PIMLINK1_primary; process(clk40, sig1) begin if clk40'event and clk40 = '0' then BUSY_OUT1 <= sig1; end if; end process; sig2 <= CB_TOF_PIMLINK0_primary xor CB_TOF_PIMLINK2_primary; process(clk40, sig2) begin if clk40'event and clk40 = '0' then BUSY_OUT2 <= sig2; end if; end process; BUSY_OUT5 <= CB_TOF_PIMLINK0_primary; BUSY_OUT6 <= CB_TOF_PIMLINK1_primary; BUSY_OUT7 <= CB_TOF_PIMLINK2_primary; CB_TOF_BUSY_primary <= BUSY_IN1 xor clk40; LED2 <= CB_TOF_PIMLINK1_primary; -- backup system DCM_inst2 : DCM generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 24.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 40 , -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE port map ( CLK0 => clk40_prebuf_B, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => open, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk40_B, -- DCM clock feedback CLKIN => CB_A_PIMLINK0_primary, --PIM0_signal, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); BUFG_inst_clk40_B : BUFG port map ( O => clk40_B, -- Clock buffer output I => clk40_prebuf_B -- Clock buffer input ); sig3 <= CB_A_PIMLINK0_primary xor CB_A_PIMLINK1_primary; process(clk40_B, sig3) begin if clk40_B'event and clk40_B = '0' then BUSY_OUT3 <= sig3; end if; end process; sig4 <= CB_A_PIMLINK0_primary xor CB_A_PIMLINK2_primary; process(clk40_B, sig4) begin if clk40_B'event and clk40_B = '0' then BUSY_OUT4 <= sig4; end if; end process; CB_A_BUSY_primary <= BUSY_IN1 xor clk40_B; BUSY_OUT8 <= CB_A_PIMLINK2_primary; end BEHAVIORAL;