---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:03:05 04/05/2008 -- Design Name: -- Module Name: timing_analyze_module - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity timing_analyze_module is Port ( activate : in STD_LOGIC; -- keep active high whenever you want to be sensitive for triggers reset : in STD_LOGIC; -- normal sync reset design reset clear : in STD_LOGIC; -- clears the done; next activate will start recording done : out STD_LOGIC; signals : in STD_LOGIC_VECTOR (15 downto 0); clk : in STD_LOGIC; clk_scsn : in STD_LOGIC; readout_value : out STD_LOGIC_VECTOR (31 downto 0); readout_address : in STD_LOGIC_VECTOR (8 downto 0); trigger_mask: in STD_LOGIC_VECTOR(31 downto 0)); -- mark the bits you want to use for triggering with 1 end timing_analyze_module; architecture Behavioral of timing_analyze_module is signal sig1, sig1_reg, sig7, sig9, sig10, sig11, sig12: std_logic_vector(15 downto 0); signal sig2, sig3, sig4, sig5, sig8: std_logic; signal counter: std_logic_vector(8 downto 0); signal clear_signal: std_logic; signal done_signal: std_logic; type type_signals_reg is array (0 to 9) of std_logic_vector(15 downto 0); signal signals_reg : type_signals_reg; signal comp, comp1, comp2, comp3 : std_logic_vector(31 downto 0); signal comp4 : std_logic; -- signal trigger_mask_reg: std_logic_vector(15 downto 0); signal trigger_trap_reset: std_logic_vector(15 downto 0); signal comp_pre : std_LOGIC_VECTOR(15 DOWNTO 0); begin clear_signal <= clear or reset; -- trigger logic: start if one of the trigger signals changes -- detect signal change trigger_chain: for i in 0 to 15 generate process(reset, clk, signals(i)) begin if reset = '1' then sig7(i) <= '0'; elsif (clk'event and clk='1') then sig7(i) <= signals(i); end if; end process; process(reset, clk, sig12(i)) begin if reset = '1' then sig9(i) <= '0'; elsif (clk'event and clk='1') then sig9(i) <= sig12(i); end if; end process; process(reset, clk, sig11(i)) begin if reset = '1' then sig10(i) <= '0'; elsif (clk'event and clk='1') then sig10(i) <= sig11(i); end if; end process; sig1(i) <= (sig7(i) xor sig9(i)); -- don't use trigger mask here only -- one logic in a clk160 frame and trigger_mask(i)); -- after a clear prevent the trigger from being started by an old change -- set all registers to the signal value if there is a reset sig11(i) <= sig9(i) when clear_signal = '0' else signals(i); sig12(i) <= sig7(i) when clear_signal = '0' else signals(i); end generate; -- idea use larger buffer and use clk40 in the trigger decision logic !!!!!!!! -- trigger comperator don't use --sig2 <= '1' when sig1 /= X"00000000" else '0'; -- due to timing problems in the clk160 domain -- use pipeline structure for the comparison because of timing issues -- in each pipelinestep one LUT (4 inputs 1 output) -- this costs a view presamples trigger_register: for ii in 0 to 15 generate process(clk, reset, sig1(ii)) begin if reset = '1' then sig1_reg(ii) <= '0';--X"0000"; elsif clk'event and clk = '1' then sig1_reg(ii) <= sig1(ii); end if; end process; end generate; trigger_mask_reg: for ii in 0 to 15 generate trigger_trap_reset(ii) <= reset or (not activate) or clear_signal or (not trigger_mask(ii)) or done_signal; process(clk, trigger_trap_reset(ii),reset, sig1_reg(ii), comp_pre(ii)) begin if trigger_trap_reset(ii) = '1' then comp_pre(ii) <= '0'; elsif clk'event and clk = '1' then comp_pre(ii) <= sig1_reg(ii) or comp_pre(ii); end if; end process; process(clk, reset, comp_pre(ii)) begin if reset = '1' then comp(ii) <= '0'; elsif clk'event and clk = '1' then comp(ii) <= comp_pre(ii); end IF; end process; end generate; -- make the or of all possible triggers as pipeline -- first pipeline step: update this is not possible due to hardware limitations delay the trigger signal instead. -- select only between two trigger lines. (one physical trigger one fast trigger) --process(clk,comp(2 downto 3), reset) --DEBUG --begin -- if reset = '1' then -- comp1(0) <= '0'; -- elsif clk'event and clk = '1' then -- comp1(0) <= comp(2) or comp(0); -- end if; --end process; --sig2 <= comp(0); --sig1_reg(0); --trigger trap important to have a contiouus clk_en for the memory counter --sig8 <= sig2;-- and activate; activation is done in the reset signal --sig3 <= sig8 or sig5; process(clk,comp_pre(0),sig4, sig5) begin if sig4 ='1' then sig5 <= '0'; elsif clk'event and clk = '1' then sig5 <= comp_pre(0) or sig5; end if; end process; sig4 <= done_signal or clear_signal or reset; --sig5 <= sig2; --sig5 <= comp_pre(0); -- memory address counter process(clk, reset, counter, clear_signal, sig5) begin if clear_signal = '1' then counter <= "000000000"; elsif clk'event and clk='1' and sig5 = '1' then counter <= counter + '1'; end if; end process; -- stop recording if memory is full done_signal <= '1' when ((counter = 510) or (counter = 511)) else '0'; -- buffer for presamples --signals_reg(0) <= sig10(15 downto 0); signals_reg(0) <= signals; -- DEBUG presamples: for jj in 1 to 6 generate process(reset, clk, signals_reg(jj-1)) begin if reset = '1' then signals_reg(jj) <= X"0000"; elsif clk'event and clk='1' then signals_reg(jj) <= signals_reg(jj-1); end if; end process; end generate; -- memory to store counter value and trigger pattern RAMB16_S36_S36_inst : RAMB16_S36_S36 generic map ( INIT_A => X"000000000", -- Value of output RAM registers on Port A at startup INIT_B => X"000000000", -- Value of output RAM registers on Port B at startup SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE SIM_COLLISION_CHECK => "NONE", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" -- The following INIT_xx declarations specify the initial contents of the RAM -- Address 0 to 127 INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 128 to 255 INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 256 to 383 INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 384 to 511 INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INITP_xx are for the parity bits -- Address 0 to 127 INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 128 to 255 INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 256 to 383 INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", -- Address 384 to 511 INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( DOA => open, -- Port A 32-bit Data Output DOB => readout_value, -- Port B 32-bit Data Output DOPA => open, -- Port A 4-bit Parity Output DOPB => open, -- Port B 4-bit Parity Output ADDRA => counter, -- Port A 9-bit Address Input ADDRB => readout_address, -- Port B 9-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk_scsn, -- Port B Clock DIA(15 downto 0) => signals_reg(6), --DEBUG signals_reg(4),--sig10(31 downto 0), -- Port A 32-bit Data Input DIA(31 downto 16) => X"0000", DIB => X"01011000", -- Port B 32-bit Data Input DIPA => X"0", -- Port A 4-bit parity Input DIPB => X"0", -- Port-B 4-bit parity Input ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => reset, -- Port A Synchronous Set/Reset Input SSRB => reset, -- Port B Synchronous Set/Reset Input WEA => sig5, -- Port A Write Enable Input WEB => '0' -- Port B Write Enable Input ); done <= done_signal; end Behavioral;