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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:08:49 06/01/2008 
-- Design Name: 
-- Module Name:    serializer_clk80 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity serializer_clk80 is
    Port ( data_paralell : in  STD_LOGIC_VECTOR (1 downto 0);
           data_serial : out  STD_LOGIC;
           clk160 : in  STD_LOGIC;
			  reset : in STD_LOGIC;
           input_edge_marker_reg : in  STD_LOGIC);
end serializer_clk80;

architecture Behavioral of serializer_clk80 is

signal sig0 : std_logic;
signal counter : std_logic_vector(1 downto 0);
signal input_edge_marker : std_logic;

begin
process(clk160, reset, input_edge_marker_reg)
begin
   if reset = '1' then
	   input_edge_marker <= '0';
	elsif clk160'event and clk160 = '0' then
	   input_edge_marker <= input_edge_marker_reg;
	end if;
end process;

process(clk160, reset, input_edge_marker, counter)
begin
   if reset = '1' then
      counter  <= "00";
   elsif clk160'event and clk160 = '1' then
	   if input_edge_marker = '1' then
         counter <= "00";
      else
         counter <= counter + "1"; -- don't use not counter makes latching problems
      end if;
   end if;		
end process;

-- MSB most significant bit first
sig0 <= data_paralell(0) when counter(1) = '1' else data_paralell(1); 

-- conservative register for registering in the IOB
-- to ensure equal timing for sig0(0) and sig0(1)
-- can most probably be ommitet. So one can win another (6 ns - 2erMuxTime) = ca. 4 ns
process(clk160, reset, sig0)
begin
   if reset = '1' then
	   data_serial <= '0';
	elsif clk160'event and clk160 = '1' then
	   data_serial <= sig0;
	end if;
end process;	
	
end Behavioral;