----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Stefan Zimmer
-- 
-- Create Date:    15:42:26 03/13/2008 
-- Design Name: 
-- Module Name:    scintillator_trigger - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: syncronize asyncronous signals into the clk160 domain with low latency to avoid
--              setup and hold time problematics like oscillating registers.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity scintillator_trigger is
    Port ( scintillator : in  STD_LOGIC;
	        reset : in std_logic;
                veto: in std_logic;
           clk : in  STD_LOGIC;
			  busy_cycles : in STD_LOGIC_VECTOR(7 downto 0);
			  clk_enoutdeg_reg: in STD_LOGIC;
			  clk_enoutplus90deg_reg : in STD_LOGIC;
			  clk_enoutplus180deg_reg : in STD_LOGIC;
			  clk_enoutplus270deg_reg : in STD_LOGIC;
           to_SM : out  STD_LOGIC);
end scintillator_trigger;

architecture Behavioral of scintillator_trigger is

signal sig1 : std_logic;
signal sig2 : std_logic := '0';
signal sig3, sig4 : std_logic;
signal sig5, sig6 : std_logic;
signal sig7, sig8, sig9 : std_logic;
signal clk_enoutdeg, clk_enoutplus90deg: std_logic;
signal clk_enoutplus180deg, clk_enoutplus270deg: std_logic;

attribute period: string;
attribute PERIOD of clk: signal is "4ns";
attribute PERIOD of scintillator: signal is "4ns";
attribute PERIOD of sig3: signal is "4ns";

begin
   process(reset, clk, clk_enoutdeg_reg)
	begin
	   if reset='1' then
		   clk_enoutdeg <= '0';
		elsif clk'event and clk = '0' then
		   clk_enoutdeg <= clk_enoutdeg_reg;
		end if;
	end process;
	process(reset, clk, clk_enoutplus90deg_reg)
	begin
	   if reset='1' then
		   clk_enoutplus90deg <= '0';
		elsif clk'event and clk = '0' then
		   clk_enoutplus90deg <= clk_enoutplus90deg_reg;
		end if;
	end process;
	process(reset, clk, clk_enoutplus180deg_reg)
	begin
	   if reset='1' then
		   clk_enoutplus180deg <= '0';
		elsif clk'event and clk = '0' then
		   clk_enoutplus180deg <= clk_enoutplus180deg_reg;
		end if;
	end process;
	process(reset, clk, clk_enoutplus270deg_reg)
	begin
	   if reset='1' then
		   clk_enoutplus270deg <= '0';
		elsif clk'event and clk = '0' then
		   clk_enoutplus270deg <= clk_enoutplus270deg_reg;
		end if;
	end process;

   process(scintillator, sig5, reset)
	begin
	   if sig5 = '1' or reset = '1' then
		   sig1 <= '0';
		elsif scintillator'event and scintillator = '1' and veto = '0' then
         sig1 <= '1';
      end if;			
	end process;
	
	sig2 <= clk_enoutplus90deg or clk_enoutplus180deg; 
	sig3 <= sig1 and sig2;
	
	process(sig3, sig5, reset)
	begin
	   if sig5 = '1' or reset = '1' then
		   sig4 <= '0';
		elsif sig3'event and sig3 = '1' then
		   sig4 <= '1';
		end if;
	end process;
	
	process(sig4, clk, clk_enoutdeg, reset)
	begin
	   if reset = '1' then
		   sig6 <= '0';
		elsif clk'event and clk='1' and clk_enoutdeg='1' then
		   sig6 <= sig4 and not sig6;
		end if;
	end process;
	
	process(sig6,clk, clk_enoutdeg, reset)
	begin
	   if reset = '1' then
		   sig5 <= '0';
		elsif clk'event and clk = '1' and clk_enoutdeg = '1' then
		   sig5 <= sig6;
		end if;
	end process;
	
   to_SM <= sig6;

end Behavioral;