LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity general_config is
generic(
    device_id  : Integer := 1;
    version_id : Integer := 1);
    port (
        clk             : in  std_logic;
        reset_n         : in  std_logic;
		  GenReset        : out std_logic;
		  Temp            : in std_logic_vector(13 downto 0);
      -- enable
        bus_req         : in  std_logic;
        bus_ack         : out std_logic;

      -- internal bus
        bus_addr        : in  std_logic_vector(15 downto 0);
        bus_we          : in  std_logic;            -- write enable
        bus_din         : in  std_logic_vector(31 downto 0);
        bus_dout        : out std_logic_vector(31 downto 0);

      -- config registers
        creg0d          : out std_logic_vector(31 downto 0);
		  OutReg0         : out std_logic_vector(7 downto 0);
		  OutReg1         : out std_logic_vector(7 downto 0);
		  OutReg2         : out std_logic_vector(7 downto 0);
		  OutReg3         : out std_logic_vector(7 downto 0);
		  OutReg4         : out std_logic_vector(7 downto 0);
		  OutReg5         : out std_logic_vector(7 downto 0);
		  OutReg6         : out std_logic_vector(7 downto 0);
		  OutReg7         : out std_logic_vector(7 downto 0);
		  OutReg8         : out std_logic_vector(7 downto 0);
		  OutReg9         : out std_logic_vector(7 downto 0);
		  OutReg10        : out std_logic_vector(7 downto 0);
		  OutReg11        : out std_logic_vector(7 downto 0);
		  B               : out std_logic
        );
end general_config;

architecture a of general_config is

signal  dev_id        : std_logic_vector(31 downto 0);
signal  version       : std_logic_vector(31 downto 0);

signal  creg0d_i      : std_logic_vector(31 downto 0);
signal  creg1d_i      : std_logic_vector(7 downto 0);

type States is (Idle, Busy);
signal State : States;
signal Counter : integer range 0 to 5;
type DacRegister is array (11 downto 0, 7 downto 0) of std_logic;
signal RegA: DacRegister;
signal Ch: integer range 0 to 15;

begin
version <= conv_std_logic_vector(version_id, version'length);
dev_id  <= conv_std_logic_vector(device_id,  dev_id'length);
Ch <= conv_integer(bus_addr(3 downto 0));

process(clk, reset_n)
begin
	if reset_n='0' then
		creg0d_i      <= (others => '0');
		for I in 0 to 11 loop
			for L in 0 to 7 loop
				RegA(I, L) <= '0';
			end loop;
		end loop;
		B        <= '0';
		bus_ack  <= '0';
		GenReset <= '0';
	elsif rising_edge (clk) then
		bus_ack <= bus_req;
		if bus_we='1' and bus_req='1' then
			case bus_addr(3 downto 0) is
				when "0000" | "0001" | "0010" | "0011" |
					  "0100" | "0101" | "0110" | "0111" | -- decimals 0 to 11, to command the channels of the DAC
					  "1000" | "1001" | "1010" | "1011"
								=> for M in 0 to 7 loop
										RegA(Ch, M) <= bus_din(M);
									end loop;
									GenReset       <= '0';
				when "1100" => creg0d_i       <= bus_din(creg0d_i'range); -- decimal 12, to control the coincidence logic
									GenReset       <= '0';
				when "1101" => GenReset       <= '1'; -- decimal 13, to give the global reset command
				when "1110" => GenReset       <= '0'; -- decimal 14, to give the DAC convert command
									B              <= '1';
				when others => GenReset       <= '0';
			end case;
		else
			B <= '0';
			GenReset <= '0';
		end if;
	end if;
end process;

process (RegA)
begin
	for I in 0 to 7 loop	OutReg0(I)  <= RegA( 0, I); end loop;
	for I in 0 to 7 loop	OutReg1(I)  <= RegA( 1, I); end loop;
	for I in 0 to 7 loop	OutReg2(I)  <= RegA( 2, I); end loop;
	for I in 0 to 7 loop	OutReg3(I)  <= RegA( 3, I); end loop;
	for I in 0 to 7 loop	OutReg4(I)  <= RegA( 4, I); end loop;
	for I in 0 to 7 loop	OutReg5(I)  <= RegA( 5, I); end loop;
	for I in 0 to 7 loop	OutReg6(I)  <= RegA( 6, I); end loop;
	for I in 0 to 7 loop	OutReg7(I)  <= RegA( 7, I); end loop;
	for I in 0 to 7 loop	OutReg8(I)  <= RegA( 8, I); end loop;
	for I in 0 to 7 loop	OutReg9(I)  <= RegA( 9, I); end loop;
	for I in 0 to 7 loop	OutReg10(I) <= RegA(10, I); end loop;
	for I in 0 to 7 loop	OutReg11(I) <= RegA(11, I); end loop;
end process;

   creg0d <= creg0d_i;


process(bus_addr, version, dev_id, Temp) 
begin
	bus_dout <= conv_std_logic_vector (0, 32);
	case bus_addr(1 downto 0) is
		when "11"   =>  bus_dout(Temp'range)     <= Temp;     -- decimal 3 or 15
		when "00"   =>  bus_dout(version'range)  <= version;  -- decimal 0 or 12 or 16
		when "01"   =>  bus_dout(dev_id'range)   <= dev_id;   -- decimal 1 or 15 or 17
		when others =>  bus_dout                 <= (others => '-');
	end case;
end process;

end;