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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:02:15 05/06/2008 
-- Design Name: 
-- Module Name:    pattern_sync - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity delay_module is
    Port ( reset : in STD_LOGIC;
	        clk160 : in STD_Logic;
	        signal_in : in  STD_LOGIC;
           signal_delayed : out  STD_LOGIC;
			  set_delay : in STD_LOGIC_VECTOR(4 downto 0));
end delay_module;

architecture Behavioral of delay_module is


-- Synplicity black box declaration
attribute syn_black_box : boolean;

signal sig1, sig2, sig3, sig5, sig6, sig7, sig8, sig9, sig10: std_logic;
signal sig4: std_logic_vector(31 downto 0);

attribute period: string;
attribute PERIOD of clk160: signal is "4ns";

begin

sig4(0) <= signal_in;

-- delay chain
delay_chain: for i in 1 to 31 generate
   process(reset, clk160, sig4)
   begin		
      if reset = '1' then
		    sig4(i) <= '0';
      elsif (clk160'event and clk160='1') then
	       sig4(i) <= sig4(i-1);
      end if;
   end process;
end generate;

-- fastpath idea: don't guide the 0 delay signal through the big mux or if zero delay
-- if the mux is used use an additional register
sig7 <= '1' when set_delay(4 downto 0)="00000" else '0';
process(clk160, reset, sig7)
begin
   if reset = '1' then
	   sig8 <= '0';
	elsif clk160'event and clk160 = '1' then
	   sig8 <= sig7;
	end if;
end process;



--mux_signal
--Mux to select delayed signal
--   signal_sync_delayed_0_mux : Mux32_bit
--		port map (
--			M => sig4(31 downto 0),
--			S => set_delay(4 downto 0),
--			O => signal_sync_delayed);
process(set_delay(4 downto 0), sig4(31 downto 0))
begin
   case (set_delay(4 downto 0)) is 
      when "00000" =>
         sig9 <= '0'; -- use fastpath instead
      when "00001" =>
                  sig9 <= sig4(0); -- shifted by one for fastpath so is a register after the mux possible
      when "00010" =>
                  sig9 <= sig4(1);
      when "00011" =>
                  sig9 <= sig4(2);
      when "00100" =>
                  sig9 <= sig4(3);
      when "00101" =>
                  sig9 <= sig4(4);
      when "00110" =>
                  sig9 <= sig4(5);
      when "00111" =>
                  sig9 <= sig4(6);
      when "01000" =>
                  sig9 <= sig4(7);
      when "01001" =>
                  sig9 <= sig4(8);
      when "01010" =>
                  sig9 <= sig4(9);
      when "01011" =>
                  sig9 <= sig4(10);
      when "01100" =>
                  sig9 <= sig4(11); 
      when "01101" =>
                  sig9 <= sig4(12);
      when "01110" =>
                  sig9 <= sig4(13);
      when "01111" =>
                  sig9 <= sig4(14);
      when "10000" =>
                  sig9 <= sig4(15);-- save registers for better timing
      when "10001" =>
                  sig9 <= sig4(16);
      when "10010" =>
                  sig9 <= sig4(17);
      when "10011" =>
                  sig9 <= sig4(18);
      when "10100" =>
                  sig9 <= sig4(19);
      when "10101" =>
                  sig9 <= sig4(20);
      when "10110" =>
                  sig9 <= sig4(21);
      when "10111" =>
                  sig9 <= sig4(22);
      when "11000" =>
                  sig9 <= sig4(23);
      when "11001" =>
                  sig9 <= sig4(24);
      when "11010" =>
                  sig9 <= sig4(25);
      when "11011" =>
                  sig9 <= sig4(26);
      when "11100" =>
                  sig9 <= sig4(27);
      when "11101" =>
                  sig9 <= sig4(28);
      when "11110" =>
                  sig9 <= sig4(29);
      when "11111" =>
                  sig9 <= sig4(30);
      when others =>
                  sig9 <= sig4(31);
   end case;
end process;

process(clk160, reset, sig9)
begin
   if reset = '1' then
	   sig10 <= '0';
	elsif clk160'event and clk160 = '1' then
	   sig10 <= sig9;
	end if;
end process;

signal_delayed <= sig4(0) when sig8 = '1' else sig10;  -- fastpath for sig4(0)

end Behavioral;