---------------------------------------------------------------------------------- -- Company: -- Engineer: Stefan Zimmer -- -- Create Date: 00:03:39 06/01/2008 -- Design Name: -- Module Name: clk_generator - Behavioral -- Project Name: CheshireCat -- Target Devices: FEB-FPGA -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity clk_generator is Port ( clk40_pad : in STD_LOGIC; clk40 : out STD_LOGIC; clk160 : out STD_LOGIC; clk120 : out STD_LOGIC; clk80 : out STD_LOGIC; clk_scsn: out STD_LOGIC; reset : in STD_LOGIC; locked: out std_logic); end clk_generator; architecture Behavioral of clk_generator is signal clk120_con, dummy, dummy2 : std_logic; -- clk signals without any phase relation signal clk40_con, clk80_con : std_logic; -- feedback for clk160 signal clk40_prebuf, clk120_prebuf, clk160_prebuf, clk_scsn_prebuf : std_logic; signal clk40_signal, clk120_signal, clk160_signal, clk_scsn_signal : std_logic; signal DCM1_locked_signal, DCM2_reset : std_logic; signal DCM2_locked_signal, DCM3_locked_signal, DCM4_locked_signal: std_logic; begin -- produce clk80_con make duty cycle correction (neccessary since LVDS quality -- over a long cable is not good) for the incomeing clock DCM_SP_inst1 : DCM -- do not reset this DCMs, so the other DCMs have a good clock after an reset generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 25.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => clk40_prebuf, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => clk80_con, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => DCM1_locked_signal, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk40_signal, -- DCM clock feedback CLKIN => clk40_pad, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => '0' -- DCM asynchronous reset input ); -- descew and produce clk160 DCM_SP_inst2 : DCM generic map ( CLKDV_DIVIDE => 4.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 6.25, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "2X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => open,--dummy2, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => clk160_prebuf, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => DCM2_locked_signal, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk160_signal, -- DCM clock feedback CLKIN => clk80_con, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => DCM2_reset -- DCM asynchronous reset input ); DCM2_reset <= reset or (not DCM1_locked_signal); -- clk120 produce DCM_SP_inst3 : DCM generic map ( CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 3, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 25.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => clk_scsn_prebuf, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => clk120_con, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => DCM3_locked_signal, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk_scsn_signal, -- DCM clock feedback CLKIN => clk40_signal, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => reset -- DCM asynchronous reset input ); -- clk120 deskew and produce clk40 for locking DCM_SP_inst4 : DCM generic map ( CLKDV_DIVIDE => 3.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 3, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 8.33, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for -- frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE port map ( CLK0 => clk120_prebuf, -- 0 degree DCM CLK ouptput CLK180 => open, -- 180 degree DCM CLK output CLK270 => open, -- 270 degree DCM CLK output CLK2X => open, -- 2X DCM CLK output CLK2X180 => open, -- 2X, 180 degree DCM CLK out CLK90 => open, -- 90 degree DCM CLK output CLKDV => clk40_con, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => open, -- DCM CLK synthesis out (M/D) CLKFX180 => open, -- 180 degree CLK synthesis out LOCKED => DCM4_locked_signal, -- DCM LOCK status output PSDONE => open, -- Dynamic phase adjust done output STATUS => open, -- 8-bit DCM status bits output CLKFB => clk120_signal, -- DCM clock feedback CLKIN => clk120_con, -- Clock input (from IBUFG, BUFG or DCM) PSCLK => open, -- Dynamic phase adjust clock input PSEN => open, -- Dynamic phase adjust enable input PSINCDEC => open, -- Dynamic phase adjust increment/decrement RST => reset -- DCM asynchronous reset input ); BUFG_inst_clk120 : BUFG port map ( O => clk120_signal, -- Clock buffer output I => clk120_prebuf -- Clock buffer input ); BUFG_inst_clk40 : BUFG port map ( O => clk40_signal, -- Clock buffer output I => clk40_prebuf -- Clock buffer input ); BUFG_inst_clk_scsn : BUFG port map ( O => clk_scsn_signal, -- Clock buffer output I => clk_scsn_prebuf -- Clock buffer input ); BUFG_inst_clk160 : BUFG port map ( O => clk160_signal, -- Clock buffer output I => clk160_prebuf -- Clock buffer input ); clk40 <= clk40_signal; clk80 <= '0'; clk120 <= clk120_con; clk160 <= clk160_signal; clk_scsn <= clk_scsn_signal; locked <= DCM1_locked_signal and DCM2_locked_signal and DCM3_locked_signal and DCM4_locked_signal; end Behavioral;