----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Stefan Zimmer
-- 
-- Create Date:    17:21:29 05/17/2008 
-- Design Name: 
-- Module Name:    clk_enable_logic - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: enabels the different clk160 cycles with respect to clk40
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_enable_logic is
    Port ( clk160 : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk40 : in  STD_LOGIC;
			  select_offset : in STD_LOGIC_vector(1 downto 0);
           en0deg : out  STD_LOGIC; -- when using en_0deg think of: after a reset there is no en_0deg in the first cycle
           en90deg : out  STD_LOGIC;
           en180deg : out  STD_LOGIC;
           en270deg : out  STD_LOGIC);
end clk_enable_logic;

architecture Behavioral of clk_enable_logic is

signal sig1, sig2, sig3, sig4, sig5,sig6,sig7, sig8, sig9 : std_logic;
signal sig10, sig11, sig12, sig13a, sig13b, sig14, sig15, sig16, sig17 : std_logic;
signal sig18, sig19, sig20 : std_logic;
attribute period: string;
attribute PERIOD of clk160: signal is "3ns";
attribute PERIOD of clk40: signal is "3ns";

begin

-- lock to the falling edge of clk40
-- to avoid having a clk160 falling edge register behind a clk160 rising edge register
process(clk40, reset, sig4)
begin
   if reset = '1' or sig4 = '1' then
	   sig1 <= '0';
   elsif clk40'event and clk40='0' then
	   sig1 <= '1';
	end if;
end process;

process(clk160, reset, sig1)
begin
   if reset = '1' then
	   sig2 <= '0'; 
	elsif clk160'event and clk160 = '0' then
	   sig2 <= sig1;
	end if;
end process;

process(clk160, reset, sig2)
begin
   if reset = '1' then
	   sig3 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig3 <= sig2;
	end if;
end process;

-- edge detection
sig4 <= sig2 and (not sig3);

process(clk160, reset, sig4)
begin
   if reset = '1' then
	   sig5 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig5 <= sig4;
   end if;
end process;

process(clk160, reset, sig5)
begin
   if reset = '1' then
	   sig6 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig6 <= sig5;
	end if;
end process;

process(clk160, reset, sig6)
begin
   if reset = '1' then
	   sig7 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig7 <= sig6;
	end if;
end process;

process(clk160, reset, sig7)
begin
   if reset = '1' then
	   sig8 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig8 <= sig7;
	end if;
end process;

process(clk160, reset, sig8)
begin
   if reset = '1' then
	   sig9 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig9 <= sig8;
	end if;
end process;

-- mux select offset
process(select_offset(1), sig6, sig7, sig8, sig9, clk160, reset)
begin
   case (select_offset(1)) is 
      when '0' =>
         sig13a <= sig6;
      when '1' =>
         sig13a <= sig8;
      when others =>
         sig13a <= '0';
   end case;
end process;

-- additional register for setup and hold times
process(clk160, reset, sig13a)
begin
	if reset = '1' then
	   sig18 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig18 <= sig13a;
	end if;
end process;

process(clk160, reset, sig18)
begin
	if reset = '1' then
	   sig19 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig19 <= sig18;
	end if;
end process;						

process(clk160, reset, sig19)
begin
	if reset = '1' then
	   sig20 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig20 <= sig19;
	end if;
end process;						

-- mux select offset
process(select_offset(0), sig19, sig20, clk160, reset)
begin
   case (select_offset(0)) is 
      when '0' =>
         sig13b <= sig19;
      when '1' =>
         sig13b <= sig20;
      when others =>
         sig13b <= '0';
   end case;
end process;

process(clk160, reset, sig13b)
begin
	if reset = '1' then
	   sig14 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig14 <= sig13b;
	end if;
end process;			

--process(clk160, reset, sig13)
--begin
--   if reset = '1' then
--	   sig14 <= '0';
--	elsif clk160'event and clk160 = '0' then
--	   sig14 <= sig13;
--	end if;
--end process;	

process(clk160, reset, sig14)
begin
   if reset = '1' then
	   sig15 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig15 <= sig14;
	end if;
end process;

process(clk160, reset, sig15)
begin
   if reset = '1' then
	   sig16 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig16 <= sig15;
	end if;
end process;

process(clk160, reset, sig16)
begin
   if reset = '1' then
	   sig17 <= '0';
	elsif clk160'event and clk160 = '0' then
	   sig17 <= sig16;
	end if;
end process;

en270deg <= sig14;
en0deg <= sig15;
en90deg <= sig16;
en180deg <= sig17;

end Behavioral;