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-- Company: 
-- Engineer: 
-- 
-- Create Date:    05/12/2009 
-- Design Name: 
-- Module Name:    Veto_Logic - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Veto_Logic is
    Port ( clk : in  STD_LOGIC;
           reset: in STD_LOGIC;
           enable: in STD_LOGIC;
           sig_in: in STD_LOGIC;
           veto: out STD_LOGIC;
           veto_duration: in STD_LOGIC_VECTOR(7 downto 0)
          );

end Veto_Logic;

architecture Behavioral of Veto_Logic is

signal counter : std_logic_vector(7 downto 0);
signal creset : std_logic;

signal veto_active : STD_LOGIC;

begin
  process(clk, creset)
  begin
    if creset = '1' then
      counter <= ( others => '0');
    elsif clk'event and clk = '1' then
      counter <= counter + '1';
    end if;
  end process;

creset <= not veto_active;

process(clk, reset)
  begin
    if reset = '1' then
      veto_active <= '0';
    elsif clk'event and clk='1' then
      if sig_in = '1' and enable = '1' then
        veto_active <= '1';
      elsif counter = veto_duration then
        veto_active <= '0';
      end if;
    end if;
  end process;
  
veto <= veto_active;
  
end Behavioral;