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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:13:44 05/31/2008 
-- Design Name: 
-- Module Name:    Temp_Controll - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Temp_Controll is
    Port ( clk40 : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           D : inout  STD_LOGIC;
           SCK : out  STD_LOGIC;
           Temp : out  STD_LOGIC_VECTOR (13 downto 0));
end Temp_Controll;

architecture Behavioral of Temp_Controll is

COMPONENT Temperature
	PORT(
		Clk : IN std_logic;
		Reset : IN std_logic;    
		Data : INOUT std_logic;      
		Sck : OUT std_logic;
	   Busy : OUT std_logic;
   	Temp : OUT std_logic_vector(13 downto 0)
	);
END COMPONENT;

COMPONENT AutoReset
	PORT(
		BusyIn : IN std_logic;
		Clk : IN std_logic;          
		AutoReset : OUT std_logic
		);
END COMPONENT;

signal DataTemp, SckTemp, AutoResTemp: std_logic;
signal ResetTemp, BusyTemp : std_logic;


begin

ResetTemp <= AutoResTemp or reset;

TemperatureSensor: Temperature
    port map ( Data  => DataTemp,
					Sck   => SckTemp,
					Clk   => Clk40,
					Reset => ResetTemp,
					Busy  => BusyTemp,
					Temp  => Temp);

AutoResetTemp : AutoReset
    port map ( BusyIn    => BusyTemp,
					AutoReset => AutoResTemp,
					Clk       => Clk40);

D   <= DataTemp;
Sck <= SckTemp;

end Behavioral;