library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SHAPER is
    Port (D     : in  STD_LOGIC;
			 RESET : in  STD_LOGIC;
			 CLK : in  STD_LOGIC;
          Q : out STD_LOGIC);
end SHAPER;

architecture Behavioral of SHAPER is
	signal Q1  : STD_LOGIC;	
	signal Q2  : STD_LOGIC;
	signal Q3  : STD_LOGIC;
	signal RIN : STD_LOGIC;

	component DFLIPFLOP
		port (D     : in  STD_LOGIC;
				RESET : in  STD_LOGIC;
				CLK   : in  STD_LOGIC;
				Q     : out STD_LOGIC);
	end component;
	
begin
	SHAPERMODULE0 : DFLIPFLOP
		port map(D=>'1',RESET=>RIN,CLK=>D,Q=>Q1);

	SHAPERMODULE1 : DFLIPFLOP
		port map(D=>Q1,RESET=>RESET,CLK=>CLK,Q=>Q2);

	SHAPERMODULE2 : DFLIPFLOP
		port map(D=>Q2,RESET=>RESET,CLK=>CLK,Q=>Q3);
		
	ANDGATE1 : process(D,Q3,RESET)
		begin 
		case RESET is
			when '1' => RIN <= '1';
			when others => RIN <= Q3 and (not D);
		end case;
	end process;

	ANDGATE2 : process(Q2,Q3)
		begin 
		 Q <= Q2 and (not Q3);
	end process;
	
end Behavioral;