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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:22:19 06/26/2008 
-- Design Name: 
-- Module Name:    Pulser - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Pulser is
    Port ( clk40 : in  STD_LOGIC;
           pause_after_puls : in  STD_LOGIC_VECTOR (7 downto 0);
           puls : out  STD_LOGIC;
			  pulser_en : in std_logic;
			  reset : in STD_LOGIC);
end Pulser;

architecture Behavioral of Pulser is

signal counter : std_logic_vector(7 downto 0);
signal counter_reset : std_logic;
signal comperator : std_logic;

begin
   process(counter, reset, clk40)
   begin
	   if reset = '1' then
		   counter <= "00000000";
		elsif clk40'event and clk40 = '1' then
		   if counter_reset = '1' then
			   counter <= "00000000";
			else
			   counter <= counter + '1';
			end if;
		end if;
   end process;

   comperator <= '1' when counter = pause_after_puls else '0'; 
   process(comperator, clk40, reset, pulser_en)
	begin
	  if reset = '1' then
		   counter_reset <= '0';
		elsif clk40'event and clk40 = '0' then
		   counter_reset <= comperator;
		end if;
	end process;
	
	process(pulser_en, clk40, reset, comperator)
	begin
	   if reset = '1' then
		   puls <= '0';
		elsif clk40'event and clk40 = '1' then
		   puls <= comperator and pulser_en;
		end if;
	end process;
end Behavioral;