LIBRARY ieee; USE IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.VComponents.all; use std.textio.all; ENTITY PreTriggerTB IS generic (Tperiod : time := 25 ns); END PreTriggerTB; ARCHITECTURE behavior OF PreTriggerTB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT PreTrigger Generic( device_id : Integer := 1; version_id : Integer := 1); PORT( ClkP : in STD_LOGIC; -- connector to the control board ClkN : in STD_LOGIC; ScsnInP : in STD_LOGIC; ScsnInN : in STD_LOGIC; SelectorP : in STD_LOGIC; SelectorN : in STD_LOGIC; KoinzP : out STD_LOGIC; KoinzN : out STD_LOGIC; SDA : out STD_LOGIC; -- DAC SCL : out STD_LOGIC; D : inout STD_LOGIC; -- Temperature Sck : out STD_LOGIC; -- input signals from 12 detectors DET0p : in STD_LOGIC; DET0n : in STD_LOGIC; DET1p : in STD_LOGIC; DET1n : in STD_LOGIC; DET2p : in STD_LOGIC; DET2n : in STD_LOGIC; DET3p : in STD_LOGIC; DET3n : in STD_LOGIC; DET4p : in STD_LOGIC; DET4n : in STD_LOGIC; DET5p : in STD_LOGIC; DET5n : in STD_LOGIC; DET6p : in STD_LOGIC; DET6n : in STD_LOGIC; DET7p : in STD_LOGIC; DET7n : in STD_LOGIC; DET8p : in STD_LOGIC; DET8n : in STD_LOGIC; DET9p : in STD_LOGIC; DET9n : in STD_LOGIC; DET10p : in STD_LOGIC; DET10n : in STD_LOGIC; DET11p : in STD_LOGIC; DET11n : in STD_LOGIC ); END COMPONENT; component IBUFDS port (I : in STD_LOGIC; IB : in STD_LOGIC; O : out STD_LOGIC); end component; component OBUFDS port (I : in STD_LOGIC; O : out STD_LOGIC; OB : out STD_LOGIC); end component; COMPONENT ser_int generic ( wait_delay : integer := 34; --100 init_delay : integer := 1365; --4095 file_in : string := "C:\Documents and Settings\Massimiliano\My Documents\Repository\PreTrigger\sc_send.txt"; file_out : string := "C:\Documents and Settings\Massimiliano\My Documents\Repository\PreTrigger\sc_recv.txt" ); PORT( reset_n : IN std_logic; clkP : IN std_logic; clkN : IN std_logic; ready : IN std_logic; ser0din : IN std_logic; ser0dout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL SelectorP : std_logic; SIGNAL SelectorN : std_logic; SIGNAL ClkP : std_logic := '1'; SIGNAL ClkN : std_logic := '0'; SIGNAL reset_n : std_logic; SIGNAL ready : std_logic := '0'; SIGNAL KoinzP : std_logic; SIGNAL KoinzN : std_logic; SIGNAL ser0_din : std_logic; SIGNAL ser0_dout : std_logic; SIGNAL ser0_dout_p : std_logic; SIGNAL ser0_dout_n : std_logic; SIGNAL ser0_dout_c : std_logic; SIGNAL DET0p : std_logic := '0'; SIGNAL DET0n : std_logic := '1'; SIGNAL DET1p : std_logic := '0'; SIGNAL DET1n : std_logic := '1'; SIGNAL DET2p : std_logic := '0'; SIGNAL DET2n : std_logic := '1'; SIGNAL DET3p : std_logic := '0'; SIGNAL DET3n : std_logic := '1'; SIGNAL DET4p : std_logic := '0'; SIGNAL DET4n : std_logic := '1'; SIGNAL DET5p : std_logic := '0'; SIGNAL DET5n : std_logic := '1'; SIGNAL DET6p : std_logic := '0'; SIGNAL DET6n : std_logic := '1'; SIGNAL DET7p : std_logic := '0'; SIGNAL DET7n : std_logic := '1'; SIGNAL DET8p : std_logic := '0'; SIGNAL DET8n : std_logic := '1'; SIGNAL DET9p : std_logic := '0'; SIGNAL DET9n : std_logic := '1'; SIGNAL DET10p : std_logic := '0'; SIGNAL DET10n : std_logic := '1'; SIGNAL DET11p : std_logic := '0'; SIGNAL DET11n : std_logic := '1'; --Outputs signal SDA : STD_LOGIC; signal SCL : STD_LOGIC; signal D : STD_LOGIC; signal Sck : STD_LOGIC; signal My : STD_LOGIC; BEGIN scsnmast: ser_int PORT MAP( reset_n => reset_n, ClkP => ClkP, ClkN => ClkN, ready => ready, ser0din => ser0_din, ser0dout => ser0_dout ); SCSN: OBUFDS port map ( I => ser0_dout_c, O => ser0_dout_p, OB => ser0_dout_n); ModeMaster: process (SelectorP, ser0_dout, My) begin if SelectorP='1' then ser0_dout_c <= ser0_dout; else ser0_dout_c <= My; end if; end process; ScsnCnv: IBUFDS port map ( I => KoinzP, IB => KoinzN, O => ser0_din); -- Instantiate the Unit Under Test (UUT) uut: PreTrigger PORT MAP( ClkP => ClkP, ClkN => ClkN, SelectorP => SelectorP, SelectorN => SelectorN, SDA => SDA, SCL => SCL, D => D, Sck => Sck, ScsnInP => ser0_dout_p, ScsnInN => ser0_dout_n, KoinzP => KoinzP, KoinzN => KoinzN, -- input signals from 12 detectors DET0p => DET0p, DET0n => DET0n, DET1p => DET1p, DET1n => DET1n, DET2p => DET2p, DET2n => DET2n, DET3p => DET3p, DET3n => DET3n, DET4p => DET4p, DET4n => DET4n, DET5p => DET5p, DET5n => DET5n, DET6p => DET6p, DET6n => DET6n, DET7p => DET7p, DET7n => DET7n, DET8p => DET8p, DET8n => DET8n, DET9p => DET9p, DET9n => DET9n, DET10p => DET10p, DET10n => DET10n, DET11p => DET11p, DET11n => DET11n ); reset_n <= '0' after 0 us, '1' after 1 us, '0' after 2 us, '1' after 3 us; DET0p <= '1' after 300 us, '0' after 301 us; DET0n <= '0' after 300 us, '1' after 301 us; DET1p <= '1' after 300 us, '0' after 301 us; DET1n <= '0' after 300 us, '1' after 301 us; DET2p <= '1' after 300 us, '0' after 301 us; DET2n <= '0' after 300 us, '1' after 301 us; DET3p <= '1' after 300 us, '0' after 301 us; DET3n <= '0' after 300 us, '1' after 301 us; DET4p <= '1' after 300 us, '0' after 301 us; DET4n <= '0' after 300 us, '1' after 301 us; DET5p <= '1' after 300 us, '0' after 301 us; DET5n <= '0' after 300 us, '1' after 301 us; DET6p <= '1' after 300 us, '0' after 301 us; DET6n <= '0' after 300 us, '1' after 301 us; DET7p <= '1' after 300 us, '0' after 301 us; DET7n <= '0' after 300 us, '1' after 301 us; DET8p <= '1' after 300 us, '0' after 301 us; DET8n <= '0' after 300 us, '1' after 301 us; DET9p <= '1' after 300 us, '0' after 301 us; DET9n <= '0' after 300 us, '1' after 301 us; DET10p <= '1' after 300 us, '0' after 301 us; DET10n <= '0' after 300 us, '1' after 301 us; DET11p <= '1' after 300 us, '0' after 301 us; DET11n <= '0' after 300 us, '1' after 301 us; ClkP <= not ClkP after Tperiod/2; ClkN <= not ClkP; SelectorP <= '0' after 0 us, '1' after 3 us, '0' after 290 us, '1' after 310 us; SelectorN <= not SelectorP; My <= '1' after 0 us, -- reset signal when Selector is high '0' after 1 us, '1' after 2 us, '0' after 3 us; END;