---------------------------------------------------------------------------------- -- Company: -- Engineer: Stefan Zimmer -- -- Create Date: 19:15:04 04/16/2008 -- Design Name: -- Module Name: FEBFPGA - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Design for the FEB boxes. -- The asyncronous inputs from V0 or T0 are syncronized into the clk160 domain. -- This is done via a Syncronization circuit so that no setup and hold time problematics can -- occure. So the desing cannot be disturbed by oscillating registers. -- It is also possible to delay the individual channels to be able to trigger -- on coincidences. -- For diagnostic there is a logic analyzer as well as different counters implemented. -- The coincidence counter logic could not be implemented since the FPGA is to small. An offline -- simulation could be fine. Or the timing analyzer can be replaced by a coincidence logic. -- The DAC can be set to determine the trigger thresholds. -- It is also possible to read out the temperature of the temperature sensor. -- The Concentrator Box design determines if the Design is in the Trigger or in the -- configuration mode. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.VComponents.all; entity FEBFPGA is Port ( Clk : in STD_LOGIC; -- connector to the control board ScsnIn : in STD_LOGIC; Selector : in STD_LOGIC; Koinz : out STD_LOGIC; LED2 : out STD_LOGIC; LED3 : out STD_LOGIC; T1 : out STD_LOGIC; -- Probe Points at the FEB board T2 : out STD_LOGIC; T3 : out STD_LOGIC; T4 : out STD_LOGIC; SDA : out STD_LOGIC; -- DAC SCL : out STD_LOGIC; D : inout STD_LOGIC; -- Temperature Sck : out STD_LOGIC; DET0p : in STD_LOGIC; -- input signals from 12 detectors DET0n : in STD_LOGIC; DET1p : in STD_LOGIC; DET1n : in STD_LOGIC; DET2p : in STD_LOGIC; DET2n : in STD_LOGIC; DET3p : in STD_LOGIC; DET3n : in STD_LOGIC; DET4p : in STD_LOGIC; DET4n : in STD_LOGIC; DET5p : in STD_LOGIC; DET5n : in STD_LOGIC; DET6p : in STD_LOGIC; DET6n : in STD_LOGIC; DET7p : in STD_LOGIC; DET7n : in STD_LOGIC; DET8p : in STD_LOGIC; DET8n : in STD_LOGIC; DET9p : in STD_LOGIC; DET9n : in STD_LOGIC; DET10p : in STD_LOGIC; DET10n : in STD_LOGIC; DET11p : in STD_LOGIC; DET11n : in STD_LOGIC); end FEBFPGA; architecture Behavioral of FEBFPGA is component IBUFDS port (I : in STD_LOGIC; IB : in STD_LOGIC; O : out STD_LOGIC); end component; component OBUFDS port (I : in STD_LOGIC; O : out STD_LOGIC; OB : out STD_LOGIC); end component; COMPONENT mcm_network_interface PORT( ser0_din : IN std_logic; ser1_din : IN std_logic; bus_din : IN std_logic_vector(31 downto 0); bus_ack : IN std_logic; reset_n : IN std_logic; clk_buf : IN std_logic; clk : IN std_logic; ser0_dout : OUT std_logic; ser1_dout : OUT std_logic; bus_addr : OUT std_logic_vector(15 downto 0); bus_dout : OUT std_logic_vector(31 downto 0); bus_req : OUT std_logic; bus_we : OUT std_logic; chipRST_n : OUT std_logic; clk_buf_disable : OUT std_logic ); END COMPONENT; COMPONENT clk_generator PORT( clk40_pad : IN std_logic; reset : IN std_logic; locked : out std_logic; clk40 : OUT std_logic; clk160 : OUT std_logic; clk120 : OUT std_logic; clk_scsn: out std_logic; clk80 : OUT std_logic ); END COMPONENT; COMPONENT clk_enable_logic PORT( clk160 : IN std_logic; reset : IN std_logic; clk40 : IN std_logic; select_offset : IN std_logic_vector(1 downto 0); en0deg : OUT std_logic; en90deg : OUT std_logic; en180deg : OUT std_logic; en270deg : OUT std_logic ); END COMPONENT; COMPONENT Temp_Controll PORT( clk40 : IN std_logic; reset : IN std_logic; D : INOUT std_logic; SCK : OUT std_logic; Temp : OUT std_logic_vector(13 downto 0) ); END COMPONENT; COMPONENT DAC_Controll PORT( clk40 : IN std_logic; reset : IN std_logic; update : IN std_logic; DAC_value_0 : IN std_logic_vector(7 downto 0); DAC_value_1 : IN std_logic_vector(7 downto 0); DAC_value_2 : IN std_logic_vector(7 downto 0); DAC_value_3 : IN std_logic_vector(7 downto 0); DAC_value_4 : IN std_logic_vector(7 downto 0); DAC_value_5 : IN std_logic_vector(7 downto 0); DAC_value_6 : IN std_logic_vector(7 downto 0); DAC_value_7 : IN std_logic_vector(7 downto 0); DAC_value_8 : IN std_logic_vector(7 downto 0); DAC_value_9 : IN std_logic_vector(7 downto 0); DAC_value_10 : IN std_logic_vector(7 downto 0); DAC_value_11 : IN std_logic_vector(7 downto 0); SDA : OUT std_logic; SCL : OUT std_logic ); END COMPONENT; COMPONENT Counter_64times48Bit PORT( counter_en : IN std_logic_vector(62 downto 0); clk : IN std_logic; clk160 : IN std_logic; clk_scsn : IN std_logic; readout_req : IN std_logic; reset : IN std_logic; readout_counter_addr : IN std_logic_vector(5 downto 0); readout_done : OUT std_logic; counter_value : OUT std_logic_vector(47 downto 0); debug_signal : OUT std_logic_vector(7 downto 0) ); END COMPONENT; COMPONENT Pulser PORT( clk40 : IN std_logic; pause_after_puls : IN std_logic_vector(7 downto 0); reset : IN std_logic; puls : OUT std_logic; pulser_en : in std_logic ); END COMPONENT; COMPONENT scintillator_trigger PORT( scintillator : IN std_logic; reset : IN std_logic; veto: in std_logic; clk : IN std_logic; clk_enoutdeg_reg : IN std_logic; clk_enoutplus90deg_reg : IN std_logic; clk_enoutplus180deg_reg : IN std_logic; clk_enoutplus270deg_reg : IN std_logic; to_SM : OUT std_logic ); END COMPONENT; COMPONENT delay_module PORT( reset : IN std_logic; clk160 : IN std_logic; signal_in : IN std_logic; set_delay : IN std_logic_vector(4 downto 0); signal_delayed : OUT std_logic ); END COMPONENT; component Veto_Logic Port ( clk : in STD_LOGIC; reset: in STD_LOGIC; enable: in STD_LOGIC; sig_in: in STD_LOGIC; veto: out STD_LOGIC; veto_duration: in STD_LOGIC_VECTOR(7 downto 0) ); end component; COMPONENT LUT_module_FEB PORT( DET_signals : IN std_logic_vector(11 downto 0); clk160 : IN std_logic; clk120 : IN std_logic; clk_ro_en_reg : IN std_logic; reset : IN std_logic; LUT_address : IN std_logic_vector(11 downto 0); LUT_data_in : IN std_logic_vector(1 downto 0); LUT_we : IN std_logic; trigger : OUT std_logic_vector(1 downto 0); LUT_data_out : OUT std_logic_vector(1 downto 0) ); END COMPONENT; COMPONENT serializer_clk80 PORT( data_paralell : IN std_logic_vector(1 downto 0); clk160 : IN std_logic; reset : IN std_logic; input_edge_marker_reg : IN std_logic; data_serial : OUT std_logic ); END COMPONENT; component timestamp_timing_analyzer Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; -- normal sync reset design reset activate : in STD_LOGIC; -- keep active high whenever you want to be sensitive for triggers done : out STD_LOGIC; clear : in STD_LOGIC; -- clears the done; next activate will start recording signals : in STD_LOGIC_VECTOR(3 downto 0); trigger_mask: in STD_LOGIC_VECTOR(31 downto 0); timestamp: in STD_LOGIC_VECTOR(11 downto 0); clk_scsn : in STD_LOGIC; readout_value : out STD_LOGIC_VECTOR (31 downto 0); readout_address : in STD_LOGIC_VECTOR (8 downto 0) ); end component; component timestamp_timing_analyzer_sigdis_26bit Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; -- normal sync reset design reset activate : in STD_LOGIC; -- keep active high whenever you want to be sensitive for triggers done : out STD_LOGIC; clear : in STD_LOGIC; -- clears the done; next activate will start recording signals : in STD_LOGIC_VECTOR(2 downto 0); trigger_mask: in STD_LOGIC_VECTOR(2 downto 0); timestamp: in STD_LOGIC_VECTOR(23 downto 0); clk_scsn : in STD_LOGIC; readout_value : out STD_LOGIC_VECTOR (31 downto 0); readout_address : in STD_LOGIC_VECTOR (8 downto 0) ); end component; COMPONENT timing_analyze_module PORT( activate : IN std_logic; reset : IN std_logic; clear : IN std_logic; signals : IN std_logic_vector(15 downto 0); clk : IN std_logic; clk_scsn : IN std_logic; readout_address : IN std_logic_vector(8 downto 0); done : OUT std_logic; readout_value : OUT std_logic_vector(31 downto 0); trigger_mask : IN std_logic_vector(31 downto 0) ); END COMPONENT; signal reset, reset_n, hardware_reset : std_logic; -- input signals type type_DET is array(0 to 11) of std_logic; signal DET : type_DET; signal SCSNIN_signal, SCSNOUT_signal : std_logic; signal KOINZ_signal : std_logic; -- clock signals signal clk160, Clk120, clk80, clk40: std_logic; signal clk_en0deg, clk_en90deg, clk_en180deg, clk_en270deg : std_logic; signal clk_en0deg_prebuf, clk_en90deg_prebuf, clk_en180deg_prebuf, clk_en270deg_prebuf : std_logic; type type_DET_clk_en is array (0 to 11) of std_logic; signal DET_clk_en0deg : type_DET_clk_en; signal DET_clk_en90deg : type_DET_clk_en; signal DET_clk_en180deg : type_DET_clk_en; signal DET_clk_en270deg : type_DET_clk_en; signal clk_scsn : std_logic; -- data signals signal zero_signal: std_logic_vector(63 downto 0) := X"0000000000000000"; signal scsn_addr_signal: std_logic_vector(15 downto 0); signal scsn_dataout_signal: std_logic_vector(31 downto 0); signal scsn_datain_signal: std_logic_vector(31 downto 0); signal scsn_bus_req_signal: std_logic; signal scsn_bus_req_signal_buf : std_logic; signal scsn_we_signal: std_logic; signal scsn_bus_ack_signal: std_logic; signal scsn_out_signal: std_logic; signal scsn_out_signal_i: std_logic; signal scsn_in_signal: std_logic; signal temp_signal: std_logic_vector(13 downto 0); signal counter_value_signal: std_logic_vector(47 downto 0); signal counter_reset : std_logic; signal counter_readout_done_signal : std_logic; signal readout_counter_addr_signal : std_logic_vector(5 downto 0); signal LUT_data_in_signal : std_logic_vector(1 downto 0); signal LUT_address_signal : std_logic_vector(12 downto 0); signal LUT_we_signal : std_logic; signal serializer_en_signal : std_logic; signal pulser_signal: std_logic_vector(11 downto 0); signal locked_signal : std_logic; -- timing analyzer signals signal done_timing_analyze_signal: std_logic; signal clear_timing_analyze_reg_signal: std_logic; signal activate_timing_analyze_reg_signal: std_logic; signal timing_analyze_trigger_pattern_reg_signal: std_logic_vector(31 downto 0); signal readout_address_data_analyze_signal: std_logic_vector(8 downto 0); signal readout_value_data_analyze_signal: std_logic_vector(31 downto 0); signal readout_value_data_analyze_signal_reg: std_logic_vector(31 downto 0); -- scsn register signal threshold_update_reg_signal : std_logic; signal counter_readout_req_reg_signal: std_logic; signal counter_reset_reg_signal : std_logic; -- make additional register since timing fails because of routing type type_DET_threshold_reg_signal_prebuf is array (0 to 11) of std_logic_vector(7 downto 0); signal DET_threshold_reg_signal_prebuf: type_DET_threshold_reg_signal_prebuf; type type_DET_threshold_reg_signal is array (0 to 11) of std_logic_vector(7 downto 0); signal DET_threshold_reg_signal: type_DET_threshold_reg_signal; type type_DET_delay_reg_signal is array (0 to 11) of std_logic_vector(4 downto 0); signal DET_delay_reg_signal: type_DET_delay_reg_signal; type type_DET_phase_reg_signal is array (0 to 11) of std_logic_vector(1 downto 0); signal DET_phase_reg_signal : type_DET_phase_reg_signal; signal outphase_reg_signal : std_logic_vector(1 downto 0); signal pulser_mode_reg_signal : std_logic_vector(11 downto 0); signal pulser_en_reg_signal : std_logic_vector(11 downto 0); type type_pulser_pause_after_puls_reg_signal is array(0 to 11) of std_logic_vector(7 downto 0); signal pulser_pause_after_puls_reg_signal: type_pulser_pause_after_puls_reg_signal; -- trigger signals signal DET_sync_signal_from_scint_trigger : std_logic_vector(11 downto 0); signal DET_sync_signal_to_delay : std_logic_vector(11 downto 0); signal DET_sync_delayed_signal : std_logic_vector(11 downto 0); signal LUT_data_out_signal : std_logic_vector(1 downto 0); signal trigger_paralell : std_logic_vector(1 downto 0); signal DET_postpulser_signal : std_logic_vector(11 downto 0); -- veto signals signal veto : std_logic_vector(11 downto 0); signal veto_duration : std_logic_vector(7 downto 0); signal veto_combined : std_logic; signal veto_soft : STD_LOGIC; -- cabeling signals signal q, q_prereg: std_logic; signal analyzer_trigger0: std_logic_vector(15 downto 0); signal analyzer_trigger1: std_logic; signal analyzer_trigger2: std_logic; signal timestamp_reset : std_logic; signal timestamp_counter : std_logic_vector(23 downto 0); signal TA_clk : std_logic; signal TA_enable : std_logic; signal TA_active : std_logic; signal count_en : std_logic_vector(62 downto 0); signal test120: std_logic_vector(7 downto 0); begin -- clock counter; pulser for debugging process(clk160, reset, q_prereg) begin if reset = '1' then q_prereg <= '0'; elsif clk160'event and clk160 = '1' then q_prereg <= not q_prereg; end if; end process; -- Additional register for better timing process(clk160, reset, q_prereg) begin if reset = '1' then q <= '0'; elsif clk160'event and clk160 = '1' then q <= q_prereg; end if; end process; DET0_BUF: IBUFDS port map ( I => DET0p, IB => DET0n, O => DET(0)); DET1_BUF: IBUFDS port map ( I => DET1p, IB => DET1n, O => DET(1)); DET2_BUF: IBUFDS port map ( I => DET2p, IB => DET2n, O => DET(2)); DET3_BUF: IBUFDS port map ( I => DET3p, IB => DET3n, O => DET(3)); DET4_BUF: IBUFDS port map ( I => DET4p, IB => DET4n, O => DET(4)); DET5_BUF: IBUFDS port map ( I => DET5p, IB => DET5n, O => DET(5)); DET6_BUF: IBUFDS port map ( I => DET6p, IB => DET6n, O => DET(6)); DET7_BUF: IBUFDS port map ( I => DET7p, IB => DET7n, O => DET(7)); DET8_BUF: IBUFDS port map ( I => DET8p, IB => DET8n, O => DET(8)); DET9_BUF: IBUFDS port map ( I => DET9p, IB => DET9n, O => DET(9)); DET10_BUF: IBUFDS port map ( I => DET10p, IB => DET10n, O => DET(10)); DET11_BUF: IBUFDS port map ( I => DET11p, IB => DET11n, O => DET(11)); Inst_clk_generator: clk_generator PORT MAP( clk40_pad => clk, clk40 => clk40, clk160 => clk160, clk120 => clk120, clk80 => clk80, clk_scsn => clk_scsn, reset => reset, locked => locked_signal ); Inst_mcm_network_interface: mcm_network_interface PORT MAP( ser0_din => SCSNIN_signal, ser0_dout => SCSNOUT_signal, ser1_din => '0', ser1_dout => open , bus_addr => scsn_addr_signal, bus_dout => scsn_dataout_signal, bus_din => scsn_datain_signal, bus_req => scsn_bus_req_signal, bus_we => scsn_we_signal, bus_ack => scsn_bus_ack_signal, chipRST_n => reset_n, reset_n => '1', clk_buf_disable => open, -- to fine_delayed power, the clk can be switched off clk_buf => CLK_SCSN, -- the clock which can be switched off clk => CLK_SCSN ); reset <= hardware_reset; -- ############################################################################### -- ################### configuration ############################################# -- ############################################################################### -- automatically create the bus ack signal process(clk40, reset, scsn_bus_req_signal) begin if (reset='1') then scsn_bus_req_signal_buf <= '0'; elsif (clk40'event and clk40 = '1') then scsn_bus_req_signal_buf <= scsn_bus_req_signal; end if; end process; process(clk40, reset, scsn_bus_req_signal) begin if (reset='1') then scsn_bus_ack_signal <= '0'; elsif (clk40'event and clk40 = '1') then scsn_bus_ack_signal <= scsn_bus_req_signal_buf; end if; end process; process(scsn_we_signal, scsn_dataout_signal, scsn_addr_signal, temp_signal, counter_value_signal,counter_readout_done_signal ) begin -- some dummy readout for testing scsn communication if (scsn_addr_signal = 0) then scsn_datain_signal <= X"deadface"; elsif (scsn_addr_signal = 2) then scsn_datain_signal <=X"0000face"; -- read temp signals elsif (scsn_addr_signal = 1000) then scsn_datain_signal(13 downto 0) <= temp_signal(13 downto 0); scsn_datain_signal(15 downto 14) <= "00"; -- read out counter -- for bit 31 downto 0 use 64xx -- for bit 47 downto 32 use 128xx -- check if readout is allready done -- read counter values elsif (scsn_addr_signal(15 downto 6) = "0001100100") then scsn_datain_signal(31 downto 0) <= counter_value_signal(31 downto 0); elsif (scsn_addr_signal(15 downto 6) = "0011001000") then scsn_datain_signal(15 downto 0) <= counter_value_signal(47 downto 32); scsn_datain_signal(31 downto 16) <= zero_signal(31 downto 16); elsif (scsn_addr_signal = 52) then scsn_datain_signal(0) <= counter_readout_done_signal; scsn_datain_signal(31 downto 1) <= zero_signal(31 downto 1); -- read version elsif (scsn_addr_signal(15 downto 0) = "0000000010000001") then scsn_datain_signal(15 downto 0) <= X"ab12"; -- version -- Pulser En ( all 12 channels packed in a single SCSN read ) elsif (scsn_addr_signal = 3500) then scsn_datain_signal(11 downto 0) <= pulser_en_reg_signal; scsn_datain_signal(31 downto 12) <= zero_signal(31 downto 12); -- Pulser Mode ( all 12 channels packed in a single SCSN read ) elsif (scsn_addr_signal = 3300) then scsn_datain_signal(11 downto 0) <= pulser_mode_reg_signal; scsn_datain_signal(31 downto 12) <= zero_signal(31 downto 12); -- Pulser Pause ( readback not implemented yet ) -- Timing Analyzer Trigger Pattern elsif (scsn_addr_signal = 601) then scsn_datain_signal <= timing_analyze_trigger_pattern_reg_signal; -- read LUT elsif (scsn_addr_signal(15) = '1') then scsn_datain_signal(1 downto 0) <= LUT_data_out_signal(1 downto 0); scsn_datain_signal(31 downto 2) <= zero_signal(31 downto 2); -- timing analyze data elsif (scsn_addr_signal = 603) then scsn_datain_signal(0) <= done_timing_analyze_signal; scsn_datain_signal(31 downto 1) <= zero_signal(31 downto 1); elsif (scsn_addr_signal = 601) then scsn_datain_signal <= timing_analyze_trigger_pattern_reg_signal; -- addresses 16384 ... 16895 for the timing analyzer elsif (scsn_addr_signal(15 downto 14) = "01") then scsn_datain_signal(31 downto 0) <= readout_value_data_analyze_signal_reg(31 downto 0); -- DAC Thresholds elsif (scsn_addr_signal = 700) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(0); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 701) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(1); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 702) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(2); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 703) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(3); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 704) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(4); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 705) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(5); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 706) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(6); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 707) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(7); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 708) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(8); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 709) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(9); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 710) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(10); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); elsif (scsn_addr_signal = 711) then scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(11); scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); -- test elsif (scsn_addr_signal = 777) then scsn_datain_signal(7 downto 0) <= test120; scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); -- Input Delays elsif (scsn_addr_signal = 2200) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(0); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2201) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(1); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2202) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(2); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2203) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(3); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2204) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(4); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2205) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(5); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2206) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(6); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2207) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(7); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2208) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(8); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2209) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(9); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2210) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(10); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); elsif (scsn_addr_signal = 2211) then scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(11); scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); -- Input Sampling Phase ( all 12 channels packed in a single SCSN read ) elsif (scsn_addr_signal = 2100 ) then for ii in 0 to 11 loop scsn_datain_signal(2*ii+1 downto 2*ii) <= DET_phase_reg_signal(ii); end loop; -- ii scsn_datain_signal(31 downto 24) <= zero_signal(31 downto 24); end if; end process; -- Read threshold, delay, phase for input channels -- read_inputpars: for ii in 0 to 11 generate -- process(scsn_we_signal, scsn_dataout_signal, scsn_addr_signal, temp_signal, -- counter_value_signal,counter_readout_done_signal ) -- begin -- -- DAC Thresholds -- if (scsn_addr_signal = 800 + ii) then -- scsn_datain_signal(7 downto 0) <= DET_threshold_reg_signal(ii); -- scsn_datain_signal(31 downto 8) <= zero_signal(31 downto 8); -- -- Input Delays -- elsif (scsn_addr_signal = 3200 + ii) then -- scsn_datain_signal(4 downto 0) <= DET_delay_reg_signal(ii); -- scsn_datain_signal(31 downto 5) <= zero_signal(31 downto 5); -- -- Input Sampling Phase -- elsif (scsn_addr_signal = 3100 + ii) then -- scsn_datain_signal(1 downto 0) <= DET_phase_reg_signal(ii); -- scsn_datain_signal(31 downto 2) <= zero_signal(31 downto 2); -- end if; -- end process; -- end generate; -- clk shifter process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then outphase_reg_signal <= "00"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 99) then outphase_reg_signal <= scsn_dataout_signal(1 downto 0); end if; end process; -- clear timing analyze module (make it ready for the next activate) process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then clear_timing_analyze_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 600) then clear_timing_analyze_reg_signal <= scsn_dataout_signal(0); end if; end process; -- set trigger pattern for timing analyze module process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then timing_analyze_trigger_pattern_reg_signal <= X"00000000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 601) then timing_analyze_trigger_pattern_reg_signal <= scsn_dataout_signal(31 downto 0); end if; end process; -- activate timing analyze module process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then activate_timing_analyze_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 602) then activate_timing_analyze_reg_signal <= scsn_dataout_signal(0); end if; end process; -- set thresholds for the Detector inputs -- update DAC values to set thresholds process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then threshold_update_reg_signal <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 799) then threshold_update_reg_signal <= scsn_dataout_signal(0); end if; end process; -- set thresholds for the comperators thresholds: for ii in 0 to 11 generate -- additional buffer because of timing process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then DET_threshold_reg_signal(ii) <= "00000000"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_addr_signal = 700+ii ) then DET_threshold_reg_signal(ii) <= scsn_dataout_signal(7 downto 0); end if; end process; end generate; -- select phase for the puls shaper phase: for ii in 0 to 11 generate process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then DET_phase_reg_signal(ii) <= "00"; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 2100 + ii) then DET_phase_reg_signal(ii) <= scsn_dataout_signal(1 downto 0); end if; end process; end generate; -- set software veto process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then veto_soft <= '0'; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 122) then veto_soft <= scsn_dataout_signal(0); end if; end process; -- set veto duration process(clk_scsn, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then veto_duration <= X"00"; elsif (clk_scsn'event and clk_scsn = '1' and scsn_we_signal = '1' and scsn_addr_signal = 123) then veto_duration <= scsn_dataout_signal(7 downto 0); end if; end process; -- set veto duration process(clk120, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then test120 <= X"00"; elsif (clk120'event and clk120 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 777) then test120 <= scsn_dataout_signal(7 downto 0); end if; end process; -- select delay for an input signal delay: for ii in 0 to 11 generate process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then DET_delay_reg_signal(ii) <= "00000"; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 2200 + ii) then DET_delay_reg_signal(ii) <= scsn_dataout_signal(4 downto 0); end if; end process; end generate; -- pulser pulser_en_reg: for ii in 0 to 11 generate process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pulser_mode_reg_signal(ii) <= '0'; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 2300 + ii) then pulser_mode_reg_signal(ii) <= scsn_dataout_signal(0); end if; end process; process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pulser_pause_after_puls_reg_signal(ii) <= "00000000"; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 2400 + ii) then pulser_pause_after_puls_reg_signal(ii) <= scsn_dataout_signal(7 downto 0); end if; end process; process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then pulser_en_reg_signal(ii) <= '0'; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 2500 + ii) then pulser_en_reg_signal(ii) <= scsn_dataout_signal(0); end if; end process; end generate; -- Counter process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then counter_reset_reg_signal <= '0'; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 50) then counter_reset_reg_signal <= scsn_dataout_signal(0); end if; end process; process(clk40, scsn_we_signal, reset, scsn_dataout_signal, scsn_addr_signal) begin if (reset = '1') then counter_readout_req_reg_signal <= '0'; elsif (clk40'event and clk40 = '1' and scsn_we_signal = '1' and scsn_addr_signal = 51) then counter_readout_req_reg_signal <= scsn_dataout_signal(0); end if; end process; -- LUT configuration -- all addresses starting with "1000" & X"0000000" are reserved for the LUT -- be careful not all address bits are used so fare, due to hardware limitations LUT_data_in_signal(1 downto 0) <= scsn_dataout_signal(1 downto 0); LUT_address_signal(12 downto 0) <= scsn_addr_signal(12 downto 0); LUT_we_signal <='1' when (scsn_addr_signal(15) = '1' and scsn_we_signal = '1') else '0'; -- Inst_Temp_Controll: Temp_Controll PORT MAP( -- clk40 => clk40, -- reset => reset, -- D => D, -- SCK => SCK, -- Temp => temp_signal --); Inst_DAC_Controll: DAC_Controll PORT MAP( clk40 => clk40, reset => reset, update => Threshold_update_reg_signal, DAC_value_0 => DET_threshold_reg_signal(0), DAC_value_1 => DET_threshold_reg_signal(1), DAC_value_2 => DET_threshold_reg_signal(2), DAC_value_3 => DET_threshold_reg_signal(3), DAC_value_4 => DET_threshold_reg_signal(4), DAC_value_5 => DET_threshold_reg_signal(5), DAC_value_6 => DET_threshold_reg_signal(6), DAC_value_7 => DET_threshold_reg_signal(7), DAC_value_8 => DET_threshold_reg_signal(8), DAC_value_9 => DET_threshold_reg_signal(9), DAC_value_10 => DET_threshold_reg_signal(10), DAC_value_11 => DET_threshold_reg_signal(11), SDA => SDA, SCL => SCL ); -- input signals sync and delay and Pulser include pulser_generator_inst: for ii in 0 to 11 generate Inst_Pulser: Pulser PORT MAP( clk40 => clk40, pause_after_puls => pulser_pause_after_puls_reg_signal(ii), puls => pulser_signal(ii), pulser_en => pulser_en_reg_signal(ii), reset => reset ); -- input can be switched off by setting to pulser_mode and disable the pulser. -- it depends on the synthesis but in principle this saves one logic element in the trigger -- signal path. DET_postpulser_signal(ii) <= (DET(ii) and not pulser_mode_reg_signal(ii)) or (pulser_signal(ii) and pulser_mode_reg_signal(ii)); end generate; input_sync_and_delay: for ii in 0 to 11 generate Inst_clk_enable_logic: clk_enable_logic PORT MAP( clk160 => clk160, reset => reset, clk40 => clk40, select_offset => DET_phase_reg_signal(ii), en0deg => DET_clk_en0deg(ii), en90deg => DET_clk_en90deg(ii), en180deg => DET_clk_en180deg(ii), en270deg => DET_clk_en270deg(ii) ); Inst_iscintillator_trigger: scintillator_trigger PORT MAP( scintillator => DET_postpulser_signal(ii), reset => reset, veto => '0', -- veto_combined, clk => clk160, clk_enoutdeg_reg => DET_clk_en0deg(ii), clk_enoutplus90deg_reg => DET_clk_en90deg(ii), clk_enoutplus180deg_reg => DET_clk_en180deg(ii), clk_enoutplus270deg_reg => DET_clk_en270deg(ii), to_SM => DET_sync_signal_from_scint_trigger(ii) ); DET_sync_signal_to_delay(ii) <= DET_sync_signal_from_scint_trigger(ii); -- DET_sync_signal_to_delay(ii) <= DET_sync_signal_from_scint_trigger(ii) and not veto(ii); Inst_veto_logic: Veto_Logic Port Map( clk => clk40, reset => reset, enable => '1', sig_in => DET_sync_signal_from_scint_trigger(ii), veto => veto(ii), veto_duration => veto_duration ); Inst_delay_module: delay_module PORT MAP( reset => reset, clk160 => clk160, signal_in => DET_sync_signal_from_scint_trigger(ii), signal_delayed => DET_sync_delayed_signal(ii), set_delay => DET_delay_reg_signal(ii) ); end generate; veto_combined <= veto(7) or veto_soft; Inst_clk_enable_logic_output: clk_enable_logic PORT MAP( clk160 => clk160, reset => reset, clk40 => clk40, select_offset => outphase_reg_signal, en0deg => clk_en0deg, en90deg => clk_en90deg, en180deg => clk_en180deg, en270deg => clk_en270deg ); -- trigger logic Inst_LUT_module_FEB: LUT_module_FEB PORT MAP( DET_signals(11 downto 0) => DET_sync_delayed_signal(11 downto 0), trigger => trigger_paralell, clk160 => clk160, clk120 => clk_scsn, clk_ro_en_reg => clk_en270deg, reset => reset, LUT_address(11 downto 0) => LUT_address_signal(11 downto 0), LUT_data_in(1 downto 0) => LUT_data_in_signal(1 downto 0), LUT_we => LUT_we_signal, LUT_data_out => LUT_data_out_signal ); count_en(0) <= '1'; count_en(3 downto 1) <= DET_sync_delayed_signal(2 downto 0); count_en(4) <= DET_sync_delayed_signal(3); count_en(7 downto 5) <= DET_sync_delayed_signal(6 downto 4); count_en(8) <= DET_sync_delayed_signal(7); count_en(12 downto 9) <= DET_sync_delayed_signal(11 downto 8); count_en(13) <= trigger_paralell(0); -- and TA_active; count_en(14) <= trigger_paralell(1); count_en(62 downto 15) <= zero_signal(62 downto 15); -- monitoring counter_reset <= reset or counter_reset_reg_signal; -- address for counter readout readout_counter_addr_signal(5 downto 0) <= scsn_addr_signal(5 downto 0); Inst_Counter_64times48Bit: Counter_64times48Bit PORT MAP( counter_en(62 downto 0) => count_en(62 downto 0), clk => clk40, clk160 => clk160, clk_scsn => clk_scsn, readout_req => counter_readout_req_reg_signal, reset => counter_reset, readout_done => counter_readout_done_signal, readout_counter_addr => readout_counter_addr_signal, counter_value(47 downto 0) => counter_value_signal(47 downto 0) ); -- output -- the selector pin changes the output pin (Koinz) between -- trigger mode and configuration mode -- in trigger mode (Selector = 0 (low)) you issue a reset by -- rising SCSN_IN (SCSN_IN = '1') Output: process (SELECTOR, SCSNOUT_signal,SCSNIN) begin if Selector='1' then -- configuration mode KOINZ <= SCSNOUT_signal; SCSNIN_signal <= SCSNIN; hardware_reset <= '0'; else -- trigger mode KOINZ <= KOINZ_signal; SCSNIN_signal <= '0'; hardware_reset <= SCSNIN; end if; end process; Inst_serializer_clk80: serializer_clk80 PORT MAP( data_paralell => trigger_paralell , data_serial => KOINZ_signal, clk160 => clk160, reset => reset, input_edge_marker_reg => clk_en270deg ); -- address for timing analyze readout readout_address_data_analyze_signal <= scsn_addr_signal(8 downto 0); -- generate a trigger signals for the timing analyzer -- due to timing problems with a scintillator tirgger analyzer_trigger0(15 downto 1) <= (trigger_paralell & KOINZ_signal & DET_postpulser_signal) and timing_analyze_trigger_pattern_reg_signal(15 downto 1); analyzer_trigger0(0) <= q and timing_analyze_trigger_pattern_reg_signal(0); analyzer_trigger1 <= '1' when analyzer_trigger0 /= 0 else '0'; Inst_scintillator_trigger: scintillator_trigger PORT MAP( scintillator => analyzer_trigger1, reset => reset, veto => '0', clk => clk160, clk_enoutdeg_reg => clk_en0deg, clk_enoutplus90deg_reg => clk_en90deg, clk_enoutplus180deg_reg => clk_en180deg, clk_enoutplus270deg_reg => clk_en270deg, to_SM => analyzer_trigger2 ); --Inst_timestamp_analyzer: timestamp_timing_analyzer Port map( -- clk => clk160, -- reset => reset, -- activate => activate_timing_analyze_reg_signal, -- done => done_timing_analyze_signal, -- clear => clear_timing_analyze_reg_signal, -- signals(0) => DET_sync_delayed_signal(3), -- signals(1) => DET_sync_delayed_signal(7), -- signals(2) => trigger_paralell(0), -- signals(3) => KOINZ_signal, -- trigger_mask => timing_analyze_trigger_pattern_reg_signal(31 downto 0), -- timestamp => timestamp_counter(11 downto 0), -- clk_scsn => clk_scsn, -- readout_value => readout_value_data_analyze_signal, -- readout_address => readout_address_data_analyze_signal -- ); TA_clk <= DET_clk_en0deg(0); -- TA_clk <= clk40; --Inst_timestamp_analyzer: timestamp_timing_analyzer_sigdis_26bit Port map( -- clk => TA_clk, --reset => reset, -- activate => activate_timing_analyze_reg_signal, -- done => done_timing_analyze_signal, -- clear => clear_timing_analyze_reg_signal, -- --signals(0) => DET_sync_delayed_signal(3), -- --signals(1) => DET_sync_delayed_signal(7), -- signals(0) => DET_sync_signal_from_scint_trigger(0), -- --signals(1) => trigger_paralell(0), -- signals(1) => DET_sync_signal_from_scint_trigger(1), -- signals(2) => DET_sync_signal_from_scint_trigger(2), -- -- trigger_mask => timing_analyze_trigger_pattern_reg_signal(2 downto 0), -- timestamp => timestamp_counter(23 downto 0), -- clk_scsn => clk_scsn, -- readout_value => readout_value_data_analyze_signal, -- readout_address => readout_address_data_analyze_signal -- ); process(TA_clk, reset) begin if reset = '1' then TA_active<= '0'; elsif TA_clk'event and TA_clk = '1' then if activate_timing_analyze_reg_signal = '1' and done_timing_analyze_signal = '0' then TA_active <= '1'; elsif done_timing_analyze_signal = '1' then TA_active <= '0'; end if; end if; end process; --TA_active <= '1'; timestamp_reset <= DET_sync_signal_from_scint_trigger(0); -- timestamp_reset <= DET_sync_delayed_signal(7); process(TA_clk,reset, timestamp_reset) begin if reset = '1' or timestamp_reset = '1' then timestamp_counter <= (others =>'0'); elsif TA_clk'event and TA_clk = '1' and TA_enable = '1' then timestamp_counter <= timestamp_counter + 1; end if; end process; process(TA_clk,reset, timestamp_reset) begin if reset = '1' then TA_enable <= '0'; elsif TA_clk'event and TA_clk = '1' then if timestamp_reset = '1' then TA_enable <= '1'; --elsif timestamp_counter = X"3ffc" or timestamp_counter = X"3ffd" then -- overflow bin at 160 +5 clk cycle ( +4 us ) --elsif timestamp_counter = X"00a5" or timestamp_counter = X"00a6" then elsif timestamp_counter = X"fffff8" or timestamp_counter = X"fffff9" then TA_enable <= '0'; end if; end if; end process; Inst_timing_analyze_module: timing_analyze_module PORT MAP( activate => activate_timing_analyze_reg_signal, reset => reset, clear => clear_timing_analyze_reg_signal, done => done_timing_analyze_signal, signals(0) => analyzer_trigger2, signals(12 downto 1) => DET_sync_delayed_signal(11 downto 0), signals(13) => KOINZ_signal, signals(15 downto 14) => trigger_paralell(1 downto 0), clk => clk160, clk_scsn => clk_scsn, readout_value => readout_value_data_analyze_signal, readout_address => readout_address_data_analyze_signal, trigger_mask => X"00000001" ); -- register scsn data from timing analyze module to do proper timing process(clk_scsn, reset, readout_value_data_analyze_signal) begin if reset = '1' then readout_value_data_analyze_signal_reg <= X"00000000"; elsif clk_scsn'event and clk_scsn='1' then readout_value_data_analyze_signal_reg <= readout_value_data_analyze_signal; end if; end process; T1 <= pulser_signal(0); T2 <= DET(10); T3 <= trigger_paralell(0); T4 <= clk40; -- the encoded signal can be measure at the resistor after the FPGA LED2 <= reset; LED3 <= selector; end Behavioral;