library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;
		 
entity DELAY is
    Port ( DET0p     : in  STD_LOGIC;
			  DET0n     : in  STD_LOGIC;
			  DET1p     : in  STD_LOGIC;
			  DET1n     : in  STD_LOGIC;
	        DET2p     : in  STD_LOGIC;
			  DET2n     : in  STD_LOGIC;
	        DET3p     : in  STD_LOGIC;
			  DET3n     : in  STD_LOGIC;
	        DET4p     : in  STD_LOGIC;
			  DET4n     : in  STD_LOGIC;
	        DET5p     : in  STD_LOGIC;
			  DET5n     : in  STD_LOGIC;
	        DET6p     : in  STD_LOGIC;
			  DET6n     : in  STD_LOGIC;
	        DET7p     : in  STD_LOGIC;
			  DET7n     : in  STD_LOGIC;
	        DET8p     : in  STD_LOGIC;
			  DET8n     : in  STD_LOGIC;
	        DET9p     : in  STD_LOGIC;
			  DET9n     : in  STD_LOGIC;
	        DET10p    : in  STD_LOGIC;
			  DET10n    : in  STD_LOGIC;
	        DET11p    : in  STD_LOGIC;
			  DET11n    : in  STD_LOGIC;
			  
			  DATA      : IN std_logic_vector(31 downto 0);
			  
			  RESET     : in  STD_LOGIC;
		     CLOCK     : in  STD_LOGIC;
			  KOINZ     : out STD_LOGIC);
end DELAY;

architecture Behavioral of DELAY is
	
	signal M     : STD_LOGIC_VECTOR(0 to 11);
	signal DET   : STD_LOGIC_VECTOR(0 to 11);
	signal COINCNUMBER : natural;
	
	signal MTEST : STD_LOGIC_VECTOR(0 to 11);
	
	signal SEL0  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL1  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL2  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL3  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL4  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL5  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL6  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL7  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL8  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL9  : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL10 : STD_LOGIC_VECTOR(1 downto 0);
	signal SEL11 : STD_LOGIC_VECTOR(1 downto 0);

	signal DETNUM  : STD_LOGIC_VECTOR(3 downto 0);
			  
			  
	function COUNTER(m:STD_LOGIC_VECTOR(0 to 11)) return natural is
		variable count : natural;
	begin
			count := 0;
			for i in m'range loop
				if m(i)='1' then count:=count+1;
				end if;
			end loop;
			return count;
	end COUNTER;
		
	
   component IBUFDS 
	port (I  : in STD_LOGIC;
			IB : in STD_LOGIC;
			O  : out STD_LOGIC);
	end component;
	
	component DELAY_MODULE
	port (DIN    : in  STD_LOGIC;
			RESET  : in  STD_LOGIC;
			CLOCK  : in  STD_LOGIC;
			SEL    : in  STD_LOGIC_VECTOR(1 downto 0);
			RESULT : out STD_LOGIC;
			TEST   : out STD_LOGIC);
	end component;
	
	
begin

   -- set number (4 bit) of detector which should have coincidence
   --	and set delays (2 bit) for 12 detectors
	
	GETCOMMAND : process(DATA)
	begin
		DETNUM <= DATA(27 downto 24);
		SEL0   <= DATA(23 downto 22);
		SEL1   <= DATA(21 downto 20);
		SEL2   <= DATA(19 downto 18);
		SEL3   <= DATA(17 downto 16);
		SEL4   <= DATA(15 downto 14);
		SEL5   <= DATA(13 downto 12);
		SEL6   <= DATA(11 downto 10);
		SEL7   <= DATA( 9 downto  8);
		SEL8   <= DATA( 7 downto  6);
		SEL9   <= DATA( 5 downto  4);
		SEL10  <= DATA( 3 downto  2);
		SEL11  <= DATA( 1 downto  0);
	end process;
	
	IN0 : IBUFDS
		port map(I=>DET0p, IB=>DET0n,O=>DET(0));
	IN1 : IBUFDS
		port map(I=>DET1p, IB=>DET1n,O=>DET(1));
	IN2 : IBUFDS
		port map(I=>DET2p, IB=>DET2n,O=>DET(2));
	IN3 : IBUFDS
		port map(I=>DET3p, IB=>DET3n,O=>DET(3));
	IN4 : IBUFDS
		port map(I=>DET4p, IB=>DET4n,O=>DET(4));
	IN5 : IBUFDS
		port map(I=>DET5p, IB=>DET5n,O=>DET(5));
	IN6 : IBUFDS
		port map(I=>DET6p, IB=>DET6n,O=>DET(6));
	IN7 : IBUFDS
		port map(I=>DET7p, IB=>DET7n,O=>DET(7));
	IN8 : IBUFDS
		port map(I=>DET8p, IB=>DET8n,O=>DET(8));
	IN9 : IBUFDS
		port map(I=>DET9p, IB=>DET9n,O=>DET(9));
	IN10: IBUFDS
		port map(I=>DET10p, IB=>DET10n,O=>DET(10));
	IN11: IBUFDS
		port map(I=>DET11p, IB=>DET11n,O=>DET(11));
	
	MODULE0 : DELAY_MODULE
		port map(DET(0),RESET,CLOCK,SEL0,M(0),MTEST(0));
	
	MODULE1 : DELAY_MODULE
		port map(DET(1),RESET,CLOCK,SEL1,M(1),MTEST(1));
	
	MODULE2 : DELAY_MODULE
		port map(DET(2),RESET,CLOCK,SEL2,M(2),MTEST(2));
	
	MODULE3 : DELAY_MODULE
		port map(DET(3),RESET,CLOCK,SEL3,M(3),MTEST(3));

	MODULE4 : DELAY_MODULE
		port map(DET(4),RESET,CLOCK,SEL4,M(4),MTEST(4));

	MODULE5 : DELAY_MODULE
		port map(DET(5),RESET,CLOCK,SEL5,M(5),MTEST(5));
	
	MODULE6 : DELAY_MODULE
		port map(DET(6),RESET,CLOCK,SEL6,M(6),MTEST(6));
	
	MODULE7 : DELAY_MODULE
		port map(DET(7),RESET,CLOCK,SEL7,M(7),MTEST(7));
	
	MODULE8 : DELAY_MODULE
		port map(DET(8),RESET,CLOCK,SEL8,M(8),MTEST(8));

	MODULE9 : DELAY_MODULE
		port map(DET(9),RESET,CLOCK,SEL9,M(9),MTEST(9));

	MODULE10: DELAY_MODULE
		port map(DET(10),RESET,CLOCK,SEL10,M(10),MTEST(10));
	
	MODULE11: DELAY_MODULE
		port map(DET(11),RESET,CLOCK,SEL11,M(11),MTEST(11));
	
	CONVERT : process(DETNUM)
	begin
		case DETNUM is
			when "0001" => COINCNUMBER <=  1;
			when "0010" => COINCNUMBER <=  2;
			when "0011" => COINCNUMBER <=  3;
			when "0100" => COINCNUMBER <=  4;
			when "0101" => COINCNUMBER <=  5;
			when "0110" => COINCNUMBER <=  6;
			when "0111" => COINCNUMBER <=  7;
			when "1000" => COINCNUMBER <=  8;
			when "1001" => COINCNUMBER <=  9;
			when "1010" => COINCNUMBER <= 10;
			when "1011" => COINCNUMBER <= 11;
			when "1100" => COINCNUMBER <= 12;
			when others => COINCNUMBER <= 12;
		end case;
	end process;
	
	
	COINCIDENCE : process(M,COINCNUMBER)
	begin
		if (COUNTER(M) >= COINCNUMBER) then
			KOINZ<='1';
		else
			KOINZ<='0';
		end if;
	end process;
	
end Behavioral;