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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:47:57 05/31/2008 
-- Design Name: 
-- Module Name:    TemperatureSensor_SZ - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_Controll is
    Port ( clk40 : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           update : in  STD_LOGIC;
           DAC_value_0 : in  STD_LOGIC_VECTOR (7 downto 0);
           DAC_value_1 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_2 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_3 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_4 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_5 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_6 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_7 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_8 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_9 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_10 : in  STD_LOGIC_VECTOR (7 downto 0);
			  DAC_value_11 : in  STD_LOGIC_VECTOR (7 downto 0);
           SDA : out  STD_LOGIC;
           SCL : out  STD_LOGIC);
end DAC_Controll;

architecture Behavioral of DAC_Controll is

   component AutoReset
       Port ( BusyIn    : in  STD_LOGIC;
           AutoReset : out  STD_LOGIC;
           Clk       : in  STD_LOGIC);
   end component;

   component DAC40MHz
       Port ( CLK       : in   STD_LOGIC;
           Reset     : in   STD_LOGIC;
           Start     : in   STD_LOGIC;
           SDA       : out  STD_LOGIC;
           SCL       : out  STD_LOGIC;
			  DataIn    : in   std_logic_vector(26 downto 0);
           Busy      : out  STD_LOGIC);
   end component;

   signal AutoResDac, ResetDac, BusyDac, StartDac, SdaDac, SclDac : std_logic;
   signal DataInDac : std_logic_vector (26 downto 0);
   signal Counter : integer range 0 to 4800;
	type States is (Idle, S, C);
   signal State   : States;
   signal Cycle   : integer range 0 to 11;
	type DacRegister is array (11 downto 0, 7 downto 0) of std_logic;
   signal RegA    : DacRegister;
   signal  DacAddress  : std_logic_vector(3 downto 0);
	signal B : std_logic;
	signal creg1d_i : std_logic_vector(7 downto 0); 

begin
   B <= update;
	ResetDac <= AutoResDac or reset;
	
   process (DAC_value_0, DAC_value_1, DAC_value_2, 
	         DAC_value_3, DAC_value_4, DAC_value_5, DAC_value_6,
	         DAC_value_7, DAC_value_8, DAC_value_9, DAC_value_10, DAC_value_11)
   begin
	   for I in 0 to 7 loop
		   RegA ( 0, I) <= DAC_value_0 (I);
		   RegA ( 1, I) <= DAC_value_1 (I);
		   RegA ( 2, I) <= DAC_value_2 (I);
		   RegA ( 3, I) <= DAC_value_3 (I);
		   RegA ( 4, I) <= DAC_value_4 (I);
		   RegA ( 5, I) <= DAC_value_5 (I);
		   RegA ( 6, I) <= DAC_value_6 (I);
		   RegA ( 7, I) <= DAC_value_7 (I);
		   RegA ( 8, I) <= DAC_value_8 (I);
		   RegA ( 9, I) <= DAC_value_9 (I);
		   RegA (10, I) <= DAC_value_10 (I);
		   RegA (11, I) <= DAC_value_11 (I);
	   end loop;
   end process;

   SDA <= SdaDac;
   SCL <= SclDac;
   ResetDac <= AutoResDac or reset;
   DataInDac <= "01010" & DacAddress(3) & "00000000" & DacAddress(2 downto 0) & "0" & creg1d_i(7 downto 0) & "0";

   DAC : DAC40MHz
       port map ( CLK => Clk40,
               Reset => ResetDac,
					Start => StartDac,
					SDA => SdaDac,
					SCL => SclDac,
					DataIn => DataInDac,
					Busy => BusyDac);

   AutoResetDac : AutoReset
       port map ( BusyIn    => BusyDac,
					AutoReset => AutoResDac,
					Clk       => Clk40);

   process (Clk40, B, reset)  -- send data and start signal to the DACs
   begin
	if reset = '1' then
		StartDac   <= '0';
		Counter    <= 0;
		Cycle      <= 0;
		DacAddress <= conv_std_logic_vector (0, 4);
		creg1d_i   <= conv_std_logic_vector (0, 8);
	elsif rising_edge(Clk40) then
		if Counter = 0 then
			case State is
				when Idle =>
					if B = '1' then
						State <= S;
					else State <= Idle;
					end if;
				when S =>
					DacAddress <= conv_std_logic_vector (Cycle, 4);
					for I in 0 to 7 loop creg1d_i(I) <= RegA (Cycle, I); end loop;
					StartDac <= '1';
					Counter <= 3;
					State <= C;
				when C =>
					StartDac <= '0';
					Counter <= 2500;
					if Cycle = 11 then
						State <= Idle;
						Cycle <= 0;
					else
						State <= S;
						Cycle <= Cycle +1;
					end if;
				when others => State <= Idle;
			end case;
		else
			Counter <= Counter -1;
			StartDac <= '0';
		end if;
	end if;	
   end process;
end Behavioral;