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-- Massimiliano De Gaspari
-- 11 August 2006
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DAC120MHz is
    Port ( CLK    : in   STD_LOGIC;
           Reset  : in   STD_LOGIC;
           Start  : in   STD_LOGIC;
           SDA    : out  STD_LOGIC;
           SCL    : out  STD_LOGIC;
			  DataIn : in   std_logic_vector(26 downto 0);
           Busy   : out  STD_LOGIC);
end DAC120MHz;

architecture Behavioral of DAC120MHz is

	signal Data        : std_logic_vector(26 downto 0);
	signal cSDA, cSCL  : std_logic;
	
	type I2CStates is (Idle, Step1, Step2, StartData1, StartData2, StartData3, EndBit, Close, Close2);
	signal I2CState    : I2CStates;
	signal TimeCounter : integer range 0 to 156;
	signal BitCounter  : integer range -1 to 26;
	
	--constant ClkCycle_in_ns: integer:=25/3;    for Clock frequency 120MHz
	constant TLow      : integer:= 156; --1300/ClkCycle_in_ns;
	constant Thd       : integer:= 72;  --600/ClkCycle_in_ns;
	constant THigh     : integer:= 78;  --650/ClkCycle_in_ns;
	constant SCLup     : integer:= 42;  --350/ClkCycle_in_ns;
	constant SCLdown   : integer:= 36;  --300/ClkCycle_in_ns;
	
begin
	
	SDA <= cSDA;
	SCL <= cSCL;
	--       0101     XXX0     0     000XXXXX     0     XXXXXXXX     0
	--       0101     adr0     0     000commd     0     outputby     0
 --Data <= "0101" & "0100" & "0" & "00000000" & "0" & "10000000" & "0";
	
	DAC120MHzMaster: process(CLK,START, Reset)
	begin
		if Reset='1' then
			I2CState <= Idle;
			cSDA <= '1';
			cSCL <= '1';
			Busy <= '0';
			TimeCounter <= 0;
			BitCounter <= 26;
			Data <= conv_std_logic_vector(0, 27);
		elsif rising_edge(CLK) then
			if TimeCounter = 0 then
				case I2CState is
					when Idle =>
						cSDA <= '1';
						cSCL <= '1';
						Busy <= '0';
						--TimeCounter <= 0;
						--BitCounter <= 26;
						if Start = '1' then
							I2CState <= Step1;
						else
							I2CState <= Idle;
						end if;
					when Step1 =>
						cSDA <= '0';
						Data <= DataIn;
						Busy <= '1';
						I2CState <= Step2;
						TimeCounter <= Thd;
					when Step2 =>
						cSCL <= '0';
						I2CState <= StartData1;
						TimeCounter <= Thd;
					when StartData1 =>
						if BitCounter = -1 then
							I2CState <= EndBit;
						else
							cSDA <= Data(BitCounter);
							I2CState <= StartData2;
							TimeCounter <= SCLup;
							BitCounter <= BitCounter-1;
						end if;
					when StartData2 =>
						cSCL <= '1';
						I2CState <= StartData3;
						TimeCounter <= THigh;
					when StartData3 =>
						cSCL <= '0';
						I2CState <= StartData1;
						TimeCounter <= SCLdown;
					when EndBit =>
						cSCL <= '1';
						I2CState <= Close;
						TimeCounter <= Thd;
					when Close =>
						cSDA <= '1';
						I2CState <= Close2;
						TimeCounter <= Tlow;
						BitCounter <= 26;
					when Close2 =>
						I2CState <= Idle;
						Busy <= '0';						
					when others => I2CState <= Idle;
				end case;
			else
				TimeCounter <= TimeCounter-1;
			end if;	
		end if;
	end process;

end Behavioral;