----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:07:58 03/15/2008 
-- Design Name: 
-- Module Name:    Counter_16times48Bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;


-- the driver software should operate this readout module as follow:
-- 1) set readout_req to 1
-- 2) wait for readout_done = 1 (polling)
-- 3) readout desired addresses via scsn (address will be read with the first clk'event data are valid with
--    with the following clk'event) (forwared the scsn_bus_req one cycle later to the scsn_bus_ack) 
-- 4) set readout_req to 0 
entity Counter_64times48Bit is
    Port ( counter_en : in  STD_LOGIC_VECTOR (62 downto 0);
	        clk_en0deg : in STD_LOGIC; -- marks the clk40 rising edge
			  clk_en180deg : in std_logic;
           clk : in  STD_LOGIC;
			  clk160 : in STD_logic;
			  clk_scsn : in STD_LOGIC; -- clk for readout
           readout_req : in  STD_LOGIC; -- one readout_req'event invokes one copy process to the readout RAM
           reset : in  STD_LOGIC;
           readout_done : out  STD_LOGIC; -- indicates that the copy process to readout RAM has finished
			                                 -- indicates valid data on the counter_value port
														-- gets low after one clk'event as soon as readout_req is low
           readout_counter_addr : in  STD_LOGIC_VECTOR (5 downto 0);
           counter_value : out  STD_LOGIC_VECTOR (47 downto 0);
			  debug_signal : out std_logic_vector(7 downto 0));
end Counter_64times48Bit;

architecture Behavioral of Counter_64times48Bit is

-- controll logic
signal ctrl_sig, ctrl_minus1_sig, ctrl_plus1_sig: std_logic_vector(5 downto 0);
signal in_counter_clear, counter_reg_we : std_logic;
signal sig0, sig1, sig2, sig3, sig4, sig5, sig6, sig7, sig8, sig9: std_logic;
signal sig10, sig11, sig12: std_logic_vector(62 downto 0);
signal readout_we : std_logic;

-- reset logic
signal reset_init: std_logic;

-- counter signals
type counter_sig_type is array (integer range 0 to 62) of std_logic_vector(5 downto 0);
signal counter_en1, counter_en2, counter_en3, counter_en4, counter_en5 : std_logic_vector(62 downto 0);
signal counter_en_in_reg, counter_en_reg : std_logic_vector(62 downto 0);
signal counter_en6, counter_en7, counter_en8 : std_logic_vector(62 downto 0);
signal counter_sig, counter_sig_reg: counter_sig_type;
signal counter_sig_mux, counter_sig_alu_a : std_logic_vector(5 downto 0);
signal counter_sig_alu_res, counter_sig_alu_b : std_logic_vector(47 downto 0);
signal dummy_signal, dummy2_signal : std_logic_vector(31 downto 0);
signal zero_signal : std_logic_vector(31 downto 0):=X"00000000";

-- readout state machine
signal next_state, state : std_logic_vector(2 downto 0);

attribute PERIOD : string;
attribute PERIOD of counter_en: signal is "24ns";
attribute PERIOD of clk_scsn: signal is "7ns";
attribute PERIOD of clk: signal is "24ns";


begin

-- controll logic
-- counter
process(clk, reset,ctrl_sig)
begin
   if reset = '1' then
	   ctrl_sig <= "000000";
	elsif clk'event and clk='1' then
	   if ctrl_sig = "111110" then
		   ctrl_sig <= "000000";
		else
	      ctrl_sig <= ctrl_sig + '1';
		end if;
	end if;
end process;

process(clk, reset, ctrl_minus1_sig)
begin
   if reset = '1' then
	   ctrl_minus1_sig <= "111110";
	elsif clk'event and clk = '1' then
	   if ctrl_minus1_sig = "111110" then
	      ctrl_minus1_sig <= "000000";
		else
		   ctrl_minus1_sig <= ctrl_minus1_sig + '1';
		end if;
	end if;
end process;

process(clk, reset, ctrl_plus1_sig)
begin
   if reset = '1' then
	   ctrl_plus1_sig <= "000001";
	elsif clk'event and clk = '1' then
		if ctrl_plus1_sig = "111110" then
		   ctrl_plus1_sig <= "000000";
	   else   
   		ctrl_plus1_sig <= ctrl_plus1_sig + '1';
		end if;
	end if;
end process;

-- reset logic
-- write correct values into the RAM 
process(clk, reset, reset_init)
begin
   if reset = '1' then
	   reset_init <= '1';
	elsif clk'event and clk = '1' then
	   if ctrl_sig = "111110" then
		   reset_init <= '0';
		else
	      reset_init <= reset_init;
		end if;
	end if;
end process;

-- end of cycle controll logic 
sig0 <= '0' when ctrl_sig /= "111101" else '1';
process(clk, reset , sig1)
begin
   if reset = '1' then
      sig1 <= '0';
	elsif clk'event and clk = '1' then
	   sig1 <= sig0;
	end if;
end process;

process(clk_scsn, reset , sig1)
begin
   if reset = '1' then
      sig2 <= '0';
	elsif clk_scsn'event and clk_scsn = '1' then
	   sig2 <= sig1;
	end if;
end process;

process(clk_scsn, reset , sig2, sig1)
begin
   if reset = '1' then
      sig3 <= '0';
	elsif clk_scsn'event and clk_scsn = '1' then
	   sig3 <= sig1 and not sig2;
	end if;
end process;

process(clk_scsn, reset, sig4)
begin
   if reset = '1' then
	   sig4 <= '0';
	elsif clk_scsn'event and clk_scsn ='1' then
	   sig4 <= sig3;
   end if;		
end process;

process(clk_scsn, reset, sig4)
begin
   if reset = '1' then
	   sig5 <= '0';
	elsif clk_scsn'event and clk_scsn ='1' then
	   sig5 <= sig4;
   end if;		
end process;
counter_reg_we <= sig5;

process(clk_scsn, reset, sig5)
begin
   if reset = '1' then
	   sig6 <= '0';
	elsif clk_scsn'event and clk_scsn ='1' then
	   sig6 <= sig5;
   end if;		
end process;
in_counter_clear <= sig6;

-- inputstage 
inputstage: for ii in 0 to 62 generate

   -- syncronize to new clk40 domain
	--process(clk160, reset, counter_en(ii))
	--begin
	--   if reset = '1' then
	--	   counter_en1(ii) <= '0';
	--	elsif clk160'event and clk160 = '1' then
	--	   counter_en1(ii) <= (counter_en(ii) or counter_en1(ii)) and (not counter_en_reg(ii)) ;
	--	end if;
	--end process;
	
	--process(clk, reset, counter_en1(ii))
	--begin
	--   if reset = '1' then
	--	   counter_en_reg(ii) <= '0';
	--	elsif clk'event and clk = '0' then
	--	   counter_en_reg(ii) <= counter_en1(ii);
	--	end if;
	--end process;

	inputstage_latch:
	--syncronize to counter phase of clock
	process(clk160, reset,counter_en(ii))
	begin
	   if reset = '1' then
		   counter_en1(ii) <= counter_en(ii);
      elsif clk160'event and clk160 = '1' then
         counter_en1(ii) <= counter_en(ii); 
     end if;
   end process;

	process(clk160, reset,counter_en1(ii), counter_en8(ii))
	begin
	   if reset = '1' then
		   counter_en2(ii) <= counter_en1(ii);
      elsif clk160'event and clk160 = '1' then
         counter_en2(ii) <= counter_en1(ii) and (not counter_en8(ii)); 
     end if;
   end process;		

	process(clk160, reset,counter_en2(ii), counter_en8(ii))
	begin
	   if reset = '1' then
		   counter_en3(ii) <= counter_en2(ii);
      elsif clk160'event and clk160 = '1' then
         counter_en3(ii) <= counter_en2(ii) and (not counter_en8(ii)); 
      end if;
   end process;		

   -- feedback loop between clk40 and clk160
	process(clk160, reset,counter_en3(ii), counter_en8(ii))
	begin
	   if reset = '1' then
		   counter_en4(ii) <= counter_en3(ii);
      elsif clk160'event and clk160 = '1' then
         counter_en4(ii) <= counter_en3(ii) and (not counter_en8(ii)); 
      end if;
   end process;			
	counter_en5(ii) <= counter_en1(ii) or counter_en2(ii) or counter_en3(ii) or counter_en4(ii);
	
	process(clk160, reset, counter_en5(ii))
	begin
	   if reset = '1' then
		   counter_en7(ii) <= '0';
		elsif clk160'event and clk160 = '1' then
		   counter_en7(ii) <= counter_en5(ii); 
		end if;
	end process;
	counter_en8(ii) <= counter_en7(ii) and counter_en_reg(ii);
	
	-- delay counter_en to ensure setup and hold times
	-- make a feedback from clk40 into the clk160 clock domain so
	-- no pulses are lost or counted twice if clocks are slightly misaligned
	process(clk, reset, counter_en5(ii))
	begin
	   if reset = '1' then 
		   counter_en_reg(ii) <= '0';
		elsif clk'event and clk = '0' then
		   counter_en_reg(ii) <= counter_en5(ii);
		end if;
	end process;
	
	--inputstage_delay:
	--process(clk_scsn, reset, counter_en(ii))
	--begin
	--   if reset = '1' then 
	--	   counter_en_reg(ii) <= '0';
	--	elsif clk_scsn'event and clk_scsn = '1' then
	--	   counter_en_reg(ii) <= counter_en_in_reg(ii);
	--	end if;
	--end process;

   inputstage_incounter : 
   process(reset,counter_en_reg(ii), clk, counter_sig)
	begin
	   if reset = '1' or in_counter_clear = '1' then
		   counter_sig(ii) <= "000000";
		elsif clk'event and clk = '1' and counter_en_reg(ii) = '1' then
		   counter_sig(ii) <= counter_sig(ii) + '1';
		end if;
   end process;
	
	inputstage_latch_precounter : 
	process(reset_init, clk_scsn, counter_sig)
	begin
	   if reset_init = '1' then
		   counter_sig_reg(ii)(5 downto 0) <= "000000";
		elsif clk_scsn'event and clk_scsn = '1' and counter_reg_we = '1' then
	      counter_sig_reg(ii)(5 downto 0) <= counter_sig(ii)(5 downto 0);
		end if;
	end process;
	
end generate;

-- Mux for different counters
process(ctrl_sig, counter_sig_reg)
begin
   case (ctrl_sig) is 
      when  "000000" => counter_sig_mux <= counter_sig_reg(0);
      when  "000001" => counter_sig_mux <= counter_sig_reg(1);
      when  "000010" => counter_sig_mux <= counter_sig_reg(2);
	   when  "000011" => counter_sig_mux <= counter_sig_reg(3);
      when  "000100" => counter_sig_mux <= counter_sig_reg(4);
	   when  "000101" => counter_sig_mux <= counter_sig_reg(5);
	   when  "000110" => counter_sig_mux <= counter_sig_reg(6);
	   when  "000111" => counter_sig_mux <= counter_sig_reg(7);
	   when  "001000" => counter_sig_mux <= counter_sig_reg(8);
      when  "001001" => counter_sig_mux <= counter_sig_reg(9);
      when  "001010" => counter_sig_mux <= counter_sig_reg(10);
	   when  "001011" => counter_sig_mux <= counter_sig_reg(11);
      when  "001100" => counter_sig_mux <= counter_sig_reg(12);
	   when  "001101" => counter_sig_mux <= counter_sig_reg(13);
	   when  "001110" => counter_sig_mux <= counter_sig_reg(14);
	   when  "001111" => counter_sig_mux <= counter_sig_reg(15);
	   when  "010000" => counter_sig_mux <= counter_sig_reg(16);
      when  "010001" => counter_sig_mux <= counter_sig_reg(17);
      when  "010010" => counter_sig_mux <= counter_sig_reg(18);
	   when  "010011" => counter_sig_mux <= counter_sig_reg(19);
      when  "010100" => counter_sig_mux <= counter_sig_reg(20);
	   when  "010101" => counter_sig_mux <= counter_sig_reg(21);
	   when  "010110" => counter_sig_mux <= counter_sig_reg(22);
	   when  "010111" => counter_sig_mux <= counter_sig_reg(23);
	   when  "011000" => counter_sig_mux <= counter_sig_reg(24);
      when  "011001" => counter_sig_mux <= counter_sig_reg(25);
      when  "011010" => counter_sig_mux <= counter_sig_reg(26);
	   when  "011011" => counter_sig_mux <= counter_sig_reg(27);
      when  "011100" => counter_sig_mux <= counter_sig_reg(28);
	   when  "011101" => counter_sig_mux <= counter_sig_reg(29);
	   when  "011110" => counter_sig_mux <= counter_sig_reg(30);
	   when  "011111" => counter_sig_mux <= counter_sig_reg(31);
	   when  "100000" => counter_sig_mux <= counter_sig_reg(32);
      when  "100001" => counter_sig_mux <= counter_sig_reg(33);
      when  "100010" => counter_sig_mux <= counter_sig_reg(34);
	   when  "100011" => counter_sig_mux <= counter_sig_reg(35);
      when  "100100" => counter_sig_mux <= counter_sig_reg(36);
	   when  "100101" => counter_sig_mux <= counter_sig_reg(37);
	   when  "100110" => counter_sig_mux <= counter_sig_reg(38);
	   when  "100111" => counter_sig_mux <= counter_sig_reg(39);
	   when  "101000" => counter_sig_mux <= counter_sig_reg(40);
      when  "101001" => counter_sig_mux <= counter_sig_reg(41);
      when  "101010" => counter_sig_mux <= counter_sig_reg(42);
	   when  "101011" => counter_sig_mux <= counter_sig_reg(43);
      when  "101100" => counter_sig_mux <= counter_sig_reg(44);
	   when  "101101" => counter_sig_mux <= counter_sig_reg(45);
	   when  "101110" => counter_sig_mux <= counter_sig_reg(46);
	   when  "101111" => counter_sig_mux <= counter_sig_reg(47);
	   when  "110000" => counter_sig_mux <= counter_sig_reg(48);
      when  "110001" => counter_sig_mux <= counter_sig_reg(49);
      when  "110010" => counter_sig_mux <= counter_sig_reg(50);
	   when  "110011" => counter_sig_mux <= counter_sig_reg(51);
      when  "110100" => counter_sig_mux <= counter_sig_reg(52);
	   when  "110101" => counter_sig_mux <= counter_sig_reg(53);
	   when  "110110" => counter_sig_mux <= counter_sig_reg(54);
	   when  "110111" => counter_sig_mux <= counter_sig_reg(55);
	   when  "111000" => counter_sig_mux <= counter_sig_reg(56);
      when  "111001" => counter_sig_mux <= counter_sig_reg(57);
      when  "111010" => counter_sig_mux <= counter_sig_reg(58);
	   when  "111011" => counter_sig_mux <= counter_sig_reg(59);
      when  "111100" => counter_sig_mux <= counter_sig_reg(60);
	   when  "111101" => counter_sig_mux <= counter_sig_reg(61);
	   when  "111110" => counter_sig_mux <= counter_sig_reg(62);
      when others => counter_sig_mux <= "000000";
   end case;
end process;

-- pipeline  flipflop
process(clk, reset, reset_init, counter_sig_mux)
begin
   if reset= '1' or reset_init='1' then
	   counter_sig_alu_a <= "000000";
	elsif clk'event and clk='1' then
	   counter_sig_alu_a <= counter_sig_mux;
	end if;
end process;

-- ALU
counter_sig_alu_res (47 downto 0) <= counter_sig_alu_a(5 downto 0) + counter_sig_alu_b(47 downto 0);

   -- counter ram high bits
	counter_ram_high_inst : RAMB16_S36_S36
   generic map (
      INIT_A => X"000000000",  --  Value of output RAM registers on Port A at startup
      INIT_B => X"000000000",  --  Value of output RAM registers on Port B at startup
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      SRVAL_A => X"000000000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"000000000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Address 0 to 127
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- The next set of INITP_xx are for the parity bits
      -- Address 0 to 127
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,      -- Port A 32-bit Data Output
      DOB(31 downto 16) => zero_signal(31 downto 16),      -- Port B 32-bit Data Output
      DOB(15 downto 0) => counter_sig_alu_b(47 downto 32),
		DOPA => open,    -- Port A 4-bit Parity Output
      DOPB => open,    -- Port B 4-bit Parity Output
		ADDRA(8 downto 6) => "000",
      ADDRA(5 downto 0) => ctrl_minus1_sig,  -- Port A 9-bit Address Input
		ADDRB(8 downto 6) => "000",
      ADDRB(5 downto 0) => ctrl_sig,  -- Port B 9-bit Address Input
      CLKA => clk,    -- Port A 1-bit Clock
      CLKB => clk,    -- Port B 1-bit Clock
		DIA(31 downto 16) => dummy_signal(31 downto 16),
      DIA(15 downto 0) => counter_sig_alu_res(47 downto 32),      -- Port A 32-bit Data Input
      DIB => X"00000000",      -- Port B 32-bit Data Input
      DIPA => "0000",    -- Port A 4-bit parity Input
      DIPB => "0000",    -- Port-B 4-bit parity Input
      ENA => '1',      -- Port A 1-bit RAM Enable Input
      ENB => '1',      -- Port B 1-bit RAM Enable Input
      SSRA => reset_init,    -- Port A 1-bit Synchronous Set/Reset Input
      SSRB => reset_init,    -- Port B 1-bit Synchronous Set/Reset Input
      WEA => '1',      -- Port A 4-bit Write Enable Input
      WEB => '0'       -- Port B 4-bit Write Enable Input
   );
	
	
   -- counter ram low bits
	   counter_ram_low_inst : RAMB16_S36_S36
   generic map (
      INIT_A => X"000000000",  --  Value of output RAM registers on Port A at startup
      INIT_B => X"000000000",  --  Value of output RAM registers on Port B at startup
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      SRVAL_A => X"000000000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"000000000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Address 0 to 127
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- The next set of INITP_xx are for the parity bits
      -- Address 0 to 127
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,      -- Port A 32-bit Data Output
      DOB => counter_sig_alu_b(31 downto 0),      -- Port B 32-bit Data Output
      DOPA => open,    -- Port A 4-bit Parity Output
      DOPB => open,    -- Port B 4-bit Parity Output
		ADDRA(8 downto 6) => "000",
      ADDRA(5 downto 0) => ctrl_minus1_sig,  -- Port A 9-bit Address Input
		ADDRB(8 downto 6) => "000",
      ADDRB(5 downto 0) => ctrl_sig,  -- Port B 9-bit Address Input
      CLKA => clk,    -- Port A 1-bit Clock
      CLKB => clk,    -- Port B 1-bit Clock
      DIA => counter_sig_alu_res(31 downto 0),      -- Port A 32-bit Data Input
      DIB => X"00000000",      -- Port B 32-bit Data Input
      DIPA => "0000",    -- Port A 4-bit parity Input
      DIPB => "0000",    -- Port-B 4-bit parity Input
      ENA => '1',      -- Port A 1-bit RAM Enable Input
      ENB => '1',      -- Port B 1-bit RAM Enable Input
      SSRA => reset_init,    -- Port A 1-bit Synchronous Set/Reset Input
      SSRB => reset_init,    -- Port B 1-bit Synchronous Set/Reset Input
      WEA => '1',      -- Port A 4-bit Write Enable Input
      WEB => '0'       -- Port B 4-bit Write Enable Input
   );
	
	-- readout ram high bits
	readout_ram_low_inst : RAMB16_S36_S36
   generic map (
      INIT_A => X"000000000",  --  Value of output RAM registers on Port A at startup
      INIT_B => X"000000000",  --  Value of output RAM registers on Port B at startup
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      SRVAL_A => X"000000000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"000000000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Address 0 to 127
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- The next set of INITP_xx are for the parity bits
      -- Address 0 to 127
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,      -- Port A 32-bit Data Output
      DOB(31 downto 16) => dummy2_signal(31 downto 16),
		DOB(15 downto 0) => counter_value(47 downto 32),      -- Port B 32-bit Data Output
      DOPA => open,    -- Port A 4-bit Parity Output
      DOPB => open,    -- Port B 4-bit Parity Output
		ADDRA(8 downto 6) => "000",
      ADDRA(5 downto 0) => ctrl_minus1_sig,  -- Port A 9-bit Address Input
		ADDRB(8 downto 6) => "000",
      ADDRB(5 downto 0) => readout_counter_addr,  -- Port B 9-bit Address Input
      CLKA => clk,    -- Port A 1-bit Clock
      CLKB => clk_scsn,    -- Port B 1-bit Clock
      DIA(31 downto 16) => zero_signal(31 downto 16),
		DIA(15 downto 0) => counter_sig_alu_res(47 downto 32),      -- Port A 32-bit Data Input
      DIB => X"00000000",      -- Port B 32-bit Data Input
      DIPA => "0000",    -- Port A 4-bit parity Input
      DIPB => "0000",    -- Port-B 4-bit parity Input
      ENA => '1',      -- Port A 1-bit RAM Enable Input
      ENB => '1',      -- Port B 1-bit RAM Enable Input
      SSRA => reset_init,    -- Port A 1-bit Synchronous Set/Reset Input
      SSRB => reset_init,    -- Port B 1-bit Synchronous Set/Reset Input
      WEA => readout_we,      -- Port A 4-bit Write Enable Input
      WEB => '0'       -- Port B 4-bit Write Enable Input
   );	

	
	-- readout ram low bits
	   readout_ram_high_inst : RAMB16_S36_S36
   generic map (
      INIT_A => X"000000000",  --  Value of output RAM registers on Port A at startup
      INIT_B => X"000000000",  --  Value of output RAM registers on Port B at startup
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      SRVAL_A => X"000000000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"000000000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Address 0 to 127
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- The next set of INITP_xx are for the parity bits
      -- Address 0 to 127
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 128 to 255
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 256 to 383
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Address 384 to 511
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,      -- Port A 32-bit Data Output
      DOB(31 downto 0) => counter_value(31 downto 0),      -- Port B 32-bit Data Output
      DOPA => open,    -- Port A 4-bit Parity Output
      DOPB => open,    -- Port B 4-bit Parity Output
		ADDRA(8 downto 6) => "000",
      ADDRA(5 downto 0) => ctrl_minus1_sig,  -- Port A 9-bit Address Input
		ADDRB(8 downto 6) => "000",
      ADDRB(5 downto 0) => readout_counter_addr,  -- Port B 9-bit Address Input
      CLKA => clk,    -- Port A 1-bit Clock
      CLKB => clk_scsn,    -- Port B 1-bit Clock
      DIA => counter_sig_alu_res(31 downto 0),      -- Port A 32-bit Data Input
      DIB => X"00000000",      -- Port B 32-bit Data Input
      DIPA => "0000",    -- Port A 4-bit parity Input
      DIPB => "0000",    -- Port-B 4-bit parity Input
      ENA => '1',      -- Port A 1-bit RAM Enable Input
      ENB => '1',      -- Port B 1-bit RAM Enable Input
      SSRA => reset_init,    -- Port A 1-bit Synchronous Set/Reset Input
      SSRB => reset_init,    -- Port B 1-bit Synchronous Set/Reset Input
      WEA => readout_we,      -- Port A 4-bit Write Enable Input
      WEB => '0'       -- Port B 4-bit Write Enable Input
   );
	
-- readout state machine
-- state machine controlling readout of counters
-- state switching
process(state, ctrl_sig, readout_req)
begin
   next_state <= (others => '0');

	-- reset state
   if state = "000" then
	   if reset_init /= '1' then
	      next_state <= "001";
		end if;
	end if;
	
	-- wait readout_req state
	if state = "001" then
	   if (readout_req = '0') then
	      next_state <= "001";
		end if;
		if (readout_req = '1') then
		   next_state <= "010";
		end if;
	end if;

   -- wait ctrl = 62	state
	if state = "010" then
	   if ctrl_sig = "111110" then
		   next_state <= "011";
		else
		   next_state <= "010";
		end if;
	end if;

   -- copy state
	if state = "011" then
	   if ctrl_sig = "111110" then
		   next_state <= "100";
		else
		   next_state <= "011";
		end if;
	end if;
	
	-- Done state (valid data on the counter_value port)
	if state = "100" then
	   if (readout_req = '0') then
		   next_state <= "001";
		else
		   next_state <= "100";
		end if;
	end if;
end process;

-- output
process(state)
begin
   -- standard values
	readout_we <= '0'; -- we signal for readout ram
	readout_done <= '0';
	
	if state ="000" then
	   readout_we <= '0';
		readout_done <= '0';
	end if;
	
	if state ="001" then
	   readout_we <= '0';
		readout_done <= '0';
	end if;
	
	if state = "010" then
	   readout_we <= '0';
		readout_done <= '0';
	end if;
	
   if state ="011" then
	   readout_we <= '1';
		readout_done <= '0';
	end if;
	
   if state ="100" then
	   readout_we <= '0';
		readout_done <= '1';
	end if;
end process;

-- state transmission register
process (clk, reset, next_state)
begin
   if reset = '1' then
	   state <= "000";
	elsif clk'event and clk = '1' then
	   state <= next_state;
	end if;
end process;

end Behavioral;