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-- Massimiliano De Gaspari
-- July 25th, 2006
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity Clock120MHz is
    Port ( ClkP   : in   STD_LOGIC;
           ClkN   : in   STD_LOGIC;
           Clk120 : out  STD_LOGIC;
			  Clk40  : out  STD_LOGIC;
           Reset  : in   STD_LOGIC);
end Clock120MHz;

architecture Behavioral of Clock120MHz is

	component mydcmx3 is
   port ( CLKIN_N_IN        : in    std_logic; 
          CLKIN_P_IN        : in    std_logic; 
          RST_IN            : in    std_logic; 
          CLKFX_OUT         : out   std_logic; 
          CLKIN_IBUFGDS_OUT : out   std_logic; 
          CLK0_OUT          : out   std_logic; 
          LOCKED_OUT        : out   std_logic);
	end component;

signal A, C : std_logic;

begin

Inst_MyDCMX3: MyDCMX3 PORT MAP(  CLKIN_N_IN        => ClkN,
											CLKIN_P_IN        => ClkP,
											RST_IN            => Reset,
											CLKFX_OUT         => Clk120,
											CLKIN_IBUFGDS_OUT => A,
											CLK0_OUT          => Clk40,
											LOCKED_OUT        => C);

end Behavioral;