------------------------------------------------------------------------------- -- Title : Trigger Receiver Module ------------------------------------------------------------------------------- -- Description : Receives and decodes data from the Trigger system using -- Channel A and B ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ttc_receiver_top is port ( -- general signals clk : in std_logic; reset_n : in std_logic; -- -- ttc event logging & communication -- clk_ppc : in std_logic; -- ttc_events_addr : in std_logic_vector(9 downto 0); -- ttc_events_data : out std_logic_vector(17 downto 0); -- ttc_events_log_ctrl : in std_logic_vector(19 downto 0); -- ttc_events_log_mon : out std_logic_vector(15 downto 0); -- ttc_events_log_halt : in std_logic; -- -- ttc debugging -- ttc_dbg_ctrl : in std_logic_vector(7 downto 0); -- ttc_dbg_cmpval : in std_logic_vector(61 downto 0); -- diag_busy_req_ttc : out std_logic; channelA : in std_logic; channelB : in std_logic; -- triggers l0trigger : out std_logic; l1trigger : out std_logic; l2atrigger : out std_logic; l2rtrigger : out std_logic; -- strobes l1m_strobe : out std_logic; l2m_strobe : out std_logic; -- sod/eod sod : out std_logic; eod : out std_logic; sod_eod_debug_up : out std_logic_vector(31 downto 0); -- resets reset_bc : out std_logic; reset_ec : out std_logic; error_ttc_rcv : out std_logic_vector(15 downto 0); -- message outputs l1_message : out std_logic_vector(59 downto 0); l1_message_rdy : out std_logic; l2a_message : out std_logic_vector(95 downto 0); l2r_message : out std_logic_vector(11 downto 0) ); end ttc_receiver_top; architecture arc of ttc_receiver_top is ------------------------------------------------------------------------------- component ila port ( control : in std_logic_vector(35 downto 0); clk : in std_logic; data : in std_logic_vector(255 downto 0); trig0 : in std_logic_vector(15 downto 0) ); end component; ------------------------------------------------------------------------------- signal channelB_on : std_logic; signal testmode_on : std_logic; signal chB_data : std_logic_vector(38 downto 0); signal chB_data_rdy : std_logic_vector(1 downto 0); signal l0trigger_i : std_logic; signal l1trigger_i : std_logic; signal l2atrigger_i : std_logic; signal l2rtrigger_i : std_logic; signal l1m_strobe_i : std_logic; signal l2m_strobe_i : std_logic; signal l1_message_rdy_i : std_logic; signal eod_i : std_logic; signal sod_i : std_logic; signal reset_bc_i : std_logic; signal reset_ec_i : std_logic; signal chA_decode_error_i : std_logic; signal single_bit_error_i : std_logic; signal double_bit_error_i : std_logic; signal channelB_comm_error_i : std_logic; signal err_l1_message_i : std_logic; signal err_l2a_message_i : std_logic; signal err_roi_message_i : std_logic; signal err_bcid_i : std_logic; signal err_cit_i : std_logic; signal err_unknown_addr_i : std_logic; signal l2am_interrupted_i : std_logic; signal l2m_consecutive_i : std_logic; signal channelA_r, channelA_r2 : std_logic; signal l2a_message_i : std_logic_vector(95 downto 0); -- -- ttc event logging -- type fsm_arb is (ARB_RST, ARB_IDLE, ARB_A, ARB_B, ARB_INFO, ARB_HALT); -- signal cs, ns : fsm_arb; -- signal bram_sel : std_logic_vector(3 downto 0); -- signal bram_we_i : std_logic; -- signal bram_waddr : std_logic_vector(9 downto 0); -- signal bram_waddr_i : std_logic_vector(9 downto 0); -- signal last_bram_waddr : std_logic_vector(9 downto 0); -- signal bram_wdata : std_logic_vector(17 downto 0); -- signal bc : std_logic_vector(11 downto 0); -- signal timestamp : std_logic_vector(16 downto 0); -- signal info_code : std_logic_vector(2 downto 0); -- signal typeA : std_logic_vector(1 downto 0); -- signal eventA : std_logic; -- signal eventA_req : std_logic; -- signal eventA_log : std_logic_vector(35 downto 0); -- signal eventA_written : std_logic; -- signal eventB : std_logic; -- signal eventB_l1m : std_logic; -- signal eventB_l2a : std_logic; -- signal eventB_l2r : std_logic; -- signal eventB_res_ctp : std_logic; -- signal eventB_brc_orbit : std_logic; -- signal eventB_brc_prepulse : std_logic; -- signal eventB_brc_others : std_logic; -- signal eventB_req : std_logic; -- signal eventB_log : std_logic_vector(53 downto 0); -- signal eventB_written : std_logic; -- signal is_l1m_word : std_logic; -- signal is_l2a_word : std_logic; -- signal is_l2r_word : std_logic; -- signal is_res_ctp_word : std_logic; -- signal is_brc_orbit : std_logic; -- signal is_brc_prepulse : std_logic; -- signal is_brc_others : std_logic; -- signal info : std_logic; -- signal info_ctb0, info_ctb1 : std_logic; -- signal info_req : std_logic; -- signal info_log : std_logic_vector(17 downto 0); -- signal info_written : std_logic; -- signal wcnt : std_logic_vector(3 downto 0); -- signal wcnt_i : std_logic_vector(3 downto 0); -- -- signal reset_done : std_logic; -- signal reset_in_progress : std_logic; -- signal logging_halted : std_logic; -- signal bram_overflow : std_logic; -- signal bram_overflow_rst_i : std_logic; -- -- signal ppc_reset_req : std_logic; -- signal ppc_halt_req : std_logic; -- signal ppc_cont_req : std_logic; -- signal ppc_ignore_brc : std_logic; -- signal ppc_ignore_iac : std_logic; -- signal ppc_ignore_chA : std_logic; -- signal ppc_ignore_l1m : std_logic; -- signal ppc_ignore_l2a : std_logic; -- signal ppc_ignore_l2r : std_logic; -- signal ppc_ignore_res_ctp : std_logic; -- signal ppc_ignore_brc_orbit : std_logic; -- signal ppc_ignore_brc_prepulse : std_logic; -- signal ppc_ignore_brc_others : std_logic; -- signal ppc_ignore_brcinfo : std_logic; -- signal ppc_ignore_msginfo : std_logic; -- signal ppc_log_mask : std_logic_vector(5 downto 0); -- -- signal stop_on_ext_cond : std_logic; -- signal stop_on_error : std_logic; -- signal stop_on_debug : std_logic; -- signal reset_timestamp : std_logic; -- signal chB_header : std_logic_vector(3 downto 0); -- signal chB_brc_data : std_logic_vector(7 downto 0); -- -- signal ppc_reset_req_r : std_logic; -- signal ppc_cont_req_r : std_logic; -- signal reset_req : std_logic; -- signal cont_req : std_logic; -- signal halt_req : std_logic; -- signal halt : std_logic; begin ------------------------------------------------------------------------------- sod <= sod_i; eod <= eod_i; channelB_on <= '1'; testmode_on <= '0'; l0trigger <= l0trigger_i; l1trigger <= l1trigger_i; l2atrigger <= l2atrigger_i; l2rtrigger <= l2rtrigger_i; l1m_strobe <= l1m_strobe_i; l2m_strobe <= l2m_strobe_i; l1_message_rdy <= l1_message_rdy_i; l2a_message <= l2a_message_i; reset_bc <= reset_bc_i; reset_ec <= reset_ec_i; error_ttc_rcv(0) <= chA_decode_error_i; error_ttc_rcv(1) <= single_bit_error_i; error_ttc_rcv(2) <= double_bit_error_i; error_ttc_rcv(3) <= channelB_comm_error_i; error_ttc_rcv(4) <= err_l1_message_i; error_ttc_rcv(5) <= err_l2a_message_i; error_ttc_rcv(6) <= '0'; error_ttc_rcv(7) <= err_roi_message_i; error_ttc_rcv(8) <= err_bcid_i; error_ttc_rcv(9) <= err_cit_i; error_ttc_rcv(10) <= err_unknown_addr_i; error_ttc_rcv(13 downto 11) <= "000"; error_ttc_rcv(14) <= l2am_interrupted_i; -- illegal for single event mode error_ttc_rcv(15) <= l2m_consecutive_i; -- illegal for single event mode --#out log out -- ------------------------------------------------------------------------------ -- -- BRAM instance -- -- ------------------------------------------------------------------------------ -- ttc_log_bram : entity work.ppc_interface_bram -- port map ( -- write_clk => clk, -- write_enable => bram_we_i, -- write_addr => bram_waddr, -- write_data => bram_wdata, -- read_clk => clk_ppc, -- read_addr => ttc_events_addr, -- read_data => ttc_events_data -- ); -- ------------------------------------------------------------------------------ -- -- PPC interface -- -- ------------------------------------------------------------------------------ -- ppc_reset_req <= ttc_events_log_ctrl(0); -- ppc_halt_req <= ttc_events_log_ctrl(1); -- ppc_cont_req <= ttc_events_log_ctrl(2); -- ppc_ignore_brc <= ttc_events_log_ctrl(3); -- ppc_ignore_chA <= ttc_events_log_ctrl(4); -- ppc_ignore_brcinfo <= ttc_events_log_ctrl(5); -- ppc_ignore_msginfo <= ttc_events_log_ctrl(6); -- ppc_ignore_l1m <= ttc_events_log_ctrl(7); -- ppc_ignore_l2a <= ttc_events_log_ctrl(8); -- ppc_ignore_l2r <= ttc_events_log_ctrl(9); -- ppc_ignore_res_ctp <= ttc_events_log_ctrl(10); -- ppc_ignore_brc_orbit <= ttc_events_log_ctrl(11); -- ppc_ignore_brc_prepulse <= ttc_events_log_ctrl(12); -- ppc_ignore_brc_others <= ttc_events_log_ctrl(13); -- ppc_log_mask <= ttc_events_log_ctrl(19 downto 14); -- -- ttc_events_log_mon(0) <= reset_in_progress; -- ttc_events_log_mon(1) <= logging_halted; -- ttc_events_log_mon(2) <= bram_overflow; -- ttc_events_log_mon(3) <= eventA_req; -- ttc_events_log_mon(4) <= eventB_req; -- ttc_events_log_mon(5) <= info_req; -- ttc_events_log_mon(15 downto 6) <= bram_waddr; -- process(clk) -- begin -- if rising_edge(clk) then -- -- edge detection for reset and continue -- ppc_reset_req_r <= ppc_reset_req; -- ppc_cont_req_r <= ppc_cont_req; -- -- -- reset_in_progress is evaluated by PPC to determine when logging reset is finished -- if reset_n = '0' or reset_done = '1' then -- reset_in_progress <= '0'; -- elsif reset_req = '1' then -- reset_in_progress <= '1'; -- end if; -- end if; -- end process; -- reset_req <= ppc_reset_req and (not ppc_reset_req_r); -- cont_req <= ppc_cont_req and (not ppc_cont_req_r); -- -- -- ------------------------------------------------------------------------------ -- -- Logging arbitration -- -- ------------------------------------------------------------------------------ -- process(clk) -- begin -- if rising_edge(clk) then -- if reset_n = '0' then -- cs <= ARB_RST; -- wcnt <= (others => '0'); -- bram_waddr <= (others => '0'); -- else -- cs <= ns; -- wcnt <= wcnt_i; -- bram_waddr <= bram_waddr_i; -- end if; -- end if; -- end process; -- -- -- process(cs, -- eventA_req, eventB_req, info_req, -- reset_req, halt, bram_waddr, -- wcnt, bram_waddr ) -- begin -- -- ns <= cs; -- -- wcnt_i <= wcnt; -- eventA_written <= '0'; -- eventB_written <= '0'; -- info_written <= '0'; -- -- bram_sel <= (others => '0'); -- bram_waddr_i <= bram_waddr; -- bram_we_i <= '0'; -- bram_overflow_rst_i <= '0'; -- -- reset_done <= '0'; -- -- logging_halted <= '0'; -- -- case cs is -- when ARB_RST => bram_waddr_i <= (others => '0'); -- bram_overflow_rst_i <= '1'; -- eventA_written <= '1'; -- eventB_written <= '1'; -- info_written <= '1'; -- -- reset_done <= '1'; -- -- ns <= ARB_IDLE; -- -- when ARB_IDLE => if eventA_req = '1' then ns <= ARB_A; -- elsif eventB_req = '1' then ns <= ARB_B; -- elsif info_req = '1' then ns <= ARB_INFO; -- elsif reset_req = '1' then ns <= ARB_RST; -- elsif halt = '1' then ns <= ARB_HALT; -- end if; -- -- when ARB_A => bram_sel <= x"1"; -- bram_we_i <= '1'; -- bram_waddr_i <= bram_waddr + '1'; -- -- if wcnt /= x"1" then -- wcnt_i <= wcnt + '1'; -- else -- wcnt_i <= (others => '0'); -- eventA_written <= '1'; -- -- if eventB_req = '1' then ns <= ARB_B; -- elsif info_req = '1' then ns <= ARB_INFO; -- elsif halt = '1' then ns <= ARB_HALT; -- else ns <= ARB_IDLE; -- end if; -- end if; -- -- when ARB_B => bram_sel <= x"2"; -- bram_we_i <= '1'; -- bram_waddr_i <= bram_waddr + '1'; -- -- if wcnt /= x"2" then -- wcnt_i <= wcnt + '1'; -- else -- wcnt_i <= (others => '0'); -- eventB_written <= '1'; -- -- if eventA_req = '1' then ns <= ARB_A; -- elsif info_req = '1' then ns <= ARB_INFO; -- elsif halt = '1' then ns <= ARB_HALT; -- else ns <= ARB_IDLE; -- end if; -- end if; -- -- when ARB_INFO => bram_sel <= x"3"; -- bram_we_i <= '1'; -- bram_waddr_i <= bram_waddr + '1'; -- info_written <= '1'; -- -- if eventA_req = '1' then ns <= ARB_A; -- elsif eventB_req = '1' then ns <= ARB_B; -- elsif halt = '1' then ns <= ARB_HALT; -- else ns <= ARB_IDLE; -- end if; -- -- -- when ARB_HALT => logging_halted <= '1'; -- -- if reset_req = '1' then -- reset_req clears halt_req-flag -- ns <= ARB_RST; -- elsif halt = '0' then -- ns <= ARB_IDLE; -- end if; -- end case; -- end process; -- -- -- -- store last bram write address -- process(clk) -- begin -- if rising_edge(clk) then -- if reset_n = '0' or reset_req = '1' then -- last_bram_waddr <= (others => '0'); -- bram_overflow <= '0'; -- else -- if bram_we_i = '1' then -- last_bram_waddr <= bram_waddr; -- end if; -- -- if bram_waddr = ("00" & x"00") and last_bram_waddr = ("11" & x"ff") then -- bram_overflow <= '1'; -- end if; -- end if; -- end if; -- end process; -- -- -- -- timestamp and bunch counter -- -- bunch counter for logging purposes only... -- bc0: process(clk) -- begin -- if rising_edge(clk) then -- if reset_n = '0' then -- bc <= (others => '0'); -- timestamp <= (others => '0'); -- else -- if reset_bc_i = '1' then -- bc <= (others => '0'); -- else -- bc <= bc + '1'; -- end if; -- -- if reset_timestamp = '1' then -- timestamp <= (others => '0'); -- elsif timestamp /= conv_std_logic_vector(131071, timestamp'length) then -- timestamp <= timestamp + '1'; -- end if; -- end if; -- end if; -- end process bc0; -- -- reset_timestamp <= eventA or eventB; -- -- -- log request and message registers -- process(clk) -- begin -- if rising_edge(clk) then -- if reset_n = '0' or reset_req = '1' then -- eventA_log <= (others => '0'); -- eventB_log <= (others => '0'); -- info_log <= (others => '0'); -- eventA_req <= '0'; -- eventB_req <= '0'; -- info_req <= '0'; -- else -- -- -- Logging priority: channelA, then channelB, then Info event -- if eventA_written = '1' then -- eventA_req <= '0'; -- elsif eventB_written = '1' then -- eventB_req <= '0'; -- elsif info_written = '1' then -- info_req <= '0'; -- end if; -- -- -- eventA Bram entry format -- -- word0 firstword(17) & evntid(16..15) & '0' & typeA(13..12) & bunch_count(11..0) -- -- word1 zero(17) & timestamp(16..0) -- if eventA = '1' and halt_req = '0' then -- eventA_req <= '1'; -- eventA_log(17 downto 0) <= '1' & "01" & '0' & typeA & bc; -- eventA_log(35 downto 18) <= '0' & timestamp; -- end if; -- -- -- eventB Bram entry format -- -- word0 firstword(17) & evntid(16..15) & zero(14..12) & bunch_count(11..0) -- -- word1 (iac) zero(17) & fmt(16) & header(15..12) & data(11..0) -- -- word1 (brc) zero(17) & fmt(16) & zero(15..8) & data(7..0) -- -- word2 zero(17) & timestamp(16..0) -- if eventB = '1' and halt_req = '0' then -- eventB_req <= '1'; -- eventB_log(17 downto 0) <= '1' & "10" & "000" & bc; -- eventB_log(53 downto 36) <= '0' & timestamp; -- -- -- iac -- if chB_data_rdy = "10" then -- eventB_log(35 downto 18) <= '0' & '1' & chB_data(22 downto 7); -- -- brc -- elsif chB_data_rdy = "01" then -- eventB_log(35 downto 18) <= '0' & '0' & x"00" & chB_data(12 downto 5); -- else -- eventB_log(35 downto 18) <= '0' & '0' & x"FF" & x"00"; -- end if; -- end if; -- -- -- info entry format -- -- word0 firstword(17) & evntid(16..15) & info_code(14..12) & bunch_count(11..0) -- if info = '1' and halt_req = '0' then -- info_req <= '1'; -- info_log <= '1' & "11" & info_code & bc; -- end if; -- -- end if; -- end if; -- end process; -- -- -- ------------------------------------------------------------------------------ -- -- Logging trigger conditions and log selection -- -- ------------------------------------------------------------------------------ -- -- -- channel A events -- eventA <= (l0trigger_i or l1trigger_i or chA_decode_error_i) and (not ppc_ignore_chA); -- typeA <= "01" when l0trigger_i = '1' else -- "10" when l1trigger_i = '1' else -- "11" when chA_decode_error_i = '1' else -- "00"; -- -- -- channel B events -- chB_header <= chB_data(22 downto 19); -- chB_brc_data <= chB_data(12 downto 5); -- -- is_l1m_word <= '1' when (chB_header = L1M_H) or (chB_header = L1M_D) else '0'; -- is_l2a_word <= '1' when (chB_header = L2M_H) or (chB_header = L2M_D) else '0'; -- is_l2r_word <= '1' when (chB_header = L2M_R) else '0'; -- is_res_ctp_word <= '1' when (chB_header = RES_CTP0) or (chB_header = RES_CTP1) or -- (chB_header = RES_CTP2) or (chB_header = RES_CTP3) else -- '0'; -- is_brc_orbit <= '1' when (chB_brc_data = BRC_MSG_ORBIT) and (chB_data_rdy(0) = '1') else '0'; -- is_brc_prepulse <= '1' when (chB_brc_data = BRC_MSG_PREPULSE) and (chB_data_rdy(0) = '1') else '0'; -- is_brc_others <= '1' when (chB_brc_data /= BRC_MSG_ORBIT) and -- (chB_brc_data /= BRC_MSG_PREPULSE) and -- (chb_data_rdy(0) = '1') else '0'; -- -- -- IACs -- eventB_l1m <= (chB_data_rdy(1) and is_l1m_word) and (not ppc_ignore_l1m); -- eventB_l2a <= (chB_data_rdy(1) and is_l2a_word) and (not ppc_ignore_l2a); -- eventB_l2r <= (chB_data_rdy(1) and is_l2r_word) and (not ppc_ignore_l2r); -- eventB_res_ctp <= (chB_data_rdy(1) and is_res_ctp_word) and (not ppc_ignore_res_ctp); -- -- BRCs -- eventB_brc_orbit <= is_brc_orbit and (not ppc_ignore_brc_orbit); -- eventB_brc_prepulse <= is_brc_prepulse and (not ppc_ignore_brc_prepulse); -- eventB_brc_others <= is_brc_others and (not ppc_ignore_brc_others); -- -- eventB <= eventB_l1m or eventB_l2a or eventB_L2r or eventB_res_ctp or -- eventB_brc_orbit or eventB_brc_prepulse or eventB_brc_others; -- -- -- info events -- info_ctb1 <= (l1_message_rdy_i or sod_i or eod_i or l2atrigger_i or l2rtrigger_i) and (not ppc_ignore_msginfo); -- info_ctb0 <= (reset_bc_i or reset_ec_i) and (not ppc_ignore_brcinfo); -- info <= info_ctb1 or info_ctb0; -- -- process(l1_message_rdy_i, sod_i, eod_i, l2atrigger_i, l2rtrigger_i, reset_bc_i, reset_ec_i) -- begin -- if sod_i = '1' then info_code <= "001"; -- elsif eod_i = '1' then info_code <= "010"; -- elsif l2atrigger_i = '1' then info_code <= "011"; -- elsif l2rtrigger_i = '1' then info_code <= "100"; -- elsif l1_message_rdy_i = '1' then info_code <= "101"; -- elsif reset_bc_i = '1' then info_code <= "110"; -- elsif reset_ec_i = '1' then info_code <= "111"; -- else info_code <= (others => '0'); -- end if; -- end process; -- -- bram_wdata <= eventA_log(17 downto 0) when (bram_sel = x"1" and wcnt = x"0") else -- eventA_log(35 downto 18) when (bram_sel = x"1" and wcnt = x"1") else -- eventB_log(17 downto 0) when (bram_sel = x"2" and wcnt = x"0") else -- eventB_log(35 downto 18) when (bram_sel = x"2" and wcnt = x"1") else -- eventB_log(53 downto 36) when (bram_sel = x"2" and wcnt = x"2") else -- info_log when (bram_sel = x"3") else -- "00" & x"0000"; -- -- -- stop conditions -- stop_on_error <= (err_l1_message_i and (not ppc_log_mask(0))) or -- (err_l2a_message_i and (not ppc_log_mask(1))) or -- (err_unknown_addr_i and (not ppc_log_mask(2))); -- -- stop_on_debug <= (l2am_interrupted_i and (not ppc_log_mask(3))) or -- (l2m_consecutive_i and (not ppc_log_mask(4))); -- -- stop_on_ext_cond <= ttc_events_log_halt and (not ppc_log_mask(5)); -- -- halt_req <= ppc_halt_req or -- stop_on_ext_cond or -- stop_on_error or -- stop_on_debug; -- -- process(clk) -- begin -- if rising_edge(clk) then -- if reset_n = '0' or reset_req = '1' or cont_req = '1' then -- halt <= '0'; -- elsif halt_req = '1' then -- halt <= '1'; -- end if; -- end if; -- end process; ------------------------------------------------------------------------------ -- Channel A decoding -- ------------------------------------------------------------------------------ process(clk) begin if rising_edge(clk) then channelA_r <= channelA; channelA_r2 <= channelA_r; if reset_n = '0' then l0trigger_i <= '0'; l1trigger_i <= '0'; channelA_r <= '0'; else l0trigger_i <= '0'; l1trigger_i <= '0'; chA_decode_error_i <= '0'; if channelA_r2 = '0' then if channelA = '0' and channelA_r = '1' then l0trigger_i <= '1'; end if; if channelA = '1' and channelA_r = '1' then l1trigger_i <= '1'; end if; else -- channelA_r2 = '1' if channelA = '1' and channelA_r = '1' then chA_decode_error_i <= '1'; end if; end if; end if; end if; end process; ------------------------------------------------------------------------------ -- serial B receive shift register -- ------------------------------------------------------------------------------ serialb_com0: entity work.serialb_com generic map ( include_hamming => true) port map( clk => clk, reset_n => reset_n, serBchan => channelB, serB_en => channelB_on, testmode => testmode_on, single_bit_error => single_bit_error_i, double_bit_error => double_bit_error_i, communication_error => channelB_comm_error_i, data_ready => chB_data_rdy, data_out => chB_data); ------------------------------------------------------------------------------ -- channel B registers -- ------------------------------------------------------------------------------ channelB_reg0: entity work.channelB_reg port map ( clk => clk, reset_n => reset_n, data => chB_data, data_rdy => chB_data_rdy, l1m_strobe => l1m_strobe_i, -- strobes are compliant with the 'theory of errors' l2m_strobe => l2m_strobe_i, -- they're issued after the message header is received l2a => l2atrigger_i, -- l2a, l2r and roi_received also serve as message l2r => l2rtrigger_i, -- ready signals, for L2r: l2r = l2m_strobe (message ready and strobe identical) roi_received => open, err_l1_message => err_l1_message_i, err_l2a_message => err_l2a_message_i, err_roi_message => err_roi_message_i, err_bcid => err_bcid_i, err_cit => err_cit_i, err_unknown_addr => err_unknown_addr_i, l2am_interrupted => l2am_interrupted_i, -- for single event mode debugging l2m_consecutive => l2m_consecutive_i, -- for single event mode debugging l1_message => l1_message, l1_message_rdy => l1_message_rdy_i, l2a_message => l2a_message_i, l2r_message => l2r_message, roi_message => open, sod => sod_i, eod => eod_i, sod_eod_debug_up => sod_eod_debug_up, reset_bc => reset_bc_i, reset_ec => reset_ec_i ); end arc;